pwilczewski commited on
Commit
3d1690c
·
1 Parent(s): b7eb826
Files changed (1) hide show
  1. app.py +1 -1
app.py CHANGED
@@ -138,7 +138,7 @@ workflow.add_node("ARIMA", arima_node)
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  # conditional_edge to refit and the loop refit with resid?
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  workflow.add_edge(START, "EDA")
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- workflow.add_edge("EDA", END)
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  workflow.add_conditional_edges("PlotAnalysis", router)
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  workflow.add_edge("Difference", "EDA")
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  workflow.add_edge("ARIMA", END)
 
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  # conditional_edge to refit and the loop refit with resid?
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  workflow.add_edge(START, "EDA")
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+ workflow.add_edge("EDA", "PlotAnalysis")
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  workflow.add_conditional_edges("PlotAnalysis", router)
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  workflow.add_edge("Difference", "EDA")
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  workflow.add_edge("ARIMA", END)