text
stringlengths 2
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|---|---|
.messg "mcntl"
.subttl "mcntl"
.page
; Controller command in .a and job # in .y
lcc tsx ; save current stk pntr
stx savsp
lda #bit7
sta nextjob ; set no job flag
ldy #numjob ; include bam jobs
lcc0 lda jobs,y ; find a job
bmi prcmd ; ... a real job
lda cacheoff,y
and #all-bit7 ; leave offset into track cache
sta cacheoff,y ; clear translation flag
top dey ; try next one
bpl lcc0 ; next if no job's now
ldy nextjob
bpl start_ctl ; start job
jmp end_ctl ; do timing
.page
prcmd sty nextjob
tax ; job index
tya
asl a ; x2
sta hdrjob ; shifted nextjob
lda cmdindex,x ; translate for internal use
sta cindex ; save index
tax
lda ctl_cmd_info,x
sta info ; get information and save it
lda ctl_cmd_info1,x
sta info+1 ; get information and save it
jsr jtrans_ts ; translate logical track and sector to physical
1$ asl info ; cache operation ?
bcc 2$
jsr trk_in_mem ; is trk in memory ?, don't come back if it is...
2$ ldy nextjob
jmp top
.page
start_ctl
asl info ; start motor ?
bcc 1$
jsr start_mtr ; start motor
1$ asl info ; wait for motor up to speed ?
bcc 2$
jsr wait_mtr ; check mtr don't come back if drv not ready
2$ asl info ; logical seek required ?
bcc 3$
jsr seek ; seek - won't come back on an error
3$ asl info ; check dirty track cache flag ?
bcc 4$
lda dirty
bpl 4$ ; br, not dirty
lda cachetrk
sta cmdtrk ; want to go here
cmp drvtrk ; where are we?
bne 5$ ; br, step there first
lda cacheside
jsr sid_select ; select side
jmp wrtold_ctl ; handle dirty condition & write out old track
4$ asl info ; step?
bcc 6$
ldy hdrjob
lda hdrs2,y ; get address
sta cmdtrk ; want to go here
cmp drvtrk
beq 6$
5$ lda drvst ; set stepping mode
ora #bit6
sta drvst
jmp end_ctl ; do stepper stuff
6$ asl info ; select side
bcc 7$
lda tcacheside ; get translated side
jsr sid_select ; select side
7$ lda cindex ; get index
asl a ; x2
tax
lda ctl_cmd,x
sta ip+2
lda ctl_cmd+1,x
sta ip+3
jmp (ip+2) ; go do the command
.page
; Command Table Information
ctl_cmd_info
;bit 7 - Translate T & S ?
;bit 6 - Cache Op ?
;bit 5 - Start Motor ?
;bit 4 - Wait Motor ?
;bit 3 - Seek?
;bit 2 - Check Dirty Flag ?
;bit 1 - Step Required ?
;bit 0 - Select side?
bit7543=bit7+bit5+bit4+bit3
bit543=bit5+bit4+bit3
.byte all ; read sector* 1
.byte 0 ; reset disk controller 2
.byte bit5+bit4 ; motor on with spinup sequence 3
.byte 0 ; motor off with spin down sequence 4
.byte bit5 ; motor on 5
.byte 0 ; motor off 6
.byte bit5+bit4+bit1 ; move physical 7
.byte bit5+bit4 ; format side 8
.byte all ; write sector* 9
.byte bit5+bit4 ; disk present? 10
.byte 0 ; turn activity led on 11
.byte 0 ; turn activity led off 12
.byte 0 ; blink power led 13
.byte 0 ; disable power led blink 14
.byte 0 ; select side 15
.byte 0 ; buffer move 16
.byte bit7543+bit1+bit0 ; verify sector* 17
.byte bit5+bit4+bit3+bit2 ; dump track cache buffer 18
.byte all-bit7-bit6-bit2 ; read physical into buffer 19
.byte all-bit7-bit6-bit2 ; write physical from buffer 20
.byte all-bit7-bit6 ; move head to physical track 21
.byte bit5+bit4 ; seek any header* 22
.byte all-bit6-bit2 ; seek a particular header* 23
.byte bit5+bit4 ; restore head* 24
.byte 0 ; execute buffer* 25
.byte bit543+bit1 ; execute buffer w/ mtr on speed & on track* 26
.byte bit7+bit5+bit4+bit1 ; format disk 27
.byte all ; read sector notransfer 28
.byte all ; write sector notransfer 29
.byte all-bit7 ; read sector notranslate, notransfer 30
.byte all-bit7 ; write sector notranslate, notransfer 31
.byte bit5+bit4 ; check write protect status 32
.byte 0 ; syntax error 33
ctl_cmd_info1
;bit 7 - Bypass translate routine?
;bit 6 - Logical/Physical?
;bit 5 - Write/Read Operation?
;bit 4 - *** reserved ***
;bit 3 - *** reserved ***
;bit 2 - *** reserved ***
;bit 1 - *** reserved ***
;bit 0 - *** reserved ***
.byte 0 ; read sector* 1
.byte bit7 ; reset disk controller 2
.byte bit7 ; motor on with spinup sequence 3
.byte bit7 ; motor off with spin down sequence 4
.byte bit7 ; motor on 5
.byte bit7 ; motor off 6
.byte bit7 ; move physical 7
.byte 0 ; format side 8
.byte bit5 ; write sector* 9
.byte bit7 ; disk present? 10
.byte bit7 ; turn activity led on 11
.byte bit7 ; turn activity led off 12
.byte bit7 ; blink power led 13
.byte bit7 ; disable power led blink 14
.byte bit7 ; select side 15
.byte bit7 ; buffer move 16
.byte 0 ; verify sector* 17
.byte 0 ; dump track cache buffer 18
.byte bit6 ; read physical into buffer 19
.byte bit6+bit5 ; write physical from buffer 20
.byte 0 ; move head to physical track 21
.byte 0 ; seek any header* 22
.byte 0 ; seek a particular header* 23
.byte 0 ; restore head* 24
.byte 0 ; execute buffer* 25
.byte 0 ; execute buffer w/ mtr on speed & on track* 26
.byte 0 ; format disk 27
.byte bit6 ; read sector notransfer 28
.byte bit6+bit5 ; write sector notransfer 29
.byte bit6 ; read sector notranslation, notransfer 30
.byte bit6+bit5 ; write sector notranslation, notransfer 31
.byte bit7 ; check write protect status 32
.byte bit7 ; syntax error 33
; Command Indirects
ctl_cmd
.word read_ctl ; read from track cache buffer* 1
.word reset_ctl ; reset disk controller 2
.word moton_ctl ; motor on with spinup sequence 3
.word motoff_ctl ; motor off with spin down sequence 4
.word motoni_ctl ; motor on 5
.word motoffi_ctl ; motor off 6
.word seek_ctl ; move physical 7
.word format_ctl ; format side 8
.word wrtsd_ctl ; write to track cache buffer* 9
.word diskin_ctl ; disk present? 10
.word ledacton_ctl ; turn activity led on 11
.word ledactoff_ctl ; turn activity led off 12
.word errledon_ctl ; blink power led 13
.word errledoff_ctl ; disable power led blink 14
.word side_ctl ; select side 15
.word bufmove_ctl ; buffer move 16
.word wrtver_ctl ; verify track cache buffer 17
.word trkwrt_ctl ; track cache dump 18
.word spread_ctl ; read notrx in buffer 19
.word spwrt_ctl ; wrt notrx in buffer 20
.word pseek_ctl ; move head to physical track 21
.word seekhd_ctl ; seek any header* 22
.word seekphd_ctl ; seek a particular header 23
.word restore_ctl ; restore head* 24
.word jumpc_ctl ; execute buffer* 25
.word exbuf_ctl ; execute buffer w/ mtr on speed & on track* 26
.word formatdk_ctl ; format disk 27
.word read_ctl ; read from track 28
.word wrtsd_ctl ; write to track 29
.word pread_ctl ; read physical address 30
.word pwrt_ctl ; write physical address 31
.word detwp_ctl ; check write protect status 32
.word syntaxer ; syntax error 33
ctllen= *-ctl_cmd
.page
; Index for Jobs
cmdindex
.byte $20 ; 0
.byte $20 ; 1
.byte $20 ; 2
.byte $20 ; 3
.byte $20 ; 4
.byte $20 ; 5
.byte $20 ; 6
.byte $20 ; 7
.byte $20 ; 8
.byte $20 ; 9
.byte $20 ; a
.byte $20 ; b
.byte $20 ; c
.byte $20 ; d
.byte $20 ; e
.byte $20 ; f
.byte $20 ; 10
.byte $20 ; 11
.byte $20 ; 12
.byte $20 ; 13
.byte $20 ; 14
.byte $20 ; 15
.byte $20 ; 16
.byte $20 ; 17
.byte $20 ; 18
.byte $20 ; 19
.byte $20 ; 1a
.byte $20 ; 1b
.byte $20 ; 1c
.byte $20 ; 1d
.byte $20 ; 1e
.byte $20 ; 1f
.byte $20 ; 20
.byte $20 ; 21
.byte $20 ; 22
.byte $20 ; 23
.byte $20 ; 24
.byte $20 ; 25
.byte $20 ; 26
.byte $20 ; 27
.byte $20 ; 28
.byte $20 ; 29
.byte $20 ; 2a
.byte $20 ; 2b
.byte $20 ; 2c
.byte $20 ; 2d
.byte $20 ; 2e
.byte $20 ; 2f
.byte $20 ; 30
.byte $20 ; 31
.byte $20 ; 32
.byte $20 ; 33
.byte $20 ; 34
.byte $20 ; 35
.byte $20 ; 36
.byte $20 ; 37
.byte $20 ; 38
.byte $20 ; 39
.byte $20 ; 3a
.byte $20 ; 3b
.byte $20 ; 3c
.byte $20 ; 3d
.byte $20 ; 3e
.byte $20 ; 3f
.byte $20 ; 40
.byte $20 ; 41
.byte $20 ; 42
.byte $20 ; 43
.byte $20 ; 44
.byte $20 ; 45
.byte $20 ; 46
.byte $20 ; 47
.byte $20 ; 48
.byte $20 ; 49
.byte $20 ; 4a
.byte $20 ; 4b
.byte $20 ; 4c
.byte $20 ; 4d
.byte $20 ; 4e
.byte $20 ; 4f
.byte $20 ; 50
.byte $20 ; 51
.byte $20 ; 52
.byte $20 ; 53
.byte $20 ; 54
.byte $20 ; 55
.byte $20 ; 56
.byte $20 ; 57
.byte $20 ; 58
.byte $20 ; 59
.byte $20 ; 5a
.byte $20 ; 5b
.byte $20 ; 5c
.byte $20 ; 5d
.byte $20 ; 5e
.byte $20 ; 5f
.byte $20 ; 60
.byte $20 ; 61
.byte $20 ; 62
.byte $20 ; 63
.byte $20 ; 64
.byte $20 ; 65
.byte $20 ; 66
.byte $20 ; 67
.byte $20 ; 68
.byte $20 ; 69
.byte $20 ; 6a
.byte $20 ; 6b
.byte $20 ; 6c
.byte $20 ; 6d
.byte $20 ; 6e
.byte $20 ; 6f
.byte $20 ; 70
.byte $20 ; 71
.byte $20 ; 72
.byte $20 ; 73
.byte $20 ; 74
.byte $20 ; 75
.byte $20 ; 76
.byte $20 ; 77
.byte $20 ; 78
.byte $20 ; 79
.byte $20 ; 7a
.byte $20 ; 7b
.byte $20 ; 7c
.byte $20 ; 7d
.byte $20 ; 7e
.byte $20 ; 7f
.byte $00 ; 80 read*
.byte $20 ; 81
.byte $01 ; 82 reset
.byte $20 ; 83
.byte $02 ; 84 moton
.byte $20 ; 85
.byte $03 ; 86 motoff
.byte $20 ; 87
.byte $04 ; 88 motoni
.byte $20 ; 89
.byte $05 ; 8a motoffi
.byte $20 ; 8b
.byte $06 ; 8c seek
.byte $20 ; 8d
.byte $07 ; 8e format side
.byte $20 ; 8f
.byte $08 ; 90 write*
.byte $20 ; 91
.byte $09 ; 92 diskin
.byte $20 ; 93
.byte $0a ; 94 ledacton
.byte $20 ; 95
.byte $0b ; 96 ledactoff
.byte $20 ; 97
.byte $0c ; 98 errledon
.byte $20 ; 99
.byte $0d ; 9a errledoff
.byte $20 ; 9b
.byte $0e ; 9c sidesel
.byte $20 ; 9d
.byte $0f ; 9e bufmove
.byte $20 ; 9f
.byte $10 ; a0 verify*
.byte $20 ; a1
.byte $11 ; a2 trkwrt
.byte $20 ; a3
.byte $12 ; a4 spread
.byte $20 ; a5
.byte $13 ; a6 spwrt
.byte $20 ; a7
.byte $14 ; a8 pseek
.byte $20 ; a9
.byte $1b ; aa read notrx
.byte $20 ; ab
.byte $1c ; ac write notrx
.byte $20 ; ad
.byte $20 ; ae
.byte $20 ; af
.byte $15 ; b0 seek*
.byte $20 ; b1
.byte $1d ; b2 read notransl, notrx
.byte $20 ; b3
.byte $1e ; b4 write notransl, notrx
.byte $20 ; b5
.byte $1f ; b6 check write protect status
.byte $20 ; b7
.byte $16 ; b8 seekparticular*
.byte $20 ; b9
.byte $20 ; ba
.byte $20 ; bb
.byte $20 ; bc
.byte $20 ; bd
.byte $20 ; be
.byte $20 ; bf
.byte $17 ; c0 bump*
.byte $20 ; c1
.byte $20 ; c2
.byte $20 ; c3
.byte $20 ; c4
.byte $20 ; c5
.byte $20 ; c6
.byte $20 ; c7
.byte $20 ; c8
.byte $20 ; c9
.byte $20 ; ca
.byte $20 ; cb
.byte $20 ; cc
.byte $20 ; cd
.byte $20 ; ce
.byte $20 ; cf
.byte $18 ; d0 jumpc*
.byte $20 ; d1
.byte $20 ; d2
.byte $20 ; d3
.byte $20 ; d4
.byte $20 ; d5
.byte $20 ; d6
.byte $20 ; d7
.byte $20 ; d8
.byte $20 ; d9
.byte $20 ; da
.byte $20 ; db
.byte $20 ; dc
.byte $20 ; dd
.byte $20 ; de
.byte $20 ; df
.byte $19 ; e0 exbuf*
.byte $20 ; e1
.byte $20 ; e2
.byte $20 ; e3
.byte $20 ; e4
.byte $20 ; e5
.byte $20 ; e6
.byte $20 ; e7
.byte $20 ; e8
.byte $20 ; e9
.byte $20 ; ea
.byte $20 ; eb
.byte $20 ; ec
.byte $20 ; ed
.byte $20 ; ee
.byte $20 ; ef
.byte $1a ; f0 format
.byte $20 ; f1
.byte $20 ; f2
.byte $20 ; f3
.byte $20 ; f4
.byte $20 ; f5
.byte $20 ; f6
.byte $20 ; f7
.byte $20 ; f8
.byte $20 ; f9
.byte $20 ; fa
.byte $20 ; fb
.byte $20 ; fc
.byte $20 ; fd
.byte $20 ; fe
.byte $20 ; ff
| {
"language": "Assembly"
} |
// Scilab ( http://www.scilab.org/ ) - This file is part of Scilab
// Copyright (C) 2018 - Samuel GOUGEON
//
// Copyright (C) 2012 - 2016 - Scilab Enterprises
//
// This file is hereby licensed under the terms of the GNU GPL v2.0,
// pursuant to article 5.3.4 of the CeCILL v.2.1.
// This file was originally licensed under the terms of the CeCILL v2.1,
// and continues to be available under such terms.
// For more information, see the COPYING file which you should have received
// along with this program.
function i = mtlb_uint16(x)
// Emulation function for Matlab uint16()
if type(x)==4 then
i = uint16(x*1)
else
if type(x)==1
if ~isreal(x)
x = real(x)
end
x(isnan(x)) = 0
end
i = uint16(max(min(round(x),65535),0))
end
endfunction
| {
"language": "Assembly"
} |
glabel func_80A3B678
/* 00F28 80A3B678 27BDFFE8 */ addiu $sp, $sp, 0xFFE8 ## $sp = FFFFFFE8
/* 00F2C 80A3B67C AFBF0014 */ sw $ra, 0x0014($sp)
/* 00F30 80A3B680 AFA5001C */ sw $a1, 0x001C($sp)
/* 00F34 80A3B684 84A201CA */ lh $v0, 0x01CA($a1) ## 000001CA
/* 00F38 80A3B688 24010005 */ addiu $at, $zero, 0x0005 ## $at = 00000005
/* 00F3C 80A3B68C 10410009 */ beq $v0, $at, .L80A3B6B4
/* 00F40 80A3B690 2401000A */ addiu $at, $zero, 0x000A ## $at = 0000000A
/* 00F44 80A3B694 1041000B */ beq $v0, $at, .L80A3B6C4
/* 00F48 80A3B698 24010014 */ addiu $at, $zero, 0x0014 ## $at = 00000014
/* 00F4C 80A3B69C 1041000D */ beq $v0, $at, .L80A3B6D4
/* 00F50 80A3B6A0 2401001E */ addiu $at, $zero, 0x001E ## $at = 0000001E
/* 00F54 80A3B6A4 1041000F */ beq $v0, $at, .L80A3B6E4
/* 00F58 80A3B6A8 00000000 */ nop
/* 00F5C 80A3B6AC 10000010 */ beq $zero, $zero, .L80A3B6F0
/* 00F60 80A3B6B0 8FAF001C */ lw $t7, 0x001C($sp)
.L80A3B6B4:
/* 00F64 80A3B6B4 0C021344 */ jal Item_Give
/* 00F68 80A3B6B8 2405008E */ addiu $a1, $zero, 0x008E ## $a1 = 0000008E
/* 00F6C 80A3B6BC 1000000C */ beq $zero, $zero, .L80A3B6F0
/* 00F70 80A3B6C0 8FAF001C */ lw $t7, 0x001C($sp)
.L80A3B6C4:
/* 00F74 80A3B6C4 0C021344 */ jal Item_Give
/* 00F78 80A3B6C8 2405008F */ addiu $a1, $zero, 0x008F ## $a1 = 0000008F
/* 00F7C 80A3B6CC 10000008 */ beq $zero, $zero, .L80A3B6F0
/* 00F80 80A3B6D0 8FAF001C */ lw $t7, 0x001C($sp)
.L80A3B6D4:
/* 00F84 80A3B6D4 0C021344 */ jal Item_Give
/* 00F88 80A3B6D8 24050090 */ addiu $a1, $zero, 0x0090 ## $a1 = 00000090
/* 00F8C 80A3B6DC 10000004 */ beq $zero, $zero, .L80A3B6F0
/* 00F90 80A3B6E0 8FAF001C */ lw $t7, 0x001C($sp)
.L80A3B6E4:
/* 00F94 80A3B6E4 0C021344 */ jal Item_Give
/* 00F98 80A3B6E8 24050091 */ addiu $a1, $zero, 0x0091 ## $a1 = 00000091
/* 00F9C 80A3B6EC 8FAF001C */ lw $t7, 0x001C($sp)
.L80A3B6F0:
/* 00FA0 80A3B6F0 85E401C8 */ lh $a0, 0x01C8($t7) ## 000001C8
/* 00FA4 80A3B6F4 00042023 */ subu $a0, $zero, $a0
/* 00FA8 80A3B6F8 00042400 */ sll $a0, $a0, 16
/* 00FAC 80A3B6FC 0C021CC3 */ jal Rupees_ChangeBy
/* 00FB0 80A3B700 00042403 */ sra $a0, $a0, 16
/* 00FB4 80A3B704 8FBF0014 */ lw $ra, 0x0014($sp)
/* 00FB8 80A3B708 27BD0018 */ addiu $sp, $sp, 0x0018 ## $sp = 00000000
/* 00FBC 80A3B70C 03E00008 */ jr $ra
/* 00FC0 80A3B710 00000000 */ nop
| {
"language": "Assembly"
} |
;
; S-OS specific routines
; by Stefano Bodrato, 2013
;
; Set the cursor position
;
; int __CALLEE__ setcursorpos_callee(x,y);
;
;
; $Id: setcursorpos_callee.asm,v 1.5 2016-06-19 20:58:00 dom Exp $
;
SECTION code_clib
PUBLIC setcursorpos_callee
PUBLIC _setcursorpos_callee
PUBLIC ASMDISP_SETCURSORPOS_CALLEE
setcursorpos_callee:
_setcursorpos_callee:
pop bc
pop hl
pop de
push bc
; enter : l = x
; e = y
.asmentry
;jr asmentry
ld h,e
jp $201E
DEFC ASMDISP_SETCURSORPOS_CALLEE = asmentry - setcursorpos_callee
| {
"language": "Assembly"
} |
.setcpu "6502"
.export nmi_int, irq_int ; Used by lib/vectors.s
.export _isr_jump_table ; Used by lib/sys_irq.c
.import timer_isr ; See lib/timer_isr.s
.import kbd_isr ; See lib/kbd_isr.s
; These must be the same addresses defined in prog/memorymap.h
IRQ_STATUS = $7FFF
IRQ_MASK = $7FDF
.segment "BSS"
tmp1:
.byte 0
tmp2:
.byte 0
tmp3:
.byte 0, 0
.segment "ZEROPAGE"
isr_ptr:
.byte 0, 0 ; This is temporary scratch space.
.segment "DATA"
_isr_jump_table:
.addr timer_isr ; IRQ 0 (TIMER)
.addr unhandled_irq ; IRQ 1 (VGA)
.addr kbd_isr ; IRQ 2 (Keyboard)
.addr unhandled_irq ; IRQ 3 (Reserved)
.addr unhandled_irq ; IRQ 4 (Reserved)
.addr unhandled_irq ; IRQ 5 (Reserved)
.addr unhandled_irq ; IRQ 6 (Reserved)
.addr unhandled_irq ; IRQ 7 (Reserved)
.segment "CODE"
; Unhandled interrupts just return immediately.
unhandled_irq:
RTS
nmi_int:
RTI ; NMI is not implemented. Just return.
irq_int:
PHA
TXA
PHA
TYA
PHA
LDA IRQ_STATUS ; Reading the IRQ status clears it.
AND IRQ_MASK ; Mask off any disabled interrupts.
LDY #$00 ; Start from bit 0
loop:
LSR ; Shift current bit to carry
BCC next_irq ; Jump if current bit is clear
LDX _isr_jump_table,Y ; Load interrupt vector from table
STX isr_ptr ; and store in temporary pointer
LDX _isr_jump_table+1,Y
STX isr_ptr+1
JSR jmp_isr_ptr ; Jump indirectly to interrupt service routine, see below.
; The A and Y registers MUST be preserved.
next_irq:
TAX ; Optimization: If no more interrupts, quickly skip to the end.
BEQ end
INY
INY
CPY #$10 ; More interrupts?
BNE loop ; Jump back if so.
end:
PLA
TAY
PLA
TAX
PLA
RTI
jmp_isr_ptr:
JMP (isr_ptr)
| {
"language": "Assembly"
} |
/* Copyright (c) 1996-2018, OPC Foundation. All rights reserved.
The source code in this file is covered under a dual-license scenario:
- RCL: for OPC Foundation members in good-standing
- GPL V2: everybody else
RCL license terms accompanied with this source code. See http://opcfoundation.org/License/RCL/1.00/
GNU General Public License as published by the Free Software Foundation;
version 2 of the License are accompanied with this source code. See http://opcfoundation.org/License/GPLv2
This source code is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
#if OPCUA_MUTEX_ERROR_CHECKING
#define OPCUA_P_MUTEX_CREATE(xMutex) OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexCreate( xMutex, __FILE__, __LINE__)
#define OPCUA_P_MUTEX_DELETE(xMutex) OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexDelete( xMutex, __FILE__, __LINE__)
#define OPCUA_P_MUTEX_LOCK(xMutex) OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexLock( xMutex, __FILE__, __LINE__)
#define OPCUA_P_MUTEX_UNLOCK(xMutex) OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexUnlock( xMutex, __FILE__, __LINE__)
#else /* OPCUA_MUTEX_ERROR_CHECKING */
#if OPCUA_USE_SYNCHRONISATION
#define OPCUA_P_MUTEX_CREATE OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexCreate
#define OPCUA_P_MUTEX_DELETE OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexDelete
#define OPCUA_P_MUTEX_LOCK OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexLock
#define OPCUA_P_MUTEX_UNLOCK OpcUa_ProxyStub_g_PlatformLayerCalltable->MutexUnlock
#else /* OPCUA_USE_SYNCHRONISATION */
#define OPCUA_P_MUTEX_CREATE(xMutex) OpcUa_Good
#define OPCUA_P_MUTEX_DELETE(xMutex)
#define OPCUA_P_MUTEX_LOCK(xMutex)
#define OPCUA_P_MUTEX_UNLOCK(xMutex)
#endif /* OPCUA_USE_SYNCHRONISATION */
#endif /* OPCUA_MUTEX_ERROR_CHECKING */
| {
"language": "Assembly"
} |
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
revh z0.s, p7/m, z31.s
// CHECK-INST: revh z0.s, p7/m, z31.s
// CHECK-ENCODING: [0xe0,0x9f,0xa5,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f a5 05 <unknown>
revh z0.d, p7/m, z31.d
// CHECK-INST: revh z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e5 05 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0.d, p7/z, z7.d
// CHECK-INST: movprfx z0.d, p7/z, z7.d
// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
revh z0.d, p7/m, z31.d
// CHECK-INST: revh z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e5 05 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
revh z0.d, p7/m, z31.d
// CHECK-INST: revh z0.d, p7/m, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f e5 05 <unknown>
| {
"language": "Assembly"
} |
/*****************************************************************
|
| Neptune - Trust Anchors
|
| This file is automatically generated by a script, do not edit!
|
| Copyright (c) 2002-2010, Axiomatic Systems, LLC.
| All rights reserved.
|
| Redistribution and use in source and binary forms, with or without
| modification, are permitted provided that the following conditions are met:
| * Redistributions of source code must retain the above copyright
| notice, this list of conditions and the following disclaimer.
| * Redistributions in binary form must reproduce the above copyright
| notice, this list of conditions and the following disclaimer in the
| documentation and/or other materials provided with the distribution.
| * Neither the name of Axiomatic Systems nor the
| names of its contributors may be used to endorse or promote products
| derived from this software without specific prior written permission.
|
| THIS SOFTWARE IS PROVIDED BY AXIOMATIC SYSTEMS ''AS IS'' AND ANY
| EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
| WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
| DISCLAIMED. IN NO EVENT SHALL AXIOMATIC SYSTEMS BE LIABLE FOR ANY
| DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
| (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
| LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
| ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
| SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
****************************************************************/
/* TC TrustCenter Universal CA I */
const unsigned char NptTlsTrustAnchor_Base_0124_Data[993] = {
0x30,0x82,0x03,0xdd,0x30,0x82,0x02,0xc5
,0xa0,0x03,0x02,0x01,0x02,0x02,0x0e,0x1d
,0xa2,0x00,0x01,0x00,0x02,0xec,0xb7,0x60
,0x80,0x78,0x8d,0xb6,0x06,0x30,0x0d,0x06
,0x09,0x2a,0x86,0x48,0x86,0xf7,0x0d,0x01
,0x01,0x05,0x05,0x00,0x30,0x79,0x31,0x0b
,0x30,0x09,0x06,0x03,0x55,0x04,0x06,0x13
,0x02,0x44,0x45,0x31,0x1c,0x30,0x1a,0x06
,0x03,0x55,0x04,0x0a,0x13,0x13,0x54,0x43
,0x20,0x54,0x72,0x75,0x73,0x74,0x43,0x65
,0x6e,0x74,0x65,0x72,0x20,0x47,0x6d,0x62
,0x48,0x31,0x24,0x30,0x22,0x06,0x03,0x55
,0x04,0x0b,0x13,0x1b,0x54,0x43,0x20,0x54
,0x72,0x75,0x73,0x74,0x43,0x65,0x6e,0x74
,0x65,0x72,0x20,0x55,0x6e,0x69,0x76,0x65
,0x72,0x73,0x61,0x6c,0x20,0x43,0x41,0x31
,0x26,0x30,0x24,0x06,0x03,0x55,0x04,0x03
,0x13,0x1d,0x54,0x43,0x20,0x54,0x72,0x75
,0x73,0x74,0x43,0x65,0x6e,0x74,0x65,0x72
,0x20,0x55,0x6e,0x69,0x76,0x65,0x72,0x73
,0x61,0x6c,0x20,0x43,0x41,0x20,0x49,0x30
,0x1e,0x17,0x0d,0x30,0x36,0x30,0x33,0x32
,0x32,0x31,0x35,0x35,0x34,0x32,0x38,0x5a
,0x17,0x0d,0x32,0x35,0x31,0x32,0x33,0x31
,0x32,0x32,0x35,0x39,0x35,0x39,0x5a,0x30
,0x79,0x31,0x0b,0x30,0x09,0x06,0x03,0x55
,0x04,0x06,0x13,0x02,0x44,0x45,0x31,0x1c
,0x30,0x1a,0x06,0x03,0x55,0x04,0x0a,0x13
,0x13,0x54,0x43,0x20,0x54,0x72,0x75,0x73
,0x74,0x43,0x65,0x6e,0x74,0x65,0x72,0x20
,0x47,0x6d,0x62,0x48,0x31,0x24,0x30,0x22
,0x06,0x03,0x55,0x04,0x0b,0x13,0x1b,0x54
,0x43,0x20,0x54,0x72,0x75,0x73,0x74,0x43
,0x65,0x6e,0x74,0x65,0x72,0x20,0x55,0x6e
,0x69,0x76,0x65,0x72,0x73,0x61,0x6c,0x20
,0x43,0x41,0x31,0x26,0x30,0x24,0x06,0x03
,0x55,0x04,0x03,0x13,0x1d,0x54,0x43,0x20
,0x54,0x72,0x75,0x73,0x74,0x43,0x65,0x6e
,0x74,0x65,0x72,0x20,0x55,0x6e,0x69,0x76
,0x65,0x72,0x73,0x61,0x6c,0x20,0x43,0x41
,0x20,0x49,0x30,0x82,0x01,0x22,0x30,0x0d
,0x06,0x09,0x2a,0x86,0x48,0x86,0xf7,0x0d
,0x01,0x01,0x01,0x05,0x00,0x03,0x82,0x01
,0x0f,0x00,0x30,0x82,0x01,0x0a,0x02,0x82
,0x01,0x01,0x00,0xa4,0x77,0x23,0x96,0x44
,0xaf,0x90,0xf4,0x31,0xa7,0x10,0xf4,0x26
,0x87,0x9c,0xf3,0x38,0xd9,0x0f,0x5e,0xde
,0xcf,0x41,0xe8,0x31,0xad,0xc6,0x74,0x91
,0x24,0x96,0x78,0x1e,0x09,0xa0,0x9b,0x9a
,0x95,0x4a,0x4a,0xf5,0x62,0x7c,0x02,0xa8
,0xca,0xac,0xfb,0x5a,0x04,0x76,0x39,0xde
,0x5f,0xf1,0xf9,0xb3,0xbf,0xf3,0x03,0x58
,0x55,0xd2,0xaa,0xb7,0xe3,0x04,0x22,0xd1
,0xf8,0x94,0xda,0x22,0x08,0x00,0x8d,0xd3
,0x7c,0x26,0x5d,0xcc,0x77,0x79,0xe7,0x2c
,0x78,0x39,0xa8,0x26,0x73,0x0e,0xa2,0x5d
,0x25,0x69,0x85,0x4f,0x55,0x0e,0x9a,0xef
,0xc6,0xb9,0x44,0xe1,0x57,0x3d,0xdf,0x1f
,0x54,0x22,0xe5,0x6f,0x65,0xaa,0x33,0x84
,0x3a,0xf3,0xce,0x7a,0xbe,0x55,0x97,0xae
,0x8d,0x12,0x0f,0x14,0x33,0xe2,0x50,0x70
,0xc3,0x49,0x87,0x13,0xbc,0x51,0xde,0xd7
,0x98,0x12,0x5a,0xef,0x3a,0x83,0x33,0x92
,0x06,0x75,0x8b,0x92,0x7c,0x12,0x68,0x7b
,0x70,0x6a,0x0f,0xb5,0x9b,0xb6,0x77,0x5b
,0x48,0x59,0x9d,0xe4,0xef,0x5a,0xad,0xf3
,0xc1,0x9e,0xd4,0xd7,0x45,0x4e,0xca,0x56
,0x34,0x21,0xbc,0x3e,0x17,0x5b,0x6f,0x77
,0x0c,0x48,0x01,0x43,0x29,0xb0,0xdd,0x3f
,0x96,0x6e,0xe6,0x95,0xaa,0x0c,0xc0,0x20
,0xb6,0xfd,0x3e,0x36,0x27,0x9c,0xe3,0x5c
,0xcf,0x4e,0x81,0xdc,0x19,0xbb,0x91,0x90
,0x7d,0xec,0xe6,0x97,0x04,0x1e,0x93,0xcc
,0x22,0x49,0xd7,0x97,0x86,0xb6,0x13,0x0a
,0x3c,0x43,0x23,0x77,0x7e,0xf0,0xdc,0xe6
,0xcd,0x24,0x1f,0x3b,0x83,0x9b,0x34,0x3a
,0x83,0x34,0xe3,0x02,0x03,0x01,0x00,0x01
,0xa3,0x63,0x30,0x61,0x30,0x1f,0x06,0x03
,0x55,0x1d,0x23,0x04,0x18,0x30,0x16,0x80
,0x14,0x92,0xa4,0x75,0x2c,0xa4,0x9e,0xbe
,0x81,0x44,0xeb,0x79,0xfc,0x8a,0xc5,0x95
,0xa5,0xeb,0x10,0x75,0x73,0x30,0x0f,0x06
,0x03,0x55,0x1d,0x13,0x01,0x01,0xff,0x04
,0x05,0x30,0x03,0x01,0x01,0xff,0x30,0x0e
,0x06,0x03,0x55,0x1d,0x0f,0x01,0x01,0xff
,0x04,0x04,0x03,0x02,0x01,0x86,0x30,0x1d
,0x06,0x03,0x55,0x1d,0x0e,0x04,0x16,0x04
,0x14,0x92,0xa4,0x75,0x2c,0xa4,0x9e,0xbe
,0x81,0x44,0xeb,0x79,0xfc,0x8a,0xc5,0x95
,0xa5,0xeb,0x10,0x75,0x73,0x30,0x0d,0x06
,0x09,0x2a,0x86,0x48,0x86,0xf7,0x0d,0x01
,0x01,0x05,0x05,0x00,0x03,0x82,0x01,0x01
,0x00,0x28,0xd2,0xe0,0x86,0xd5,0xe6,0xf8
,0x7b,0xf0,0x97,0xdc,0x22,0x6b,0x3b,0x95
,0x14,0x56,0x0f,0x11,0x30,0xa5,0x9a,0x4f
,0x3a,0xb0,0x3a,0xe0,0x06,0xcb,0x65,0xf5
,0xed,0xc6,0x97,0x27,0xfe,0x25,0xf2,0x57
,0xe6,0x5e,0x95,0x8c,0x3e,0x64,0x60,0x15
,0x5a,0x7f,0x2f,0x0d,0x01,0xc5,0xb1,0x60
,0xfd,0x45,0x35,0xcf,0xf0,0xb2,0xbf,0x06
,0xd9,0xef,0x5a,0xbe,0xb3,0x62,0x21,0xb4
,0xd7,0xab,0x35,0x7c,0x53,0x3e,0xa6,0x27
,0xf1,0xa1,0x2d,0xda,0x1a,0x23,0x9d,0xcc
,0xdd,0xec,0x3c,0x2d,0x9e,0x27,0x34,0x5d
,0x0f,0xc2,0x36,0x79,0xbc,0xc9,0x4a,0x62
,0x2d,0xed,0x6b,0xd9,0x7d,0x41,0x43,0x7c
,0xb6,0xaa,0xca,0xed,0x61,0xb1,0x37,0x82
,0x15,0x09,0x1a,0x8a,0x16,0x30,0xd8,0xec
,0xc9,0xd6,0x47,0x72,0x78,0x4b,0x10,0x46
,0x14,0x8e,0x5f,0x0e,0xaf,0xec,0xc7,0x2f
,0xab,0x10,0xd7,0xb6,0xf1,0x6e,0xec,0x86
,0xb2,0xc2,0xe8,0x0d,0x92,0x73,0xdc,0xa2
,0xf4,0x0f,0x3a,0xbf,0x61,0x23,0x10,0x89
,0x9c,0x48,0x40,0x6e,0x70,0x00,0xb3,0xd3
,0xba,0x37,0x44,0x58,0x11,0x7a,0x02,0x6a
,0x88,0xf0,0x37,0x34,0xf0,0x19,0xe9,0xac
,0xd4,0x65,0x73,0xf6,0x69,0x8c,0x64,0x94
,0x3a,0x79,0x85,0x29,0xb0,0x16,0x2b,0x0c
,0x82,0x3f,0x06,0x9c,0xc7,0xfd,0x10,0x2b
,0x9e,0x0f,0x2c,0xb6,0x9e,0xe3,0x15,0xbf
,0xd9,0x36,0x1c,0xba,0x25,0x1a,0x52,0x3d
,0x1a,0xec,0x22,0x0c,0x1c,0xe0,0xa4,0xa2
,0x3d,0xf0,0xe8,0x39,0xcf,0x81,0xc0,0x7b
,0xed,0x5d,0x1f,0x6f,0xc5,0xd0,0x0b,0xd7
,0x98};
const unsigned int NptTlsTrustAnchor_Base_0124_Size = 993;
| {
"language": "Assembly"
} |
// Copyright 2016 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build amd64,!gccgo,!appengine
#include "textflag.h"
// func hasAESNI() bool
TEXT ·hasAESNI(SB),NOSPLIT,$0
XORQ AX, AX
INCL AX
CPUID
SHRQ $25, CX
ANDQ $1, CX
MOVB CX, ret+0(FP)
RET
| {
"language": "Assembly"
} |
.PAGE 'TST3'
;
;
; .A=#BUFFERS NEEDED
; SETS UP BUFFER # AND ALLOCATES LINDX
GETWCH
SEC ;SET .C=1 INDICATE WRITE
BCS GETR2
GETRCH
CLC ;SET .C=0 INDICATE READ
GETR2
PHP ;SAVE R/W FLAG (.C)
STA TEMP ;SAVE #BUFS NEEDED
JSR FRECHN ;FREE ANY CHANNELS
JSR FNDLNX ; GET NEXT LINDX OPEN
STA LINDX
LDX SA
PLP
BCC GETR55
GETR52 ORA #$80
GETR55 STA LINTAB,X ;SAVE LINDX IN LINTAB
GETBF
AND #$3F
TAY ;NOW GET THE BUFFERS
LDA #$FF
STA BUF0,Y
STA BUF1,Y
STA SS,Y
GETR3 DEC TEMP
BMI GETR4
JSR GETBUF
BPL GETR5
GBERR JSR RELBUF ; ERROR ,REL BUFS
LDA #NOCHNL
JMP CMDERR
GETR5 STA BUF0,Y
DEC TEMP
BMI GETR4
JSR GETBUF
BMI GBERR
STA BUF1,Y
GETR4 RTS
;
; FREE CHANL ASSOCIATED WITH SA
; FREE READ AND WRITE CHANLS
; DONT FREE CHANL 15
FRECHN LDA SA
CMP #$F
BNE FRECO
RTS
.SKIP
FRECO
FRERD
FREWRT LDX SA
LDA LINTAB,X
CMP #$FF
BEQ FRE25
AND #$3F
STA LINDX
LDA #$FF
STA LINTAB,X
LDX LINDX
LDA #0
STA CHNRDY,X
JSR RELBUF
;
; RELEASE THE LINDX
;
RELINX LDX LINDX
LDA #1
REL15 DEX
BMI REL10
ASL A
BNE REL15
REL10 ORA LINUSE ;1=FREE 0=USED
STA LINUSE
FRE25 RTS
; GIVEN SA , FREE ITS READ CHANL
;
;
; RELEASE BUFFERS (LINDX)
;
RELBUF LDX LINDX
LDA BUF0,X
CMP #$FF
BEQ REL1
PHA
LDA #$FF
STA BUF0,X
PLA
JSR FREBUF
REL1 LDX LINDX
LDA BUF1,X
CMP #$FF
BEQ REL2
PHA
LDA #$FF
STA BUF1,X
PLA
JSR FREBUF
REL2 LDX LINDX
LDA SS,X
CMP #$FF
BEQ REL3
PHA
LDA #$FF
STA SS,X
PLA
JSR FREBUF
REL3 RTS
;
; GET A FREE BUFFER #
;
; REGS DESTROYED: .A .X
; OUT: .A,.X= BUF # OR $FF IF FAILED
; .N= 1 IF FAILED
;
; IF SUCCESSFUL INIT JOBS & LSTJOB
;
GETBUF
TYA ;SAVE .Y
PHA
LDY #1
JSR FNDBUF
BPL GBF1 ;FOUND ONE
;
DEY
JSR FNDBUF
BPL GBF1 ;FOUND ONE
;
JSR STLBUF ;STEAL ONE
TAX ;TEST IT
BMI GBF2 ;DIDN'T FIND ONE
GBF1
LDA JOBS,X
BMI GBF1 ;WAIT FOR JOB FREE
LDA DRVNUM
STA JOBS,X ;CLEAR JOB QUEUE
STA LSTJOB,X
TXA
ASL A
TAY
LDA #2
STA BUFTAB,Y
GBF2
PLA
TAY ;RESTORE .Y
TXA ;EXIT WITH BUF # IN .A & CC SET
RTS
;
;
; FIND A FREE BUF # & SET BIT IN BUFUSE
; ALL REGS USED
; IN: .Y= INDEX INTO BUFUSE
; OUT: .X= BUF # OR $FF IF FAILED
; .N= 1 IF FAILED
;
FNDBUF
LDX #7
FB1
LDA BUFUSE,Y ;SEARCH BUFUSE
AND BMASK,X
BEQ FB2 ;FOUND A FREE ONE
;
DEX
BPL FB1 ;UNTIL ALL BITS ARE TESTED
;
RTS
FB2 ;SET IT USED
LDA BUFUSE,Y
EOR BMASK,X ;SET BIT
STA BUFUSE,Y
TXA
DEY
BMI FB3 ;IF .Y THEN...
CLC ;...ADD 8 MORE
ADC #8
FB3
TAX ;LEAVE IN .X
FRI20
RTS
;
FREIAC ;FREE INACTIVE BUFFER
LDX LINDX
LDA BUF0,X
BMI FRI10
;
TXA
CLC
ADC #MXCHNS+1
TAX
LDA BUF0,X
BPL FRI20
FRI10
CMP #$FF
BEQ FRI20
;
PHA
LDA #$FF
STA BUF0,X
PLA
; JMP FREBUF
;
;
;
FREBUF AND #$F
TAY
INY
LDX #16
FREB1 ROR BUFUSE+1
ROR BUFUSE
DEY
BNE FREB2
CLC
FREB2 DEX
BPL FREB1
RTS
;
;
CLRCHN LDA #14
STA SA
CLRC1 JSR FRECHN
DEC SA
BNE CLRC1
RTS
;
CLDCHN LDA #14
STA SA
CLSD LDX SA
LDA LINTAB,X
CMP #$FF
BEQ CLD2
AND #$3F
STA LINDX
JSR GETACT
TAX
LDA LSTJOB,X
AND #1
CMP DRVNUM
BNE CLD2
JSR FRECHN
CLD2 DEC SA
BPL CLSD
RTS
;
;********************************
;*********** S T L B U F ******
;********************************
;
; STEAL A BUFFER
;
; THIS RTN SEARCHES THE CHANNELS
; IN ORDER OF LEAST RECENTLY USED
; AND STEALS THE FIRST INACTIVE
; BUFFER IT FINDS.
;
; INPUT PARAMTERS:
; LRUTBL - LEAST RECENTYL
; USED TABLE
;
; OUTPUT PARAMTERS:
; A <== BUFFER #
;
; REGISTER USAGE:
; X - CHANNEL INDEX
; Y - LRUTBL INDEX
;
;*******************************
;
STLBUF
LDA T0
PHA ;SAVE T0
LDY #0
STL05
LDX LRUTBL,Y
LDA BUF0,X
BPL STL10 ;ACTIVE
;
CMP #$FF
BNE STL30 ;IT'S INACTIVE
STL10
TXA
CLC
ADC #MXCHNS+1
TAX
LDA BUF0,X
BPL STL20
CMP #$FF
BNE STL30
STL20
INY
CPY #MXCHNS-1
BCC STL05
LDX #$FF ;SET FAILURE
BNE STL60 ;BRA
STL30 ;STEAL THE BUFFER IF NO ERROR
STX T0
AND #$3F
TAX
STL40
LDA JOBS,X
BMI STL40 ;WAIT TILL DONE
CMP #2 ;ERRORS?
BCC STL50 ;OK
LDX T0
CPX #MXCHNS+1
BCC STL10 ;CHECK OPPOSITE SLOT
BCS STL20 ;CHECK ANOTHER CHANNEL
;
; FOUND ONE, SO LETS STEAL IT
;
STL50
LDY T0
LDA #$FF
STA BUF0,Y ;CLEAR SLOT
STL60
PLA
STA T0
TXA ;BUF # IN .A & SET CC'S
RTS
;
;
;
; FIND A FREE LINDX TO USE
; MARK AS USED IN LINUSE
;
FNDLNX LDY #0
LDA #1
FND10 BIT LINUSE ;1=FREE 0=USED
BNE FND30
INY
ASL A
BNE FND10
LDA #NOCHNL ;NO FREE LINDX AVAILABLE
JMP CMDERR
FND30 EOR #$FF ;TOGGLE BIT MASK
AND LINUSE ;MARK BIT USED
STA LINUSE
TYA ;RETURN LINDX IN .A
RTS
.END
| {
"language": "Assembly"
} |
# Copyright 2015 Wolfgang Thaller.
#
# This file is part of Retro68.
#
# Retro68 is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Retro68 is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
.globl ._savef14
.globl ._savef15
.globl ._savef16
.globl ._savef17
.globl ._savef18
.globl ._savef19
.globl ._savef20
.globl ._savef21
.globl ._savef22
.globl ._savef23
.globl ._savef24
.globl ._savef25
.globl ._savef26
.globl ._savef27
.globl ._savef28
.globl ._savef29
.globl ._savef30
.globl ._savef31
.csect .text[PR]
._savef14: stfd 14, -144(1)
._savef15: stfd 15, -136(1)
._savef16: stfd 16, -128(1)
._savef17: stfd 17, -120(1)
._savef18: stfd 18, -112(1)
._savef19: stfd 19, -104(1)
._savef20: stfd 20, -96(1)
._savef21: stfd 21, -88(1)
._savef22: stfd 22, -80(1)
._savef23: stfd 23, -72(1)
._savef24: stfd 24, -64(1)
._savef25: stfd 25, -56(1)
._savef26: stfd 26, -48(1)
._savef27: stfd 27, -40(1)
._savef28: stfd 28, -32(1)
._savef29: stfd 29, -24(1)
._savef30: stfd 30, -16(1)
._savef31: stfd 31, -8(1)
blr
.globl ._restf14
.globl ._restf15
.globl ._restf16
.globl ._restf17
.globl ._restf18
.globl ._restf19
.globl ._restf20
.globl ._restf21
.globl ._restf22
.globl ._restf23
.globl ._restf24
.globl ._restf25
.globl ._restf26
.globl ._restf27
.globl ._restf28
.globl ._restf29
.globl ._restf30
.globl ._restf31
.csect .text[PR]
._restf14: lfd 14, -144(1)
._restf15: lfd 15, -136(1)
._restf16: lfd 16, -128(1)
._restf17: lfd 17, -120(1)
._restf18: lfd 18, -112(1)
._restf19: lfd 19, -104(1)
._restf20: lfd 20, -96(1)
._restf21: lfd 21, -88(1)
._restf22: lfd 22, -80(1)
._restf23: lfd 23, -72(1)
._restf24: lfd 24, -64(1)
._restf25: lfd 25, -56(1)
._restf26: lfd 26, -48(1)
._restf27: lfd 27, -40(1)
._restf28: lfd 28, -32(1)
._restf29: lfd 29, -24(1)
._restf30: lfd 30, -16(1)
._restf31: lfd 31, -8(1)
blr
| {
"language": "Assembly"
} |
/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2018 Endre Karlson <[email protected]>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
| {
"language": "Assembly"
} |
/** @file
Kaby Lake RVP 3 Board ACPI library
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/BoardAcpiTableLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
EFI_STATUS
EFIAPI
KabylakeRvp3BoardUpdateAcpiTable (
IN OUT EFI_ACPI_COMMON_HEADER *Table,
IN OUT EFI_ACPI_TABLE_VERSION *Version
);
EFI_STATUS
EFIAPI
BoardUpdateAcpiTable (
IN OUT EFI_ACPI_COMMON_HEADER *Table,
IN OUT EFI_ACPI_TABLE_VERSION *Version
)
{
KabylakeRvp3BoardUpdateAcpiTable (Table, Version);
return EFI_SUCCESS;
}
| {
"language": "Assembly"
} |
SFX_Pokeflute_Ch3:
vibrato 16, 1, 4
note_type 12, 1, 0
octave 5
note E_, 2
note F_, 2
note G_, 4
note A_, 2
note G_, 2
octave 6
note C_, 4
note C_, 2
note D_, 2
note C_, 2
octave 5
note G_, 2
note A_, 2
note F_, 2
note G_, 8
rest 12
sound_ret
| {
"language": "Assembly"
} |
.include "MPlayDef.s"
.equ se_m_encore2_grp, voicegroup111
.equ se_m_encore2_pri, 4
.equ se_m_encore2_rev, reverb_set+50
.equ se_m_encore2_mvl, 127
.equ se_m_encore2_key, 0
.equ se_m_encore2_tbs, 1
.equ se_m_encore2_exg, 0
.equ se_m_encore2_cmp, 1
.section .rodata
.global se_m_encore2
.align 2
@********************** Track 1 **********************@
se_m_encore2_1:
.byte KEYSH , se_m_encore2_key+0
.byte TEMPO , 150*se_m_encore2_tbs/2
.byte VOICE , 60
.byte BENDR , 12
.byte VOL , 25*se_m_encore2_mvl/mxv
.byte PAN , c_v+0
.byte BEND , c_v+0
.byte TIE , Cn3 , v127
.byte W01
.byte PAN , c_v+2
.byte W01
.byte c_v+5
.byte W01
.byte VOL , 34*se_m_encore2_mvl/mxv
.byte W01
.byte PAN , c_v+2
.byte W02
.byte c_v+0
.byte W01
.byte VOL , 46*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W01
.byte c_v-4
.byte W02
.byte VOL , 56*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W02
.byte c_v+0
.byte W01
.byte c_v+2
.byte W01
.byte c_v+5
.byte W01
.byte VOL , 70*se_m_encore2_mvl/mxv
.byte W01
.byte PAN , c_v+2
.byte W02
.byte c_v+0
.byte W01
.byte VOL , 80*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W01
.byte c_v-4
.byte W02
.byte VOL , 88*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W02
.byte c_v+0
.byte W01
.byte c_v+2
.byte W01
.byte VOL , 96*se_m_encore2_mvl/mxv
.byte PAN , c_v+5
.byte W02
.byte c_v+2
.byte W02
.byte VOL , 100*se_m_encore2_mvl/mxv
.byte PAN , c_v+0
.byte W01
.byte c_v-2
.byte W01
.byte c_v-4
.byte W02
.byte c_v-2
.byte W02
se_m_encore2_1_000:
.byte PAN , c_v+0
.byte W01
.byte c_v+2
.byte W01
.byte c_v+5
.byte W02
.byte c_v+2
.byte W02
.byte c_v+0
.byte W01
.byte c_v-2
.byte W01
.byte c_v-4
.byte W02
.byte c_v-2
.byte W02
.byte PEND
.byte PATT
.word se_m_encore2_1_000
.byte PATT
.word se_m_encore2_1_000
.byte PATT
.word se_m_encore2_1_000
.byte PATT
.word se_m_encore2_1_000
.byte PATT
.word se_m_encore2_1_000
.byte PATT
.word se_m_encore2_1_000
.byte VOL , 96*se_m_encore2_mvl/mxv
.byte PAN , c_v+0
.byte W01
.byte c_v+2
.byte W01
.byte c_v+5
.byte W01
.byte VOL , 92*se_m_encore2_mvl/mxv
.byte W01
.byte PAN , c_v+2
.byte W02
.byte c_v+0
.byte W01
.byte VOL , 84*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W01
.byte c_v-4
.byte W02
.byte VOL , 72*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W02
.byte c_v+0
.byte W01
.byte c_v+2
.byte W01
.byte VOL , 63*se_m_encore2_mvl/mxv
.byte PAN , c_v+5
.byte W02
.byte VOL , 52*se_m_encore2_mvl/mxv
.byte PAN , c_v+2
.byte W02
.byte c_v+0
.byte W01
.byte VOL , 37*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W01
.byte c_v-4
.byte W01
.byte VOL , 22*se_m_encore2_mvl/mxv
.byte W01
.byte 12*se_m_encore2_mvl/mxv
.byte PAN , c_v-2
.byte W02
.byte EOT , Cn3
.byte FINE
@******************************************************@
.align 2
se_m_encore2:
.byte 1 @ NumTrks
.byte 0 @ NumBlks
.byte se_m_encore2_pri @ Priority
.byte se_m_encore2_rev @ Reverb.
.word se_m_encore2_grp
.word se_m_encore2_1
.end
| {
"language": "Assembly"
} |
/*
* Copyright (c) 2008 Mans Rullgard <[email protected]>
*
* This file is part of Libav.
*
* Libav is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* Libav is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with Libav; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
.macro transpose_8x8 r0, r1, r2, r3, r4, r5, r6, r7
vtrn.32 \r0, \r4
vtrn.32 \r1, \r5
vtrn.32 \r2, \r6
vtrn.32 \r3, \r7
vtrn.16 \r0, \r2
vtrn.16 \r1, \r3
vtrn.16 \r4, \r6
vtrn.16 \r5, \r7
vtrn.8 \r0, \r1
vtrn.8 \r2, \r3
vtrn.8 \r4, \r5
vtrn.8 \r6, \r7
.endm
.macro transpose_4x4 r0, r1, r2, r3
vtrn.16 \r0, \r2
vtrn.16 \r1, \r3
vtrn.8 \r0, \r1
vtrn.8 \r2, \r3
.endm
.macro swap4 r0, r1, r2, r3, r4, r5, r6, r7
vswp \r0, \r4
vswp \r1, \r5
vswp \r2, \r6
vswp \r3, \r7
.endm
.macro transpose16_4x4 r0, r1, r2, r3, r4, r5, r6, r7
vtrn.32 \r0, \r2
vtrn.32 \r1, \r3
vtrn.32 \r4, \r6
vtrn.32 \r5, \r7
vtrn.16 \r0, \r1
vtrn.16 \r2, \r3
vtrn.16 \r4, \r5
vtrn.16 \r6, \r7
.endm
| {
"language": "Assembly"
} |
// fn0C00_0000
// Return size: 2
// Mem0:Mem
// fp:fp
// sp:sp
// al:al
// ds:ds
// ax:ax
// SCZO:SCZO
// dx_ax:Sequence dx:ax
// dx:dx
// cx:cx
// cl:cl
// Top:Top
// return address size: 2
define fn0C00_0000
fn0C00_0000_entry:
sp = fp
Top = 0<i8>
// succ: l0C00_0000
l0C00_0000:
al = Mem0[ds:0x300<16>:byte]
ax = Mem0[ds:0x301<16>:byte] *u al
SCZO = cond(ax)
Mem0[ds:0x302<16>:word16] = ax
ax = Mem0[ds:0x304<16>:word16]
dx_ax = Mem0[ds:0x306<16>:word16] *u ax
SCZO = cond(dx_ax)
Mem0[ds:0x308<16>:word16] = ax
Mem0[ds:0x30A<16>:word16] = dx
cx = Mem0[ds:0x30C<16>:word16]
ax = Mem0[ds:0x30E<16>:word16]
dx_ax = cx *s ax
SCZO = cond(dx_ax)
Mem0[ds:0x310<16>:word16] = ax
Mem0[ds:0x312<16>:word16] = dx
al = Mem0[ds:0x300<16>:byte]
cl = Mem0[ds:0x301<16>:byte]
ax = cl *u al
SCZO = cond(ax)
Mem0[ds:0x302<16>:word16] = ax
ax = Mem0[ds:0x304<16>:word16] *s 0x24<16>
SCZO = cond(ax)
dx = ax *s 0x24<16>
SCZO = cond(dx)
ax = Mem0[ds:0x304<16>:word16] *s 0x114<16>
SCZO = cond(ax)
dx = ax *s 0x114<16>
SCZO = cond(dx)
ax = Mem0[ds:0x304<16>:word16] *s 0x114<16>
SCZO = cond(ax)
return
// succ: fn0C00_0000_exit
fn0C00_0000_exit:
| {
"language": "Assembly"
} |
StartChar: uni044C
Encoding: 1100 1100 1954
Width: 402
Flags: MW
LayerCount: 2
Fore
SplineSet
169 176 m 24
134 135 108 81 108 52 c 0
108 29 127 10 150 10 c 0
173 10 200 22 221 39 c 0
259 71 298 129 298 190 c 0
298 212 290 237 268 237 c 0
236 237 199 210 169 176 c 24
134 -14 m 0
62 -14 45 17 45 55 c 0
45 85 75 150 94 195 c 10
126 270 l 2
135 292 154 339 144 339 c 0
133 339 95 306 66 280 c 0
63 277 53 279 53 283 c 0
53 288 54 298 65 313 c 0
115 380 191 418 220 418 c 0
240 418 249 405 235 373 c 2
162 213 l 2
159 206 163 204 171 211 c 0
209 247 250 267 293 267 c 0
339 267 362 236 362 188 c 0
362 123 307 51 247 16 c 0
210 -5 162 -14 134 -14 c 0
EndSplineSet
Validated: 33
EndChar
| {
"language": "Assembly"
} |
// { dg-options "-std=gnu++0x" }
// { dg-do compile }
// Copyright (C) 2009-2013 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the
// Free Software Foundation; either version 3, or (at your option)
// any later version.
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License along
// with this library; see the file COPYING3. If not see
// <http://www.gnu.org/licenses/>.
// This file tests explicit instantiation of library containers
#include <array>
#include <testsuite_hooks.h>
#include <testsuite_api.h>
template class std::array<__gnu_test::NonDefaultConstructible, 3>;
| {
"language": "Assembly"
} |
.late_rodata
glabel D_80AEA894
.float 0.15
glabel D_80AEA898
.float 5000.0
.text
glabel func_80AE8810
/* 003D0 80AE8810 27BDFFE8 */ addiu $sp, $sp, 0xFFE8 ## $sp = FFFFFFE8
/* 003D4 80AE8814 AFBF0014 */ sw $ra, 0x0014($sp)
/* 003D8 80AE8818 AFA5001C */ sw $a1, 0x001C($sp)
/* 003DC 80AE881C 44800000 */ mtc1 $zero, $f0 ## $f0 = 0.00
/* 003E0 80AE8820 8C8F0004 */ lw $t7, 0x0004($a0) ## 00000004
/* 003E4 80AE8824 2401FFFE */ addiu $at, $zero, 0xFFFE ## $at = FFFFFFFE
/* 003E8 80AE8828 240E0064 */ addiu $t6, $zero, 0x0064 ## $t6 = 00000064
/* 003EC 80AE882C 01E1C024 */ and $t8, $t7, $at
/* 003F0 80AE8830 24190008 */ addiu $t9, $zero, 0x0008 ## $t9 = 00000008
/* 003F4 80AE8834 24080001 */ addiu $t0, $zero, 0x0001 ## $t0 = 00000001
/* 003F8 80AE8838 A48E01EE */ sh $t6, 0x01EE($a0) ## 000001EE
/* 003FC 80AE883C AC980004 */ sw $t8, 0x0004($a0) ## 00000004
/* 00400 80AE8840 A49901F4 */ sh $t9, 0x01F4($a0) ## 000001F4
/* 00404 80AE8844 A4880378 */ sh $t0, 0x0378($a0) ## 00000378
/* 00408 80AE8848 A0800370 */ sb $zero, 0x0370($a0) ## 00000370
/* 0040C 80AE884C 3C0180AF */ lui $at, %hi(D_80AEA894) ## $at = 80AF0000
/* 00410 80AE8850 E4800068 */ swc1 $f0, 0x0068($a0) ## 00000068
/* 00414 80AE8854 E480036C */ swc1 $f0, 0x036C($a0) ## 0000036C
/* 00418 80AE8858 E4800364 */ swc1 $f0, 0x0364($a0) ## 00000364
/* 0041C 80AE885C C424A894 */ lwc1 $f4, %lo(D_80AEA894)($at)
/* 00420 80AE8860 3C0180AF */ lui $at, %hi(D_80AEA898) ## $at = 80AF0000
/* 00424 80AE8864 24030001 */ addiu $v1, $zero, 0x0001 ## $v1 = 00000001
/* 00428 80AE8868 E4840218 */ swc1 $f4, 0x0218($a0) ## 00000218
/* 0042C 80AE886C C426A898 */ lwc1 $f6, %lo(D_80AEA898)($at)
/* 00430 80AE8870 3C014400 */ lui $at, 0x4400 ## $at = 44000000
/* 00434 80AE8874 44814000 */ mtc1 $at, $f8 ## $f8 = 512.00
/* 00438 80AE8878 3C013F80 */ lui $at, 0x3F80 ## $at = 3F800000
/* 0043C 80AE887C 44811000 */ mtc1 $at, $f2 ## $f2 = 1.00
/* 00440 80AE8880 00034980 */ sll $t1, $v1, 6
/* 00444 80AE8884 00891021 */ addu $v0, $a0, $t1
/* 00448 80AE8888 E4800250 */ swc1 $f0, 0x0250($a0) ## 00000250
/* 0044C 80AE888C E4800258 */ swc1 $f0, 0x0258($a0) ## 00000258
/* 00450 80AE8890 E4800228 */ swc1 $f0, 0x0228($a0) ## 00000228
/* 00454 80AE8894 E48601FC */ swc1 $f6, 0x01FC($a0) ## 000001FC
/* 00458 80AE8898 E4880220 */ swc1 $f8, 0x0220($a0) ## 00000220
/* 0045C 80AE889C E4820240 */ swc1 $f2, 0x0240($a0) ## 00000240
/* 00460 80AE88A0 E4820238 */ swc1 $f2, 0x0238($a0) ## 00000238
/* 00464 80AE88A4 3C0A80AF */ lui $t2, %hi(func_80AE978C) ## $t2 = 80AF0000
/* 00468 80AE88A8 254A978C */ addiu $t2, $t2, %lo(func_80AE978C) ## $t2 = 80AE978C
/* 0046C 80AE88AC E4400310 */ swc1 $f0, 0x0310($v0) ## 00000310
/* 00470 80AE88B0 E4400318 */ swc1 $f0, 0x0318($v0) ## 00000318
/* 00474 80AE88B4 E44002E8 */ swc1 $f0, 0x02E8($v0) ## 000002E8
/* 00478 80AE88B8 E44002D0 */ swc1 $f0, 0x02D0($v0) ## 000002D0
/* 0047C 80AE88BC E44002D8 */ swc1 $f0, 0x02D8($v0) ## 000002D8
/* 00480 80AE88C0 E44002A8 */ swc1 $f0, 0x02A8($v0) ## 000002A8
/* 00484 80AE88C4 E4400290 */ swc1 $f0, 0x0290($v0) ## 00000290
/* 00488 80AE88C8 E4400298 */ swc1 $f0, 0x0298($v0) ## 00000298
/* 0048C 80AE88CC E4400268 */ swc1 $f0, 0x0268($v0) ## 00000268
/* 00490 80AE88D0 E4400228 */ swc1 $f0, 0x0228($v0) ## 00000228
/* 00494 80AE88D4 E4400250 */ swc1 $f0, 0x0250($v0) ## 00000250
/* 00498 80AE88D8 E4400258 */ swc1 $f0, 0x0258($v0) ## 00000258
/* 0049C 80AE88DC E44202F8 */ swc1 $f2, 0x02F8($v0) ## 000002F8
/* 004A0 80AE88E0 E4420300 */ swc1 $f2, 0x0300($v0) ## 00000300
/* 004A4 80AE88E4 E44202B8 */ swc1 $f2, 0x02B8($v0) ## 000002B8
/* 004A8 80AE88E8 E44202C0 */ swc1 $f2, 0x02C0($v0) ## 000002C0
/* 004AC 80AE88EC E4420278 */ swc1 $f2, 0x0278($v0) ## 00000278
/* 004B0 80AE88F0 E4420280 */ swc1 $f2, 0x0280($v0) ## 00000280
/* 004B4 80AE88F4 E4420238 */ swc1 $f2, 0x0238($v0) ## 00000238
/* 004B8 80AE88F8 E4420240 */ swc1 $f2, 0x0240($v0) ## 00000240
/* 004BC 80AE88FC AC8A014C */ sw $t2, 0x014C($a0) ## 0000014C
/* 004C0 80AE8900 0C00BE0A */ jal Audio_PlayActorSound2
/* 004C4 80AE8904 24053992 */ addiu $a1, $zero, 0x3992 ## $a1 = 00003992
/* 004C8 80AE8908 8FBF0014 */ lw $ra, 0x0014($sp)
/* 004CC 80AE890C 27BD0018 */ addiu $sp, $sp, 0x0018 ## $sp = 00000000
/* 004D0 80AE8910 03E00008 */ jr $ra
/* 004D4 80AE8914 00000000 */ nop
| {
"language": "Assembly"
} |
;Contenido del codigo fuente de la ultima version de manstransfe, MANTR11.SP que hay en el mantransfev3.tap
RUN ORG 49152
ENT 16384
INICIO
REGSP DEFW 0
;ESTA INSTRUCCION LA ALTERA
;EL EMULADOR, CON EL MODO
;ACTIVO, SI IM1 O IM2
IMMODE IM1
RET
;
;INICIO RUTINA CARGA
;
CARGAR LD SP,FINRUT
;METEMOS STACK AL FINAL DEL
;TODO
LD A,255
SCF
LD IX,FINRUT
LD DE,65536-FINRUT
CALL 1366
;RESTAURAR REGISTROS
RESTAU LD SP,(REGSP)
POP HL
POP DE
POP BC
POP AF
EX AF,AF'
EXX
POP IY
POP IX
POP HL
POP DE
POP BC
;REGISTRO I Y FLAGS QUE INDICAN
;SI DI O EI
POP AF
LD I,A
;MODO INTERRUPCIONES
CALL IMMODE
;SI EI O DI
JP PO,ESTADI
EI
ESTADI POP AF
RET
;
;RUTINA GRABAR SNAPSHOT
;
GRABAR PUSH AF
LD A,I
PUSH AF
PUSH BC
PUSH DE
PUSH HL
PUSH IX
PUSH IY
EXX
EX AF,AF'
PUSH AF
PUSH BC
PUSH DE
PUSH HL
LD (REGSP),SP
;GRABAR PROGRAMA BASIC
LD A,0
LD IX,CABBAS
LD DE,17
CALL SAVPAU
LD A,255
LD IX,INIBAS
LD DE,FINBAS-INIBAS
CALL SAVPAU
;BLOQUE BYTES PRIMERO
LD A,0
LD IX,CABCOD
LD DE,17
CALL SAVPAU
LD A,255
LD IX,16384
LD DE,GRABAR-INICIO
CALL SAVPAU
;Y BLOQUE DATOS
LD A,255
LD IX,FINRUT
LD DE,65536-FINRUT
CALL SAVPAU
;DESPUES DE GRABAR QUE HACEMOS
JP RESTAU
SAVPAU CALL 1218
LD BC,0
PAUSA2 DEC BC
LD A,B
OR C
JR NZ,PAUSA2
RET
;PROGRAMA BASIC QUE CARGA
INIBAS DEFB 0,1
DEFW FINBAS-LINEA1
LINEA1 DEFB #EF,34,34,#AF,#3A
;LOAD ""CODE:
DEFB #F9,#C0,#B0,34
;RANDOMIZE USR VAL "
DEFM "16389"
DEFB 34
DEFB 13
FINBAS
CABBAS DEFB 0
DEFM "MANTRANSFE"
DEFW FINBAS-INIBAS
DEFW 1
DEFW FINBAS-INIBAS
CABCOD DEFB 3
DEFM "1234567890"
DEFW GRABAR-INICIO
DEFW 16384
DEFW 0
FINRUT
| {
"language": "Assembly"
} |
// -*- C++ -*-
//===-------------------------- cassert -----------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/*
cassert synopsis
Macros:
assert
*/
#include <__config>
#include <assert.h>
#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
#pragma GCC system_header
#endif
| {
"language": "Assembly"
} |
; RUN: llvm-as %s -o /dev/null
; RUN: verify-uselistorder %s
@spell_order = global [4 x i8] c"\FF\00\F7\00"
| {
"language": "Assembly"
} |
/*
* RELIC is an Efficient LIbrary for Cryptography
* Copyright (C) 2007, 2008, 2009 RELIC Authors
*
* This file is part of RELIC. RELIC is legal property of its developers,
* whose names are not listed here. Please refer to the COPYRIGHT file
* for contact information.
*
* RELIC is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* RELIC is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with RELIC. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file
*
* Implementation of the low-level binary field addition and subtraction
* functions.
*
* @ingroup fb
*/
#include "relic_conf.h"
.text
.align 2
.global fb_addn_low
fb_addn_low:
mov @r14+,r12
xor @r13+,r12
mov r12,@r15
mov @r14+,r12
xor @r13+,r12
mov r12,2*1(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*2(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*3(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*4(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*5(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*6(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*7(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*8(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*9(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*10(r15)
#if (FB_POLYN > 176)
mov @r14+,r12
xor @r13+,r12
mov r12,2*11(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*12(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*13(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*14(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*15(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*16(r15)
#if (FB_POLYN > 272)
mov @r14+,r12
xor @r13+,r12
mov r12,2*17(r15)
#if (FB_POLYN > 288)
mov @r14+,r12
xor @r13+,r12
mov r12,2*18(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*19(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*20(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*21(r15)
mov @r14+,r12
xor @r13+,r12
mov r12,2*22(r15)
#endif
#endif
#endif
ret
| {
"language": "Assembly"
} |
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )
#include <librm.h>
.text
.arch i386
.section ".prefix", "awx", @progbits
.code16
.org 0
.globl _hd_start
_hd_start:
movw $load_image, %bp
jmp find_active_partition
#include "bootpart.S"
load_image:
/* Get disk geometry */
pushal
pushw %es
movb $0x08, %ah
int $0x13
jc load_failed
movb %cl, max_sector
movb %dh, max_head
popw %es
popal
1: /* Read to end of current track (or end of image) */
movb %cl, %al
negb %al
addb max_sector, %al
incb %al
andb $0x3f, %al
movzbl %al, %eax
movl load_length, %ebx
cmpl %eax, %ebx
ja 2f
movl %ebx, %eax
2: call *read_sectors
jc load_failed
/* Update %es */
movw %es, %bx
shll $5, %eax
addw %ax, %bx
movw %bx, %es
shrl $5, %eax
/* Update LBA address */
addl %eax, %edi
adcl $0, %esi
/* Update CHS address */
andb $0xc0, %cl
orb $0x01, %cl
incb %dh
cmpb max_head, %dh
jbe 3f
xorb %dh, %dh
incb %ch
jnc 3f
addb $0xc0, %cl
3:
/* Loop until whole image is read */
subl %eax, load_length
ja 1b
ljmp $BOOT_SEG, $start_image
max_sector:
.byte 0
max_head:
.byte 0
load_length:
.long 0
.section ".zinfo.fixup", "a", @progbits /* Compressor fixups */
.ascii "ADDL"
.long load_length
.long 512
.long 0
.previous
load_failed:
movw $10f, %si
jmp boot_error
10: .asciz "Could not load iPXE\r\n"
.org 510
.byte 0x55, 0xaa
start_image:
/* Install iPXE */
call install
/* Set up real-mode stack */
movw %bx, %ss
movw $_estack16, %sp
/* Jump to .text16 segment */
pushw %ax
pushw $1f
lret
.section ".text16", "awx", @progbits
1:
/* Run iPXE */
virtcall main
/* Uninstall iPXE */
call uninstall
/* Boot next device */
int $0x18
| {
"language": "Assembly"
} |
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build arm,!gccgo,!appengine,!nacl
#include "textflag.h"
// This code was translated into a form compatible with 5a from the public
// domain source by Andrew Moon: github.com/floodyberry/poly1305-opt/blob/master/app/extensions/poly1305.
DATA ·poly1305_init_constants_armv6<>+0x00(SB)/4, $0x3ffffff
DATA ·poly1305_init_constants_armv6<>+0x04(SB)/4, $0x3ffff03
DATA ·poly1305_init_constants_armv6<>+0x08(SB)/4, $0x3ffc0ff
DATA ·poly1305_init_constants_armv6<>+0x0c(SB)/4, $0x3f03fff
DATA ·poly1305_init_constants_armv6<>+0x10(SB)/4, $0x00fffff
GLOBL ·poly1305_init_constants_armv6<>(SB), 8, $20
// Warning: the linker may use R11 to synthesize certain instructions. Please
// take care and verify that no synthetic instructions use it.
TEXT poly1305_init_ext_armv6<>(SB), NOSPLIT, $0
// Needs 16 bytes of stack and 64 bytes of space pointed to by R0. (It
// might look like it's only 60 bytes of space but the final four bytes
// will be written by another function.) We need to skip over four
// bytes of stack because that's saving the value of 'g'.
ADD $4, R13, R8
MOVM.IB [R4-R7], (R8)
MOVM.IA.W (R1), [R2-R5]
MOVW $·poly1305_init_constants_armv6<>(SB), R7
MOVW R2, R8
MOVW R2>>26, R9
MOVW R3>>20, g
MOVW R4>>14, R11
MOVW R5>>8, R12
ORR R3<<6, R9, R9
ORR R4<<12, g, g
ORR R5<<18, R11, R11
MOVM.IA (R7), [R2-R6]
AND R8, R2, R2
AND R9, R3, R3
AND g, R4, R4
AND R11, R5, R5
AND R12, R6, R6
MOVM.IA.W [R2-R6], (R0)
EOR R2, R2, R2
EOR R3, R3, R3
EOR R4, R4, R4
EOR R5, R5, R5
EOR R6, R6, R6
MOVM.IA.W [R2-R6], (R0)
MOVM.IA.W (R1), [R2-R5]
MOVM.IA [R2-R6], (R0)
ADD $20, R13, R0
MOVM.DA (R0), [R4-R7]
RET
#define MOVW_UNALIGNED(Rsrc, Rdst, Rtmp, offset) \
MOVBU (offset+0)(Rsrc), Rtmp; \
MOVBU Rtmp, (offset+0)(Rdst); \
MOVBU (offset+1)(Rsrc), Rtmp; \
MOVBU Rtmp, (offset+1)(Rdst); \
MOVBU (offset+2)(Rsrc), Rtmp; \
MOVBU Rtmp, (offset+2)(Rdst); \
MOVBU (offset+3)(Rsrc), Rtmp; \
MOVBU Rtmp, (offset+3)(Rdst)
TEXT poly1305_blocks_armv6<>(SB), NOSPLIT, $0
// Needs 24 bytes of stack for saved registers and then 88 bytes of
// scratch space after that. We assume that 24 bytes at (R13) have
// already been used: four bytes for the link register saved in the
// prelude of poly1305_auth_armv6, four bytes for saving the value of g
// in that function and 16 bytes of scratch space used around
// poly1305_finish_ext_armv6_skip1.
ADD $24, R13, R12
MOVM.IB [R4-R8, R14], (R12)
MOVW R0, 88(R13)
MOVW R1, 92(R13)
MOVW R2, 96(R13)
MOVW R1, R14
MOVW R2, R12
MOVW 56(R0), R8
WORD $0xe1180008 // TST R8, R8 not working see issue 5921
EOR R6, R6, R6
MOVW.EQ $(1<<24), R6
MOVW R6, 84(R13)
ADD $116, R13, g
MOVM.IA (R0), [R0-R9]
MOVM.IA [R0-R4], (g)
CMP $16, R12
BLO poly1305_blocks_armv6_done
poly1305_blocks_armv6_mainloop:
WORD $0xe31e0003 // TST R14, #3 not working see issue 5921
BEQ poly1305_blocks_armv6_mainloop_aligned
ADD $100, R13, g
MOVW_UNALIGNED(R14, g, R0, 0)
MOVW_UNALIGNED(R14, g, R0, 4)
MOVW_UNALIGNED(R14, g, R0, 8)
MOVW_UNALIGNED(R14, g, R0, 12)
MOVM.IA (g), [R0-R3]
ADD $16, R14
B poly1305_blocks_armv6_mainloop_loaded
poly1305_blocks_armv6_mainloop_aligned:
MOVM.IA.W (R14), [R0-R3]
poly1305_blocks_armv6_mainloop_loaded:
MOVW R0>>26, g
MOVW R1>>20, R11
MOVW R2>>14, R12
MOVW R14, 92(R13)
MOVW R3>>8, R4
ORR R1<<6, g, g
ORR R2<<12, R11, R11
ORR R3<<18, R12, R12
BIC $0xfc000000, R0, R0
BIC $0xfc000000, g, g
MOVW 84(R13), R3
BIC $0xfc000000, R11, R11
BIC $0xfc000000, R12, R12
ADD R0, R5, R5
ADD g, R6, R6
ORR R3, R4, R4
ADD R11, R7, R7
ADD $116, R13, R14
ADD R12, R8, R8
ADD R4, R9, R9
MOVM.IA (R14), [R0-R4]
MULLU R4, R5, (R11, g)
MULLU R3, R5, (R14, R12)
MULALU R3, R6, (R11, g)
MULALU R2, R6, (R14, R12)
MULALU R2, R7, (R11, g)
MULALU R1, R7, (R14, R12)
ADD R4<<2, R4, R4
ADD R3<<2, R3, R3
MULALU R1, R8, (R11, g)
MULALU R0, R8, (R14, R12)
MULALU R0, R9, (R11, g)
MULALU R4, R9, (R14, R12)
MOVW g, 76(R13)
MOVW R11, 80(R13)
MOVW R12, 68(R13)
MOVW R14, 72(R13)
MULLU R2, R5, (R11, g)
MULLU R1, R5, (R14, R12)
MULALU R1, R6, (R11, g)
MULALU R0, R6, (R14, R12)
MULALU R0, R7, (R11, g)
MULALU R4, R7, (R14, R12)
ADD R2<<2, R2, R2
ADD R1<<2, R1, R1
MULALU R4, R8, (R11, g)
MULALU R3, R8, (R14, R12)
MULALU R3, R9, (R11, g)
MULALU R2, R9, (R14, R12)
MOVW g, 60(R13)
MOVW R11, 64(R13)
MOVW R12, 52(R13)
MOVW R14, 56(R13)
MULLU R0, R5, (R11, g)
MULALU R4, R6, (R11, g)
MULALU R3, R7, (R11, g)
MULALU R2, R8, (R11, g)
MULALU R1, R9, (R11, g)
ADD $52, R13, R0
MOVM.IA (R0), [R0-R7]
MOVW g>>26, R12
MOVW R4>>26, R14
ORR R11<<6, R12, R12
ORR R5<<6, R14, R14
BIC $0xfc000000, g, g
BIC $0xfc000000, R4, R4
ADD.S R12, R0, R0
ADC $0, R1, R1
ADD.S R14, R6, R6
ADC $0, R7, R7
MOVW R0>>26, R12
MOVW R6>>26, R14
ORR R1<<6, R12, R12
ORR R7<<6, R14, R14
BIC $0xfc000000, R0, R0
BIC $0xfc000000, R6, R6
ADD R14<<2, R14, R14
ADD.S R12, R2, R2
ADC $0, R3, R3
ADD R14, g, g
MOVW R2>>26, R12
MOVW g>>26, R14
ORR R3<<6, R12, R12
BIC $0xfc000000, g, R5
BIC $0xfc000000, R2, R7
ADD R12, R4, R4
ADD R14, R0, R0
MOVW R4>>26, R12
BIC $0xfc000000, R4, R8
ADD R12, R6, R9
MOVW 96(R13), R12
MOVW 92(R13), R14
MOVW R0, R6
CMP $32, R12
SUB $16, R12, R12
MOVW R12, 96(R13)
BHS poly1305_blocks_armv6_mainloop
poly1305_blocks_armv6_done:
MOVW 88(R13), R12
MOVW R5, 20(R12)
MOVW R6, 24(R12)
MOVW R7, 28(R12)
MOVW R8, 32(R12)
MOVW R9, 36(R12)
ADD $48, R13, R0
MOVM.DA (R0), [R4-R8, R14]
RET
#define MOVHUP_UNALIGNED(Rsrc, Rdst, Rtmp) \
MOVBU.P 1(Rsrc), Rtmp; \
MOVBU.P Rtmp, 1(Rdst); \
MOVBU.P 1(Rsrc), Rtmp; \
MOVBU.P Rtmp, 1(Rdst)
#define MOVWP_UNALIGNED(Rsrc, Rdst, Rtmp) \
MOVHUP_UNALIGNED(Rsrc, Rdst, Rtmp); \
MOVHUP_UNALIGNED(Rsrc, Rdst, Rtmp)
// func poly1305_auth_armv6(out *[16]byte, m *byte, mlen uint32, key *[32]key)
TEXT ·poly1305_auth_armv6(SB), $196-16
// The value 196, just above, is the sum of 64 (the size of the context
// structure) and 132 (the amount of stack needed).
//
// At this point, the stack pointer (R13) has been moved down. It
// points to the saved link register and there's 196 bytes of free
// space above it.
//
// The stack for this function looks like:
//
// +---------------------
// |
// | 64 bytes of context structure
// |
// +---------------------
// |
// | 112 bytes for poly1305_blocks_armv6
// |
// +---------------------
// | 16 bytes of final block, constructed at
// | poly1305_finish_ext_armv6_skip8
// +---------------------
// | four bytes of saved 'g'
// +---------------------
// | lr, saved by prelude <- R13 points here
// +---------------------
MOVW g, 4(R13)
MOVW out+0(FP), R4
MOVW m+4(FP), R5
MOVW mlen+8(FP), R6
MOVW key+12(FP), R7
ADD $136, R13, R0 // 136 = 4 + 4 + 16 + 112
MOVW R7, R1
// poly1305_init_ext_armv6 will write to the stack from R13+4, but
// that's ok because none of the other values have been written yet.
BL poly1305_init_ext_armv6<>(SB)
BIC.S $15, R6, R2
BEQ poly1305_auth_armv6_noblocks
ADD $136, R13, R0
MOVW R5, R1
ADD R2, R5, R5
SUB R2, R6, R6
BL poly1305_blocks_armv6<>(SB)
poly1305_auth_armv6_noblocks:
ADD $136, R13, R0
MOVW R5, R1
MOVW R6, R2
MOVW R4, R3
MOVW R0, R5
MOVW R1, R6
MOVW R2, R7
MOVW R3, R8
AND.S R2, R2, R2
BEQ poly1305_finish_ext_armv6_noremaining
EOR R0, R0
ADD $8, R13, R9 // 8 = offset to 16 byte scratch space
MOVW R0, (R9)
MOVW R0, 4(R9)
MOVW R0, 8(R9)
MOVW R0, 12(R9)
WORD $0xe3110003 // TST R1, #3 not working see issue 5921
BEQ poly1305_finish_ext_armv6_aligned
WORD $0xe3120008 // TST R2, #8 not working see issue 5921
BEQ poly1305_finish_ext_armv6_skip8
MOVWP_UNALIGNED(R1, R9, g)
MOVWP_UNALIGNED(R1, R9, g)
poly1305_finish_ext_armv6_skip8:
WORD $0xe3120004 // TST $4, R2 not working see issue 5921
BEQ poly1305_finish_ext_armv6_skip4
MOVWP_UNALIGNED(R1, R9, g)
poly1305_finish_ext_armv6_skip4:
WORD $0xe3120002 // TST $2, R2 not working see issue 5921
BEQ poly1305_finish_ext_armv6_skip2
MOVHUP_UNALIGNED(R1, R9, g)
B poly1305_finish_ext_armv6_skip2
poly1305_finish_ext_armv6_aligned:
WORD $0xe3120008 // TST R2, #8 not working see issue 5921
BEQ poly1305_finish_ext_armv6_skip8_aligned
MOVM.IA.W (R1), [g-R11]
MOVM.IA.W [g-R11], (R9)
poly1305_finish_ext_armv6_skip8_aligned:
WORD $0xe3120004 // TST $4, R2 not working see issue 5921
BEQ poly1305_finish_ext_armv6_skip4_aligned
MOVW.P 4(R1), g
MOVW.P g, 4(R9)
poly1305_finish_ext_armv6_skip4_aligned:
WORD $0xe3120002 // TST $2, R2 not working see issue 5921
BEQ poly1305_finish_ext_armv6_skip2
MOVHU.P 2(R1), g
MOVH.P g, 2(R9)
poly1305_finish_ext_armv6_skip2:
WORD $0xe3120001 // TST $1, R2 not working see issue 5921
BEQ poly1305_finish_ext_armv6_skip1
MOVBU.P 1(R1), g
MOVBU.P g, 1(R9)
poly1305_finish_ext_armv6_skip1:
MOVW $1, R11
MOVBU R11, 0(R9)
MOVW R11, 56(R5)
MOVW R5, R0
ADD $8, R13, R1
MOVW $16, R2
BL poly1305_blocks_armv6<>(SB)
poly1305_finish_ext_armv6_noremaining:
MOVW 20(R5), R0
MOVW 24(R5), R1
MOVW 28(R5), R2
MOVW 32(R5), R3
MOVW 36(R5), R4
MOVW R4>>26, R12
BIC $0xfc000000, R4, R4
ADD R12<<2, R12, R12
ADD R12, R0, R0
MOVW R0>>26, R12
BIC $0xfc000000, R0, R0
ADD R12, R1, R1
MOVW R1>>26, R12
BIC $0xfc000000, R1, R1
ADD R12, R2, R2
MOVW R2>>26, R12
BIC $0xfc000000, R2, R2
ADD R12, R3, R3
MOVW R3>>26, R12
BIC $0xfc000000, R3, R3
ADD R12, R4, R4
ADD $5, R0, R6
MOVW R6>>26, R12
BIC $0xfc000000, R6, R6
ADD R12, R1, R7
MOVW R7>>26, R12
BIC $0xfc000000, R7, R7
ADD R12, R2, g
MOVW g>>26, R12
BIC $0xfc000000, g, g
ADD R12, R3, R11
MOVW $-(1<<26), R12
ADD R11>>26, R12, R12
BIC $0xfc000000, R11, R11
ADD R12, R4, R9
MOVW R9>>31, R12
SUB $1, R12
AND R12, R6, R6
AND R12, R7, R7
AND R12, g, g
AND R12, R11, R11
AND R12, R9, R9
MVN R12, R12
AND R12, R0, R0
AND R12, R1, R1
AND R12, R2, R2
AND R12, R3, R3
AND R12, R4, R4
ORR R6, R0, R0
ORR R7, R1, R1
ORR g, R2, R2
ORR R11, R3, R3
ORR R9, R4, R4
ORR R1<<26, R0, R0
MOVW R1>>6, R1
ORR R2<<20, R1, R1
MOVW R2>>12, R2
ORR R3<<14, R2, R2
MOVW R3>>18, R3
ORR R4<<8, R3, R3
MOVW 40(R5), R6
MOVW 44(R5), R7
MOVW 48(R5), g
MOVW 52(R5), R11
ADD.S R6, R0, R0
ADC.S R7, R1, R1
ADC.S g, R2, R2
ADC.S R11, R3, R3
MOVM.IA [R0-R3], (R8)
MOVW R5, R12
EOR R0, R0, R0
EOR R1, R1, R1
EOR R2, R2, R2
EOR R3, R3, R3
EOR R4, R4, R4
EOR R5, R5, R5
EOR R6, R6, R6
EOR R7, R7, R7
MOVM.IA.W [R0-R7], (R12)
MOVM.IA [R0-R7], (R12)
MOVW 4(R13), g
RET
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for AMD64, FreeBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
#
/*
* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
* See the copyright notice in the ACK home directory, in the file "Copyright".
*/
/* $Id$ */
#include <ack/config.h>
mes 2,_EM_WSIZE,_EM_PSIZE
#if ACKCONF_WANT_FLOAT
exp $frexp
pro $frexp,0
lal 0
loi _EM_DSIZE
fef _EM_DSIZE
lal _EM_DSIZE
loi _EM_PSIZE
sti _EM_WSIZE
ret _EM_DSIZE
end
#endif
| {
"language": "Assembly"
} |
; RUN: opt < %s -basicaa -inline -instcombine -reassociate -dse -disable-output
; PR12245
@a = common global i32 0, align 4
@d = common global i32 0, align 4
define i32 @fn2() nounwind uwtable ssp {
entry:
%0 = load i32, i32* @a, align 4
%dec = add nsw i32 %0, -1
store i32 %dec, i32* @a, align 4
%1 = load i32, i32* @d, align 4
%sub = sub nsw i32 %dec, %1
store i32 %sub, i32* @d, align 4
%2 = load i32, i32* @a, align 4
%dec1 = add nsw i32 %2, -1
store i32 %dec1, i32* @a, align 4
%3 = load i32, i32* @d, align 4
%sub2 = sub nsw i32 %dec1, %3
store i32 %sub2, i32* @d, align 4
%4 = load i32, i32* @a, align 4
%dec3 = add nsw i32 %4, -1
store i32 %dec3, i32* @a, align 4
%5 = load i32, i32* @d, align 4
%sub4 = sub nsw i32 %dec3, %5
store i32 %sub4, i32* @d, align 4
%6 = load i32, i32* @a, align 4
%dec5 = add nsw i32 %6, -1
store i32 %dec5, i32* @a, align 4
%7 = load i32, i32* @d, align 4
%sub6 = sub nsw i32 %dec5, %7
store i32 %sub6, i32* @d, align 4
%8 = load i32, i32* @a, align 4
%dec7 = add nsw i32 %8, -1
store i32 %dec7, i32* @a, align 4
%9 = load i32, i32* @d, align 4
%sub8 = sub nsw i32 %dec7, %9
store i32 %sub8, i32* @d, align 4
ret i32 0
}
define i32 @fn1() nounwind uwtable ssp {
entry:
%call = call i32 @fn2()
ret i32 %call
}
| {
"language": "Assembly"
} |
# Copyright 2013 the V8 project authors. All rights reserved.
# Copyright (C) 2005, 2006, 2007, 2008, 2009 Apple Inc. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS'' AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This test checks that the Function constructor places a newline after the opening brace, for compatibility reasons. It passes if there are no syntax error exceptions.
On success, you will see a series of "PASS" messages, followed by "TEST COMPLETE".
PASS successfullyParsed is true
TEST COMPLETE
| {
"language": "Assembly"
} |
#define LDSO_ARCH "or1k"
#define TPOFF_K 0
#define REL_SYMBOLIC R_OR1K_32
#define REL_GOT R_OR1K_GLOB_DAT
#define REL_PLT R_OR1K_JMP_SLOT
#define REL_RELATIVE R_OR1K_RELATIVE
#define REL_COPY R_OR1K_COPY
#define REL_DTPMOD R_OR1K_TLS_DTPMOD
#define REL_DTPOFF R_OR1K_TLS_DTPOFF
#define REL_TPOFF R_OR1K_TLS_TPOFF
#define CRTJMP(pc,sp) __asm__ __volatile__( \
"l.jr %0 ; l.ori r1,%1,0" : : "r"(pc), "r"(sp) : "memory" )
#define GETFUNCSYM(fp, sym, got) __asm__ ( \
".hidden " #sym " \n" \
" l.jal 1f \n" \
" l.nop \n" \
" .word " #sym "-. \n" \
"1: l.lwz %0, 0(r9) \n" \
" l.add %0, %0, r9 \n" \
: "=r"(*(fp)) : : "memory", "r9" )
| {
"language": "Assembly"
} |
.file "asm-FreeBSD-386.S"
#include <sys/syscall.h>
/*
* executeonnewstack(void *tos, void (*tramp)(void *arg), void *arg)
*/
.type ournewstack,@function
.global executeonnewstack
executeonnewstack:
pushl %ebp
movl %esp, %ebp
pushl %esi
movl 8(%ebp), %esi /* get tos */
subl $4, %esi
movl 16(%ebp), %eax
movl %eax, (%esi) /* stash arg on new stack */
subl $4, %esi
movl 12(%ebp), %eax
movl %eax, (%esi) /* stash tramp on new stack */
mov %esi, %esp /* swap stacks pronto */
popl %eax /* recover the tramp address */
call *%eax /* and jump to it (ho ho) */
/* if we return here, tramp didn't do it's job */
addl $8, %esp /* clean up for pose value */
leal SYS_exit, %eax
int $0x80
/*
* unlockandexit(int *key)
*
* NB: the return status may be rubbish if the stack is reused
* between the unlock and the system call, but this should
* not matter since no task is waiting for the result
*/
.type unlockandexit,@function
.global unlockandexit
unlockandexit:
pushl %ebp
movl %esp, %ebp
movl 8(%ebp), %esi /* get the key address */
pushl $0 /* exit status 0 */
movl $0, %eax /* unlock the stack allocator */
movl %eax, (%esi)
leal SYS_exit, %eax /* call exit */
int $0x80
/*
* umult(ulong m1, ulong m2, ulong *hi)
*/
.type umult,@function
.global umult
umult:
pushl %ebp
movl %esp, %ebp
pushl %ebx
movl 8(%ebp), %eax
movl 12(%ebp), %ebx
mull %ebx
movl 16(%ebp), %ebx
movl %edx, (%ebx)
popl %ebx
popl %ebp
ret
.type FPsave,@function
.global FPsave
FPsave:
pushl %ebp
movl %esp, %ebp
movl 8(%ebp), %eax
fstenv (%eax)
popl %ebp
ret
.type FPrestore,@function
.global FPrestore
FPrestore:
pushl %ebp
movl %esp, %ebp
movl 8(%ebp), %eax
fldenv (%eax)
popl %ebp
ret
.type getcallerpc,@function
.global getcallerpc
getcallerpc:
movl 4(%ebp), %eax
ret
.type _tas,@function
.globl _tas
_tas:
movl $1, %eax
movl 4(%esp), %ecx
xchgl %eax, 0(%ecx)
ret
| {
"language": "Assembly"
} |
RGB 31, 31, 31
RGB 15, 15, 31
RGB 00, 00, 31
RGB 00, 00, 00
RGB 31, 31, 31
RGB 15, 15, 31
RGB 00, 00, 31
RGB 00, 00, 00
RGB 31, 11, 31
RGB 15, 15, 31
RGB 00, 00, 31
RGB 00, 00, 00
RGB 31, 31, 31
RGB 15, 15, 31
RGB 00, 00, 31
RGB 31, 00, 00
RGB 31, 31, 31
RGB 15, 15, 31
RGB 31, 00, 00
RGB 00, 00, 00
RGB 31, 31, 31
RGB 07, 19, 07
RGB 07, 19, 07
RGB 00, 00, 00
| {
"language": "Assembly"
} |
/*
* Copyright (c) 2017, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
L0:
(W&~f0.1)jmpi L416
L16:
cmp (1|M0) (eq)f1.0 null.0<1>:w r24.2<0;1,0>:ub 0x1:uw
(~f1.0) add (1|M0) r25.1<1>:ud r7.12<0;1,0>:uw 0x2:ud
(f1.0) add (1|M0) r25.1<1>:ud r7.12<0;1,0>:uw 0x0:ud
mov (8|M0) r17.0<1>:ud r25.0<8;8,1>:ud
add (1|M0) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB100:ud
mov (1|M0) r16.2<1>:ud 0xD000:ud
send (1|M0) r84:uw r16:ub 0x2 a0.0
add (1|M0) a0.0<1>:ud r23.5<0;1,0>:ud 0x48EB301:ud
or (1|M0) r17.7<1>:ud r17.7<0;1,0>:ud 0x8000000:ud
mov (1|M0) r16.2<1>:ud 0xA000:ud
send (1|M0) r88:uw r16:ub 0x2 a0.0
mov (1|M0) a0.8<1>:uw 0xA00:uw
mov (1|M0) a0.9<1>:uw 0xA80:uw
mov (1|M0) a0.10<1>:uw 0xB00:uw
add (4|M0) a0.12<1>:uw a0.8<4;4,1>:uw 0x40:uw
mov (16|M0) r80.0<1>:uw r90.0<16;16,1>:uw
mov (16|M0) r81.0<1>:uw r91.0<16;16,1>:uw
mov (16|M0) r90.0<1>:uw r92.0<16;16,1>:uw
mov (16|M0) r91.0<1>:uw r93.0<16;16,1>:uw
mov (16|M0) r82.0<1>:uw r94.0<16;16,1>:uw
mov (16|M0) r83.0<1>:uw r95.0<16;16,1>:uw
mov (16|M0) r92.0<1>:uw 0xFFFF:uw
mov (16|M0) r93.0<1>:uw 0xFFFF:uw
mov (16|M0) r94.0<1>:uw 0xFFFF:uw
mov (16|M0) r95.0<1>:uw 0xFFFF:uw
L416:
nop
| {
"language": "Assembly"
} |
int main() {
buf = alloca(3
#ifdef PLATFORM_A
// platform a stuff
+5
+50
#endif
#ifdef PLATFORM_B
/* platform b stuff */
+2
#endif
);
buf = alloca(3
#ifdef PLATFORM_A
// platform a stuff
+5
+50
#endif
#ifdef PLATFORM_B
/* platform b stuff */
+2
#endif
);
}
int other() {
buf = alloca(3
#ifdef PLATFORM_A
// platform a stuff
+5
#endif
#ifdef PLATFORM_B
/* platform b stuff */
+2
#endif
);
buf = alloca(3
+5
+2
);
}
int third() {
buf = alloca(3+5+2);
buf = alloca(3
+5
+2
);
}
| {
"language": "Assembly"
} |
dnl Intel Pentium-4 mpn_divexact_1 -- mpn by limb exact division.
dnl Copyright 2001, 2002, 2007 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C P4: 19.0 cycles/limb
C void mpn_divexact_1 (mp_ptr dst, mp_srcptr src, mp_size_t size,
C mp_limb_t divisor);
C
C Pairs of movd's are used to avoid unaligned loads. Despite the loads not
C being on the dependent chain and there being plenty of cycles available,
C using an unaligned movq on every second iteration measured about 23 c/l.
C
C Using divl for size==1 seems a touch quicker than mul-by-inverse. The mul
C will be about 9+2*4+2*2+10*4+19+12 = 92 cycles latency, though some of
C that might be hidden by out-of-order execution, whereas divl is around 60.
C At size==2 an extra 19 for the mul versus 60 for the divl will see the mul
C faster.
defframe(PARAM_DIVISOR,16)
defframe(PARAM_SIZE, 12)
defframe(PARAM_SRC, 8)
defframe(PARAM_DST, 4)
TEXT
ALIGN(16)
PROLOGUE(mpn_divexact_1)
deflit(`FRAME',0)
movl PARAM_SIZE, %edx
movl PARAM_SRC, %eax
movl PARAM_DIVISOR, %ecx
subl $1, %edx
jnz L(two_or_more)
movl (%eax), %eax
xorl %edx, %edx
divl %ecx
movl PARAM_DST, %ecx
movl %eax, (%ecx)
ret
L(two_or_more):
C eax src
C ebx
C ecx divisor
C edx size-1
movl %ecx, %eax
bsfl %ecx, %ecx C trailing twos
shrl %cl, %eax C d = divisor without twos
movd %eax, %mm6
movd %ecx, %mm7 C shift
shrl %eax C d/2
andl $127, %eax C d/2, 7 bits
ifdef(`PIC',`
LEA( binvert_limb_table, %ecx)
movzbl (%eax,%ecx), %eax C inv 8 bits
',`
movzbl binvert_limb_table(%eax), %eax C inv 8 bits
')
C
movd %eax, %mm5 C inv
movd %eax, %mm0 C inv
pmuludq %mm5, %mm5 C inv*inv
C
pmuludq %mm6, %mm5 C inv*inv*d
paddd %mm0, %mm0 C 2*inv
C
psubd %mm5, %mm0 C inv = 2*inv - inv*inv*d
pxor %mm5, %mm5
paddd %mm0, %mm5
pmuludq %mm0, %mm0 C inv*inv
pcmpeqd %mm4, %mm4
psrlq $32, %mm4 C 0x00000000FFFFFFFF
C
pmuludq %mm6, %mm0 C inv*inv*d
paddd %mm5, %mm5 C 2*inv
movl PARAM_SRC, %eax
movl PARAM_DST, %ecx
pxor %mm1, %mm1 C initial carry limb
C
psubd %mm0, %mm5 C inv = 2*inv - inv*inv*d
ASSERT(e,` C expect d*inv == 1 mod 2^GMP_LIMB_BITS
pushl %eax FRAME_pushl()
movq %mm6, %mm0
pmuludq %mm5, %mm0
movd %mm0, %eax
cmpl $1, %eax
popl %eax FRAME_popl()')
pxor %mm0, %mm0 C initial carry bit
C The dependent chain here is as follows.
C
C latency
C psubq s = (src-cbit) - climb 2
C pmuludq q = s*inverse 8
C pmuludq prod = q*divisor 8
C psrlq climb = high(prod) 2
C --
C 20
C
C Yet the loop measures 19.0 c/l, so obviously there's something gained
C there over a straight reading of the chip documentation.
L(top):
C eax src, incrementing
C ebx
C ecx dst, incrementing
C edx counter, size-1 iterations
C
C mm0 carry bit
C mm1 carry limb
C mm4 0x00000000FFFFFFFF
C mm5 inverse
C mm6 divisor
C mm7 shift
movd (%eax), %mm2
movd 4(%eax), %mm3
addl $4, %eax
punpckldq %mm3, %mm2
psrlq %mm7, %mm2
pand %mm4, %mm2 C src
psubq %mm0, %mm2 C src - cbit
psubq %mm1, %mm2 C src - cbit - climb
movq %mm2, %mm0
psrlq $63, %mm0 C new cbit
pmuludq %mm5, %mm2 C s*inverse
movd %mm2, (%ecx) C q
addl $4, %ecx
movq %mm6, %mm1
pmuludq %mm2, %mm1 C q*divisor
psrlq $32, %mm1 C new climb
subl $1, %edx
jnz L(top)
L(done):
movd (%eax), %mm2
psrlq %mm7, %mm2 C src
psubq %mm0, %mm2 C src - cbit
psubq %mm1, %mm2 C src - cbit - climb
pmuludq %mm5, %mm2 C s*inverse
movd %mm2, (%ecx) C q
emms
ret
EPILOGUE()
ASM_END()
| {
"language": "Assembly"
} |
/* amd64-linux.shlib-init.S -- Linux program entry point & decompressor (Elf shared lib)
*
* This file is part of the UPX executable compressor.
*
* Copyright (C) 1996-2020 Markus Franz Xaver Johannes Oberhumer
* Copyright (C) 1996-2020 Laszlo Molnar
* Copyright (C) 2000-2020 John F. Reiser
* All Rights Reserved.
*
* UPX and the UCL library are free software; you can redistribute them
* and/or modify them under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Markus F.X.J. Oberhumer Laszlo Molnar
* <[email protected]> <[email protected]>
*
* John F. Reiser
* <[email protected]>
*/
#include "arch/amd64/macros.S"
#include "arch/amd64/regs.h"
sz_Ehdr= 64
sz_Phdr= 56
sz_l_info= 12
l_lsize= 8
sz_p_info= 12
sz_b_info= 12
sz_unc= 0
sz_cpr= 4
b_method= 8
PROT_READ= 1
PROT_WRITE= 2
PROT_EXEC= 4
MAP_PRIVATE= 2
MAP_FIXED= 0x10
MAP_ANONYMOUS= 0x20
__NR_mmap= 9 // 64-bit mode only! /usr/include/asm/unistd_64.h
__NR_mprotect= 10
__NR_munmap= 11
__NR_write= 1
__NR_exit= 60
PAGE_SHIFT= 12
PAGE_MASK= (~0<<PAGE_SHIFT)
PAGE_SIZE= -PAGE_MASK
M_NRV2B_LE32=2 // ../conf.h
M_NRV2D_LE32=5
M_NRV2E_LE32=8
// .long offset(.) // detect relocation
// .long offset(user DT_INIT)
// .long offset(escape_hatch)
// .long offset({l_info; p_info; b_info; compressed data})
section ELFMAINX
_start: .globl _start
//// nop; int3; int3
push %rax // space for &DT_INIT
o_uinit= 5*8
push %arg2; push %arg1 // save first two args to DT_INIT()
push %rax // space for &hatch
o_hatch= 2*8
push %arg3 // save third arg to DT_INIT()
push %rbp; mov %rsp,%rbp // frame pointer
call main // push &decompress
ret_main:
/* Returns 0 on success; non-zero on failure. */
decompress: // (uchar const *src, size_t lsrc, uchar *dst, u32 &ldst, uint method)
/* Arguments according to calling convention */
#define src %arg1
#define lsrc %arg2
#define dst %arg3
#define ldst %arg4 /* Out: actually a reference: &len_dst */
#define meth %arg5l
#define methb %arg5b
push %rbp; push %rbx // C callable
push ldst
push dst
addq src,lsrc; push lsrc // &input_eof
section NRV_HEAD
/* Working registers */
#define off %eax /* XXX: 2GB */
#define len %ecx /* XXX: 2GB */
#define lenq %rcx
#define bits %ebx
#define disp %rbp
movq src,%rsi // hardware src for movsb, lodsb
movq dst,%rdi // hardware dst for movsb
xor bits,bits // empty; force refill
xor len,len // create loop invariant
orq $(~0),disp // -1: initial displacement
call setup // push &getbit [TUNED]
ra_setup:
/* AMD64 branch prediction is much worse if there are more than 3 branches
per 16-byte block. The jnextb would suffer unless inlined. getnextb is OK
using closed subroutine to save space, and should be OK on cycles because
CALL+RET should be predicted. getnextb could partially expand, using closed
subroutine only for refill.
*/
/* jump on next bit {0,1} with prediction {y==>likely, n==>unlikely} */
/* Prediction omitted for now. */
/* On refill: prefetch next byte, for latency reduction on literals and offsets. */
#define jnextb0np jnextb0yp
#define jnextb0yp GETBITp; jnc
#define jnextb1np jnextb1yp
#define jnextb1yp GETBITp; jc
#define GETBITp \
addl bits,bits; jnz 0f; \
movl (%rsi),bits; subq $-4,%rsi; \
adcl bits,bits; movb (%rsi),%dl; \
0:
/* Same, but without prefetch (not useful for length of match.) */
#define jnextb0n jnextb0y
#define jnextb0y GETBIT; jnc
#define jnextb1n jnextb1y
#define jnextb1y GETBIT; jc
#define GETBIT \
addl bits,bits; jnz 0f; \
movl (%rsi),bits; subq $-4,%rsi; \
adcl bits,bits; \
0:
/* rotate next bit into bottom bit of reg */
#define getnextbp(reg) call *%r11; adcl reg,reg
#define getnextb(reg) getnextbp(reg)
getbit:
addl bits,bits; jz refill // Carry= next bit
rep; ret
refill:
movl (%rsi),bits; subq $-4,%rsi // next 32 bits; set Carry
adcl bits,bits // LSB= 1 (CarryIn); CarryOut= next bit
movb (%rsi),%dl // speculate: literal, or bottom 8 bits of offset
rep; ret
copy: // In: len, %rdi, disp; Out: 0==len, %rdi, disp; trashes %rax, %rdx
leaq (%rdi,disp),%rax; cmpl $5,len // <=3 is forced
movb (%rax),%dl; jbe copy1 // <=5 for better branch predict
cmpq $-4,disp; ja copy1 // 4-byte chunks would overlap
subl $4,len // adjust for termination cases
copy4:
movl (%rax),%edx; addq $4, %rax; subl $4,len
movl %edx,(%rdi); leaq 4(%rdi),%rdi; jnc copy4
addl $4,len; movb (%rax),%dl; jz copy0
copy1:
incq %rax; movb %dl,(%rdi); subl $1,len
movb (%rax),%dl
leaq 1(%rdi),%rdi; jnz copy1
copy0:
rep; ret
setup:
cld
pop %r11 // addq $ getbit - ra_setup,%r11 # &getbit
section NRV2E
#include "arch/amd64/nrv2e_d.S"
section NRV2D
#include "arch/amd64/nrv2d_d.S"
section NRV2B
#include "arch/amd64/nrv2b_d.S"
#include "arch/amd64/lzma_d.S"
section NRV_TAIL
// empty
#undef off
#undef len
#undef lenq
#undef bits
#undef disp
section ELFMAINY
eof:
pop %rcx // &input_eof
movq %rsi,%rax; subq %rcx,%rax // src -= eof; // return 0: good; else: bad
pop %rdx; subq %rdx,%rdi // dst -= original dst
pop %rcx; movl %edi,(%rcx) // actual length used at dst XXX: 4GB
pop %rbx; pop %rbp
ret
msg_SELinux:
push $ L71 - L70; pop %arg3 // length
call L72
L70:
.asciz "PROT_EXEC|PROT_WRITE failed.\n"
L71:
// IDENTSTR goes here
section ELFMAINZ
L72:
pop %arg2 // message text
push $2; pop %arg1 // fd stderr
push $ __NR_write; pop %rax
syscall
die:
push $127; pop %arg1
push $ __NR_exit; pop %rax
syscall
main:
//// nop; int3; int3
// 1. allocate temporary pages
// 2. copy to temporary pages:
// fragment of page below dst; compressed src;
// decompress+unfilter; supervise
// 3. mmap destination pages for decompressed data
// 4. create escape hatch
// 5. jump to temporary pages
// 6. uncompress
// 7. unfilter
// 8. mprotect decompressed pages
// 9 setup args for unmap of temp pages
// 10. jump to escape hatch
// 11. unmap temporary pages
// 12. goto user DT_INIT
pop %rdx // &decompress
lea _start - decompress - 4*4(%rdx),%rsi
mov %rsi,%rcx
lodsl; sub %rax,%rcx; //mov %rcx,o_reloc(%rbp)
lodsl; add %rcx,%rax; mov %rax,o_uinit(%rbp) // reloc DT_INIT for step 12
lodsl; add %rcx,%rax; mov %rax,o_hatch(%rbp) // reloc &hatch for step 10
lodsl; lea (%rcx,%rax),%rdi // &l_info; also destination for decompress
lea sz_l_info+sz_p_info(%rdi),%rsi // &b_info
push %rax; push %rax // param space: munmap temp pages step 9
p_unmap= -2*8
lodsl; lodsl; add %rax,%rsi; lodsl // skip unpack helper block
lodsl // eax=dstlen
mov %rdi,%rcx
and $~PAGE_MASK,%ecx // %ecx= fragment
add %rcx,%rax; push %rax // params: mprotect restored pages step 8
sub %rcx,%rdi; push %rdi
p_mprot= -4*8
sub %rcx,%rax // restore
add %rcx,%rdi
push %rcx // fragment
o_frag = -5*8
call L210
#include "arch/amd64/bxx.S"
L210:
o_unflt= -6*8
movzbl b_method-4+1(%rsi),%ecx; push %rcx // ftid
movzbl b_method-4+2(%rsi),%ecx; push %rcx // cto8
push %rax; mov %rsp,%rcx // dstlen also for unfilter step 7
push %rdi // dst param for unfilter step 7
p_unflt= -10*8
push %rdx // &decompress
o_uncpr= -11*8
lodsl; mov %eax,%edx // %rdx= srclen
lodsl; push %rax // method,filter,cto,junk
push %rcx // &dstlen
push %rdi // dst
push %rdx // srclen
push %rsi // src; arglist ready for decompress step 6
p_uncpr= -16*8
mov o_uncpr(%rbp),%rax; add -4(%rax),%edx // l_d_cpr + l_f_unc
mov o_unflt(%rbp),%rax; add -4(%rax),%edx // l_d_cpr + l_f_unc + l_f_unf
call L220
supervise:
// Allocate pages for result of decompressing.
// These replace the compressed source and the following hole.
push $0; pop %arg6
push $0; pop %arg5
push $MAP_PRIVATE|MAP_ANONYMOUS|MAP_FIXED; pop %sys4
push $PROT_READ|PROT_WRITE; pop %arg3
movq p_mprot+8(%rbp),%arg2 // dstlen
movq p_mprot (%rbp),%arg1 // dst
push $__NR_mmap; pop %rax; syscall
cmp %arg1,%rax; je 0f; hlt; 0:
// Restore fragment of page below dst
movl o_frag(%rbp),%ecx
mov %rax,%rdi
mov p_unmap(%rbp),%rsi
add $3,%ecx; shr $2,%ecx // FIXME: is this safe?
rep movsl
pop %arg1
pop %arg2
pop %arg3
pop %arg4
pop %arg5
pop %rax; call *%rax // decompress
//p_unflt
pop %arg1
pop %arg2
lea (%arg1,%arg2),%rax
movl $0x5e5f050f, (%rax) // "syscall; pop %rdi; pop %rsi"
movb $0xc3,4(%rax) // "ret"
mov %rax,o_hatch(%rbp) // hatch beyond .text
pop %arg3
pop %arg4
pop %rax;
test %arg4,%arg4; je 0f // 0==ftid ==> no filter
call *%rax // unfilter
0:
pop %rcx // toss fragment
//p_mprot
pop %arg1 // dst including fragment
pop %arg2 // dstlen
push $PROT_READ|PROT_EXEC; pop %arg3
push $__NR_mprotect; pop %rax; syscall
//p_unmap
pop %arg1 // &temp pages
pop %arg2 // length
push $__NR_munmap; pop %rax
//// nop; int3; int3
pop %rbp
pop %arg3 // third arg to DT_INIT()
ret // goto escape hatch
//hatch:
// syscall // munmap temporary pages
// pop %arg1 // first two args to DT_INIT()
// pop %arg2
// ret // goto user DT_INIT
L220:
mov o_frag(%rbp),%arg2l // fragment
add %edx,%arg2l // + l_d_cpr + l_f_unc + l_f_unf
pop %rax; push %rax // &supervise
add -4(%rax),%arg2l // total length to allocate
// Allocate pages to hold temporary copy.
push $0; pop %arg6
push $0; pop %arg5
push $MAP_PRIVATE|MAP_ANONYMOUS; pop %sys4
push $PROT_READ|PROT_WRITE|PROT_EXEC; pop %arg3
mov %arg2,p_unmap+8(%rbp) // length to unmap
push $0; pop %arg1 // addr
push $__NR_mmap; pop %rax; syscall
cmpq $PAGE_MASK,%rax; jb 0f; hlt; 0:
mov %rax,p_unmap (%rbp) // addr
mov %rax,%rdi // %rdi= dst
pop %rax // &supervise
mov o_frag(%rbp),%ecx // fragment
//p_uncpr
mov p_mprot(%rbp),%rsi
add $3,%ecx; shr $2,%ecx // FIXME: is this safe?
rep movsl // copy the fragment
pop %rsi // &src data (after fragment)
pop %rcx; push %rcx // length
push %rdi // &copied data (after fragment)
add $3,%ecx; shr $2,%ecx
rep movsl // copy compressed data
mov o_uncpr(%rbp),%rsi
mov %rdi,o_uncpr(%rbp)
mov -4(%rsi),%ecx
rep movsb // copy decompressor
mov o_unflt(%rbp),%rsi
mov %rdi,o_unflt(%rbp)
mov -4(%rsi),%ecx
rep movsb // copy unfilter
//o_super
mov %rax,%rsi // %rsi= &supervise
push %rdi // &copied
mov -4(%rsi),%ecx
rep movsb // copy supervisor
ret // goto copied supervise:
/*__XTHEENDX__*/
/* vim:set ts=8 sw=8 et: */
| {
"language": "Assembly"
} |
#if 0
//
// Generated by Microsoft (R) HLSL Shader Compiler 10.0.10011.16384
//
//
// Buffer Definitions:
//
// cbuffer CB_SHADOWS_DATA
// {
//
// struct ShadowsData
// {
//
// struct Camera
// {
//
// float4x4 m_View; // Offset: 0
// float4x4 m_Projection; // Offset: 64
// float4x4 m_ViewProjection; // Offset: 128
// float4x4 m_View_Inv; // Offset: 192
// float4x4 m_Projection_Inv; // Offset: 256
// float4x4 m_ViewProjection_Inv;// Offset: 320
// float3 m_Position; // Offset: 384
// float m_Fov; // Offset: 396
// float3 m_Direction; // Offset: 400
// float m_FarPlane; // Offset: 412
// float3 m_Right; // Offset: 416
// float m_NearPlane; // Offset: 428
// float3 m_Up; // Offset: 432
// float m_Aspect; // Offset: 444
// float4 m_Color; // Offset: 448
//
// } m_Viewer; // Offset: 0
// float2 m_Size; // Offset: 464
// float2 m_SizeInv; // Offset: 472
//
// struct ShadowsLightData
// {
//
// struct Camera
// {
//
// float4x4 m_View; // Offset: 480
// float4x4 m_Projection; // Offset: 544
// float4x4 m_ViewProjection;// Offset: 608
// float4x4 m_View_Inv; // Offset: 672
// float4x4 m_Projection_Inv;// Offset: 736
// float4x4 m_ViewProjection_Inv;// Offset: 800
// float3 m_Position; // Offset: 864
// float m_Fov; // Offset: 876
// float3 m_Direction; // Offset: 880
// float m_FarPlane; // Offset: 892
// float3 m_Right; // Offset: 896
// float m_NearPlane; // Offset: 908
// float3 m_Up; // Offset: 912
// float m_Aspect; // Offset: 924
// float4 m_Color; // Offset: 928
//
// } m_Camera; // Offset: 480
// float2 m_Size; // Offset: 944
// float2 m_SizeInv; // Offset: 952
// float4 m_Region; // Offset: 960
// float4 m_Weight; // Offset: 976
// float m_SunArea; // Offset: 992
// float m_DepthTestOffset; // Offset: 996
// float m_NormalOffsetScale; // Offset: 1000
// uint m_ArraySlice; // Offset: 1004
//
// } m_Light[6]; // Offset: 480
// uint m_ActiveLightCount; // Offset: 3648
// float3 pad3; // Offset: 3652
//
// } g_cbShadowsData; // Offset: 0 Size: 3664
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim HLSL Bind Count
// ------------------------------ ---------- ------- ----------- -------------- ------
// g_scsPoint sampler_c NA NA s2 1
// g_t2dDepth texture float 2d t0 1
// g_t2dShadow texture float 2d t2 1
// CB_SHADOWS_DATA cbuffer NA NA cb0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION 0 xyzw 0 POS float xy
// TEXCOORD 0 xy 1 NONE float
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
ps_5_0
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[229], dynamicIndexed
dcl_sampler s2, mode_comparison
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t2
dcl_input_ps_siv linear noperspective v0.xy, position
dcl_output o0.xyzw
dcl_temps 11
mul r0.x, v0.x, cb0[29].z
mul r0.y, v0.y, -cb0[29].w
add r0.xy, r0.xyxx, l(-0.500000, 0.500000, 0.000000, 0.000000)
add r0.xy, r0.xyxx, r0.xyxx
ftoi r1.xy, v0.xyxx
mov r1.zw, l(0,0,0,0)
ld_indexable(texture2d)(float,float,float,float) r0.z, r1.xyzw, t0.yzxw
mov r0.w, l(1.000000)
dp4 r1.x, r0.xyzw, cb0[20].xyzw
dp4 r1.y, r0.xyzw, cb0[21].xyzw
dp4 r1.z, r0.xyzw, cb0[22].xyzw
dp4 r1.w, r0.xyzw, cb0[23].xyzw
div r0.xyzw, r1.xyzw, r1.wwww
mov r1.w, r0.w
mov r2.xz, l(-3.000000,0,-1.000000,0)
mov r3.xz, l(1.000000,0,3.000000,0)
mov r1.xyz, r0.xyzx
mov r0.w, l(0)
mov r4.x, l(1.000000)
loop
uge r4.y, r0.w, cb0[228].x
breakc_nz r4.y
imul null, r4.y, r0.w, l(33)
dp4 r5.x, r1.xyzw, cb0[r4.y + 38].xyzw
dp4 r5.y, r1.xyzw, cb0[r4.y + 39].xyzw
dp4 r5.z, r1.xyzw, cb0[r4.y + 40].xyzw
dp4 r4.z, r1.xyzw, cb0[r4.y + 41].xyzw
div r5.xyz, r5.xyzx, r4.zzzz
mad r6.xy, r5.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000), l(0.500000, 0.500000, 0.000000, 0.000000)
add r4.z, -r6.y, l(1.000000)
ge r4.w, r6.x, l(0.000000)
ge r5.x, l(1.000000), r6.x
and r4.w, r4.w, r5.x
ge r5.x, r4.z, l(0.000000)
and r4.w, r4.w, r5.x
ge r4.z, l(1.000000), r4.z
and r4.z, r4.z, r4.w
ge r4.w, r5.z, l(0.000000)
and r4.z, r4.w, r4.z
ge r4.w, l(1.000000), r5.z
and r4.z, r4.w, r4.z
if_nz r4.z
add r4.zw, -cb0[r4.y + 60].xxxy, cb0[r4.y + 60].zzzw
add r5.x, r5.z, -cb0[r4.y + 62].y
add r6.z, -r6.y, l(1.000000)
mad r5.yz, cb0[r4.y + 59].yyxy, r6.zzxz, l(0.000000, 0.500000, 0.500000, 0.000000)
round_ni r6.xy, r5.zyzz
frc r5.yz, r5.yyzy
mul r6.xy, r6.xyxx, cb0[r4.y + 59].zwzz
mad r6.xy, r6.xyxx, r4.zwzz, cb0[r4.y + 60].xyxx
add r6.zw, -r5.yyyz, l(0.000000, 0.000000, 1.000000, 1.000000)
mov r5.w, l(0)
mov r7.x, l(-3)
loop
ilt r7.y, l(3), r7.x
breakc_nz r7.y
itof r2.yw, r7.xxxx
mul r8.xyzw, r2.xyzw, cb0[r4.y + 59].zwzw
mad r8.xyzw, r8.xyzw, r4.zwzw, r6.xyxy
gather4_c_indexable(texture2d)(float,float,float,float) r9.xyzw, r8.xyxx, t2.xyzw, s2.x, r5.x
ieq r2.yw, r7.xxxx, l(0, -3, 0, 3)
movc r10.w, r2.y, r6.z, l(1.000000)
movc r10.x, r2.w, r5.y, l(1.000000)
mul r10.yz, r6.wwww, r10.xxwx
dp4 r2.y, r10.yxwz, r9.xyzw
add r2.y, r2.y, r5.w
gather4_c_indexable(texture2d)(float,float,float,float) r8.xyzw, r8.zwzz, t2.xyzw, s2.x, r5.x
dp4 r2.w, r10.xxww, r8.xyzw
add r2.y, r2.w, r2.y
itof r3.yw, r7.xxxx
mul r8.xyzw, r3.xyzw, cb0[r4.y + 59].zwzw
mad r8.xyzw, r8.xyzw, r4.zwzw, r6.xyxy
gather4_c_indexable(texture2d)(float,float,float,float) r9.xyzw, r8.xyxx, t2.xyzw, s2.x, r5.x
dp4 r2.w, r10.xxww, r9.xyzw
add r2.y, r2.w, r2.y
gather4_c_indexable(texture2d)(float,float,float,float) r8.xyzw, r8.zwzz, t2.xyzw, s2.x, r5.x
mul r10.yz, r5.zzzz, r10.xxwx
dp4 r2.w, r10.xyzw, r8.xyzw
add r5.w, r2.w, r2.y
iadd r7.x, r7.x, l(2)
endloop
mul r2.y, r5.w, l(0.020408)
else
mov r2.y, l(1.000000)
endif
min r4.x, r2.y, r4.x
iadd r0.w, r0.w, l(1)
endloop
mov o0.xyzw, r4.xxxx
ret
// Approximately 90 instruction slots used
#endif
const BYTE PS_SF_T2D_UNIFORM_TEX_FETCH_GATHER4_TAP_TYPE_FIXED_NORMAL_OPTION_NONE_FILTER_SIZE_7_Data[] =
{
68, 88, 66, 67, 135, 161,
198, 139, 158, 180, 214, 253,
12, 39, 92, 179, 1, 137,
72, 21, 1, 0, 0, 0,
212, 17, 0, 0, 5, 0,
0, 0, 52, 0, 0, 0,
236, 5, 0, 0, 68, 6,
0, 0, 120, 6, 0, 0,
56, 17, 0, 0, 82, 68,
69, 70, 176, 5, 0, 0,
1, 0, 0, 0, 240, 0,
0, 0, 4, 0, 0, 0,
60, 0, 0, 0, 0, 5,
255, 255, 0, 1, 0, 0,
124, 5, 0, 0, 82, 68,
49, 49, 60, 0, 0, 0,
24, 0, 0, 0, 32, 0,
0, 0, 40, 0, 0, 0,
36, 0, 0, 0, 12, 0,
0, 0, 0, 0, 0, 0,
188, 0, 0, 0, 3, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 2, 0, 0, 0,
1, 0, 0, 0, 3, 0,
0, 0, 199, 0, 0, 0,
2, 0, 0, 0, 5, 0,
0, 0, 4, 0, 0, 0,
255, 255, 255, 255, 0, 0,
0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 210, 0,
0, 0, 2, 0, 0, 0,
5, 0, 0, 0, 4, 0,
0, 0, 255, 255, 255, 255,
2, 0, 0, 0, 1, 0,
0, 0, 1, 0, 0, 0,
222, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 1, 0,
0, 0, 103, 95, 115, 99,
115, 80, 111, 105, 110, 116,
0, 103, 95, 116, 50, 100,
68, 101, 112, 116, 104, 0,
103, 95, 116, 50, 100, 83,
104, 97, 100, 111, 119, 0,
67, 66, 95, 83, 72, 65,
68, 79, 87, 83, 95, 68,
65, 84, 65, 0, 171, 171,
222, 0, 0, 0, 1, 0,
0, 0, 8, 1, 0, 0,
80, 14, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
48, 1, 0, 0, 0, 0,
0, 0, 80, 14, 0, 0,
2, 0, 0, 0, 88, 5,
0, 0, 0, 0, 0, 0,
255, 255, 255, 255, 0, 0,
0, 0, 255, 255, 255, 255,
0, 0, 0, 0, 103, 95,
99, 98, 83, 104, 97, 100,
111, 119, 115, 68, 97, 116,
97, 0, 83, 104, 97, 100,
111, 119, 115, 68, 97, 116,
97, 0, 109, 95, 86, 105,
101, 119, 101, 114, 0, 67,
97, 109, 101, 114, 97, 0,
109, 95, 86, 105, 101, 119,
0, 102, 108, 111, 97, 116,
52, 120, 52, 0, 3, 0,
3, 0, 4, 0, 4, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
99, 1, 0, 0, 109, 95,
80, 114, 111, 106, 101, 99,
116, 105, 111, 110, 0, 109,
95, 86, 105, 101, 119, 80,
114, 111, 106, 101, 99, 116,
105, 111, 110, 0, 109, 95,
86, 105, 101, 119, 95, 73,
110, 118, 0, 109, 95, 80,
114, 111, 106, 101, 99, 116,
105, 111, 110, 95, 73, 110,
118, 0, 109, 95, 86, 105,
101, 119, 80, 114, 111, 106,
101, 99, 116, 105, 111, 110,
95, 73, 110, 118, 0, 109,
95, 80, 111, 115, 105, 116,
105, 111, 110, 0, 102, 108,
111, 97, 116, 51, 0, 171,
171, 171, 1, 0, 3, 0,
1, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 234, 1,
0, 0, 109, 95, 70, 111,
118, 0, 102, 108, 111, 97,
116, 0, 0, 0, 3, 0,
1, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 30, 2,
0, 0, 109, 95, 68, 105,
114, 101, 99, 116, 105, 111,
110, 0, 109, 95, 70, 97,
114, 80, 108, 97, 110, 101,
0, 109, 95, 82, 105, 103,
104, 116, 0, 109, 95, 78,
101, 97, 114, 80, 108, 97,
110, 101, 0, 109, 95, 85,
112, 0, 109, 95, 65, 115,
112, 101, 99, 116, 0, 109,
95, 67, 111, 108, 111, 114,
0, 102, 108, 111, 97, 116,
52, 0, 1, 0, 3, 0,
1, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 137, 2,
0, 0, 92, 1, 0, 0,
108, 1, 0, 0, 0, 0,
0, 0, 144, 1, 0, 0,
108, 1, 0, 0, 64, 0,
0, 0, 157, 1, 0, 0,
108, 1, 0, 0, 128, 0,
0, 0, 174, 1, 0, 0,
108, 1, 0, 0, 192, 0,
0, 0, 185, 1, 0, 0,
108, 1, 0, 0, 0, 1,
0, 0, 202, 1, 0, 0,
108, 1, 0, 0, 64, 1,
0, 0, 223, 1, 0, 0,
244, 1, 0, 0, 128, 1,
0, 0, 24, 2, 0, 0,
36, 2, 0, 0, 140, 1,
0, 0, 72, 2, 0, 0,
244, 1, 0, 0, 144, 1,
0, 0, 84, 2, 0, 0,
36, 2, 0, 0, 156, 1,
0, 0, 95, 2, 0, 0,
244, 1, 0, 0, 160, 1,
0, 0, 103, 2, 0, 0,
36, 2, 0, 0, 172, 1,
0, 0, 115, 2, 0, 0,
244, 1, 0, 0, 176, 1,
0, 0, 120, 2, 0, 0,
36, 2, 0, 0, 188, 1,
0, 0, 129, 2, 0, 0,
144, 2, 0, 0, 192, 1,
0, 0, 5, 0, 0, 0,
1, 0, 116, 0, 0, 0,
15, 0, 180, 2, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 85, 1,
0, 0, 109, 95, 83, 105,
122, 101, 0, 102, 108, 111,
97, 116, 50, 0, 171, 171,
1, 0, 3, 0, 1, 0,
2, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 147, 3, 0, 0,
109, 95, 83, 105, 122, 101,
73, 110, 118, 0, 109, 95,
76, 105, 103, 104, 116, 0,
83, 104, 97, 100, 111, 119,
115, 76, 105, 103, 104, 116,
68, 97, 116, 97, 0, 109,
95, 67, 97, 109, 101, 114,
97, 0, 109, 95, 82, 101,
103, 105, 111, 110, 0, 109,
95, 87, 101, 105, 103, 104,
116, 0, 109, 95, 83, 117,
110, 65, 114, 101, 97, 0,
109, 95, 68, 101, 112, 116,
104, 84, 101, 115, 116, 79,
102, 102, 115, 101, 116, 0,
109, 95, 78, 111, 114, 109,
97, 108, 79, 102, 102, 115,
101, 116, 83, 99, 97, 108,
101, 0, 109, 95, 65, 114,
114, 97, 121, 83, 108, 105,
99, 101, 0, 100, 119, 111,
114, 100, 0, 171, 171, 171,
0, 0, 19, 0, 1, 0,
1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 59, 4, 0, 0,
227, 3, 0, 0, 104, 3,
0, 0, 0, 0, 0, 0,
140, 3, 0, 0, 156, 3,
0, 0, 208, 1, 0, 0,
192, 3, 0, 0, 156, 3,
0, 0, 216, 1, 0, 0,
236, 3, 0, 0, 144, 2,
0, 0, 224, 1, 0, 0,
245, 3, 0, 0, 144, 2,
0, 0, 240, 1, 0, 0,
254, 3, 0, 0, 36, 2,
0, 0, 0, 2, 0, 0,
8, 4, 0, 0, 36, 2,
0, 0, 4, 2, 0, 0,
26, 4, 0, 0, 36, 2,
0, 0, 8, 2, 0, 0,
46, 4, 0, 0, 68, 4,
0, 0, 12, 2, 0, 0,
5, 0, 0, 0, 1, 0,
132, 0, 6, 0, 9, 0,
104, 4, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 210, 3, 0, 0,
109, 95, 65, 99, 116, 105,
118, 101, 76, 105, 103, 104,
116, 67, 111, 117, 110, 116,
0, 112, 97, 100, 51, 0,
76, 1, 0, 0, 104, 3,
0, 0, 0, 0, 0, 0,
140, 3, 0, 0, 156, 3,
0, 0, 208, 1, 0, 0,
192, 3, 0, 0, 156, 3,
0, 0, 216, 1, 0, 0,
202, 3, 0, 0, 212, 4,
0, 0, 224, 1, 0, 0,
248, 4, 0, 0, 68, 4,
0, 0, 64, 14, 0, 0,
11, 5, 0, 0, 244, 1,
0, 0, 68, 14, 0, 0,
5, 0, 0, 0, 1, 0,
148, 3, 0, 0, 6, 0,
16, 5, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 64, 1, 0, 0,
77, 105, 99, 114, 111, 115,
111, 102, 116, 32, 40, 82,
41, 32, 72, 76, 83, 76,
32, 83, 104, 97, 100, 101,
114, 32, 67, 111, 109, 112,
105, 108, 101, 114, 32, 49,
48, 46, 48, 46, 49, 48,
48, 49, 49, 46, 49, 54,
51, 56, 52, 0, 73, 83,
71, 78, 80, 0, 0, 0,
2, 0, 0, 0, 8, 0,
0, 0, 56, 0, 0, 0,
0, 0, 0, 0, 1, 0,
0, 0, 3, 0, 0, 0,
0, 0, 0, 0, 15, 3,
0, 0, 68, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 3, 0, 0, 0,
1, 0, 0, 0, 3, 0,
0, 0, 83, 86, 95, 80,
79, 83, 73, 84, 73, 79,
78, 0, 84, 69, 88, 67,
79, 79, 82, 68, 0, 171,
171, 171, 79, 83, 71, 78,
44, 0, 0, 0, 1, 0,
0, 0, 8, 0, 0, 0,
32, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 0, 0,
0, 0, 15, 0, 0, 0,
83, 86, 95, 84, 97, 114,
103, 101, 116, 0, 171, 171,
83, 72, 69, 88, 184, 10,
0, 0, 80, 0, 0, 0,
174, 2, 0, 0, 106, 8,
0, 1, 89, 8, 0, 4,
70, 142, 32, 0, 0, 0,
0, 0, 229, 0, 0, 0,
90, 8, 0, 3, 0, 96,
16, 0, 2, 0, 0, 0,
88, 24, 0, 4, 0, 112,
16, 0, 0, 0, 0, 0,
85, 85, 0, 0, 88, 24,
0, 4, 0, 112, 16, 0,
2, 0, 0, 0, 85, 85,
0, 0, 100, 32, 0, 4,
50, 16, 16, 0, 0, 0,
0, 0, 1, 0, 0, 0,
101, 0, 0, 3, 242, 32,
16, 0, 0, 0, 0, 0,
104, 0, 0, 2, 11, 0,
0, 0, 56, 0, 0, 8,
18, 0, 16, 0, 0, 0,
0, 0, 10, 16, 16, 0,
0, 0, 0, 0, 42, 128,
32, 0, 0, 0, 0, 0,
29, 0, 0, 0, 56, 0,
0, 9, 34, 0, 16, 0,
0, 0, 0, 0, 26, 16,
16, 0, 0, 0, 0, 0,
58, 128, 32, 128, 65, 0,
0, 0, 0, 0, 0, 0,
29, 0, 0, 0, 0, 0,
0, 10, 50, 0, 16, 0,
0, 0, 0, 0, 70, 0,
16, 0, 0, 0, 0, 0,
2, 64, 0, 0, 0, 0,
0, 191, 0, 0, 0, 63,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 7,
50, 0, 16, 0, 0, 0,
0, 0, 70, 0, 16, 0,
0, 0, 0, 0, 70, 0,
16, 0, 0, 0, 0, 0,
27, 0, 0, 5, 50, 0,
16, 0, 1, 0, 0, 0,
70, 16, 16, 0, 0, 0,
0, 0, 54, 0, 0, 8,
194, 0, 16, 0, 1, 0,
0, 0, 2, 64, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 45, 0,
0, 137, 194, 0, 0, 128,
67, 85, 21, 0, 66, 0,
16, 0, 0, 0, 0, 0,
70, 14, 16, 0, 1, 0,
0, 0, 150, 124, 16, 0,
0, 0, 0, 0, 54, 0,
0, 5, 130, 0, 16, 0,
0, 0, 0, 0, 1, 64,
0, 0, 0, 0, 128, 63,
17, 0, 0, 8, 18, 0,
16, 0, 1, 0, 0, 0,
70, 14, 16, 0, 0, 0,
0, 0, 70, 142, 32, 0,
0, 0, 0, 0, 20, 0,
0, 0, 17, 0, 0, 8,
34, 0, 16, 0, 1, 0,
0, 0, 70, 14, 16, 0,
0, 0, 0, 0, 70, 142,
32, 0, 0, 0, 0, 0,
21, 0, 0, 0, 17, 0,
0, 8, 66, 0, 16, 0,
1, 0, 0, 0, 70, 14,
16, 0, 0, 0, 0, 0,
70, 142, 32, 0, 0, 0,
0, 0, 22, 0, 0, 0,
17, 0, 0, 8, 130, 0,
16, 0, 1, 0, 0, 0,
70, 14, 16, 0, 0, 0,
0, 0, 70, 142, 32, 0,
0, 0, 0, 0, 23, 0,
0, 0, 14, 0, 0, 7,
242, 0, 16, 0, 0, 0,
0, 0, 70, 14, 16, 0,
1, 0, 0, 0, 246, 15,
16, 0, 1, 0, 0, 0,
54, 0, 0, 5, 130, 0,
16, 0, 1, 0, 0, 0,
58, 0, 16, 0, 0, 0,
0, 0, 54, 0, 0, 8,
82, 0, 16, 0, 2, 0,
0, 0, 2, 64, 0, 0,
0, 0, 64, 192, 0, 0,
0, 0, 0, 0, 128, 191,
0, 0, 0, 0, 54, 0,
0, 8, 82, 0, 16, 0,
3, 0, 0, 0, 2, 64,
0, 0, 0, 0, 128, 63,
0, 0, 0, 0, 0, 0,
64, 64, 0, 0, 0, 0,
54, 0, 0, 5, 114, 0,
16, 0, 1, 0, 0, 0,
70, 2, 16, 0, 0, 0,
0, 0, 54, 0, 0, 5,
130, 0, 16, 0, 0, 0,
0, 0, 1, 64, 0, 0,
0, 0, 0, 0, 54, 0,
0, 5, 18, 0, 16, 0,
4, 0, 0, 0, 1, 64,
0, 0, 0, 0, 128, 63,
48, 0, 0, 1, 80, 0,
0, 8, 34, 0, 16, 0,
4, 0, 0, 0, 58, 0,
16, 0, 0, 0, 0, 0,
10, 128, 32, 0, 0, 0,
0, 0, 228, 0, 0, 0,
3, 0, 4, 3, 26, 0,
16, 0, 4, 0, 0, 0,
38, 0, 0, 8, 0, 208,
0, 0, 34, 0, 16, 0,
4, 0, 0, 0, 58, 0,
16, 0, 0, 0, 0, 0,
1, 64, 0, 0, 33, 0,
0, 0, 17, 0, 0, 10,
18, 0, 16, 0, 5, 0,
0, 0, 70, 14, 16, 0,
1, 0, 0, 0, 70, 142,
32, 6, 0, 0, 0, 0,
38, 0, 0, 0, 26, 0,
16, 0, 4, 0, 0, 0,
17, 0, 0, 10, 34, 0,
16, 0, 5, 0, 0, 0,
70, 14, 16, 0, 1, 0,
0, 0, 70, 142, 32, 6,
0, 0, 0, 0, 39, 0,
0, 0, 26, 0, 16, 0,
4, 0, 0, 0, 17, 0,
0, 10, 66, 0, 16, 0,
5, 0, 0, 0, 70, 14,
16, 0, 1, 0, 0, 0,
70, 142, 32, 6, 0, 0,
0, 0, 40, 0, 0, 0,
26, 0, 16, 0, 4, 0,
0, 0, 17, 0, 0, 10,
66, 0, 16, 0, 4, 0,
0, 0, 70, 14, 16, 0,
1, 0, 0, 0, 70, 142,
32, 6, 0, 0, 0, 0,
41, 0, 0, 0, 26, 0,
16, 0, 4, 0, 0, 0,
14, 0, 0, 7, 114, 0,
16, 0, 5, 0, 0, 0,
70, 2, 16, 0, 5, 0,
0, 0, 166, 10, 16, 0,
4, 0, 0, 0, 50, 0,
0, 15, 50, 0, 16, 0,
6, 0, 0, 0, 70, 0,
16, 0, 5, 0, 0, 0,
2, 64, 0, 0, 0, 0,
0, 63, 0, 0, 0, 63,
0, 0, 0, 0, 0, 0,
0, 0, 2, 64, 0, 0,
0, 0, 0, 63, 0, 0,
0, 63, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 8, 66, 0, 16, 0,
4, 0, 0, 0, 26, 0,
16, 128, 65, 0, 0, 0,
6, 0, 0, 0, 1, 64,
0, 0, 0, 0, 128, 63,
29, 0, 0, 7, 130, 0,
16, 0, 4, 0, 0, 0,
10, 0, 16, 0, 6, 0,
0, 0, 1, 64, 0, 0,
0, 0, 0, 0, 29, 0,
0, 7, 18, 0, 16, 0,
5, 0, 0, 0, 1, 64,
0, 0, 0, 0, 128, 63,
10, 0, 16, 0, 6, 0,
0, 0, 1, 0, 0, 7,
130, 0, 16, 0, 4, 0,
0, 0, 58, 0, 16, 0,
4, 0, 0, 0, 10, 0,
16, 0, 5, 0, 0, 0,
29, 0, 0, 7, 18, 0,
16, 0, 5, 0, 0, 0,
42, 0, 16, 0, 4, 0,
0, 0, 1, 64, 0, 0,
0, 0, 0, 0, 1, 0,
0, 7, 130, 0, 16, 0,
4, 0, 0, 0, 58, 0,
16, 0, 4, 0, 0, 0,
10, 0, 16, 0, 5, 0,
0, 0, 29, 0, 0, 7,
66, 0, 16, 0, 4, 0,
0, 0, 1, 64, 0, 0,
0, 0, 128, 63, 42, 0,
16, 0, 4, 0, 0, 0,
1, 0, 0, 7, 66, 0,
16, 0, 4, 0, 0, 0,
42, 0, 16, 0, 4, 0,
0, 0, 58, 0, 16, 0,
4, 0, 0, 0, 29, 0,
0, 7, 130, 0, 16, 0,
4, 0, 0, 0, 42, 0,
16, 0, 5, 0, 0, 0,
1, 64, 0, 0, 0, 0,
0, 0, 1, 0, 0, 7,
66, 0, 16, 0, 4, 0,
0, 0, 58, 0, 16, 0,
4, 0, 0, 0, 42, 0,
16, 0, 4, 0, 0, 0,
29, 0, 0, 7, 130, 0,
16, 0, 4, 0, 0, 0,
1, 64, 0, 0, 0, 0,
128, 63, 42, 0, 16, 0,
5, 0, 0, 0, 1, 0,
0, 7, 66, 0, 16, 0,
4, 0, 0, 0, 58, 0,
16, 0, 4, 0, 0, 0,
42, 0, 16, 0, 4, 0,
0, 0, 31, 0, 4, 3,
42, 0, 16, 0, 4, 0,
0, 0, 0, 0, 0, 14,
194, 0, 16, 0, 4, 0,
0, 0, 6, 132, 32, 134,
65, 0, 0, 0, 0, 0,
0, 0, 60, 0, 0, 0,
26, 0, 16, 0, 4, 0,
0, 0, 166, 142, 32, 6,
0, 0, 0, 0, 60, 0,
0, 0, 26, 0, 16, 0,
4, 0, 0, 0, 0, 0,
0, 11, 18, 0, 16, 0,
5, 0, 0, 0, 42, 0,
16, 0, 5, 0, 0, 0,
26, 128, 32, 134, 65, 0,
0, 0, 0, 0, 0, 0,
62, 0, 0, 0, 26, 0,
16, 0, 4, 0, 0, 0,
0, 0, 0, 8, 66, 0,
16, 0, 6, 0, 0, 0,
26, 0, 16, 128, 65, 0,
0, 0, 6, 0, 0, 0,
1, 64, 0, 0, 0, 0,
128, 63, 50, 0, 0, 15,
98, 0, 16, 0, 5, 0,
0, 0, 86, 132, 32, 6,
0, 0, 0, 0, 59, 0,
0, 0, 26, 0, 16, 0,
4, 0, 0, 0, 166, 8,
16, 0, 6, 0, 0, 0,
2, 64, 0, 0, 0, 0,
0, 0, 0, 0, 0, 63,
0, 0, 0, 63, 0, 0,
0, 0, 65, 0, 0, 5,
50, 0, 16, 0, 6, 0,
0, 0, 102, 10, 16, 0,
5, 0, 0, 0, 26, 0,
0, 5, 98, 0, 16, 0,
5, 0, 0, 0, 86, 6,
16, 0, 5, 0, 0, 0,
56, 0, 0, 10, 50, 0,
16, 0, 6, 0, 0, 0,
70, 0, 16, 0, 6, 0,
0, 0, 230, 138, 32, 6,
0, 0, 0, 0, 59, 0,
0, 0, 26, 0, 16, 0,
4, 0, 0, 0, 50, 0,
0, 12, 50, 0, 16, 0,
6, 0, 0, 0, 70, 0,
16, 0, 6, 0, 0, 0,
230, 10, 16, 0, 4, 0,
0, 0, 70, 128, 32, 6,
0, 0, 0, 0, 60, 0,
0, 0, 26, 0, 16, 0,
4, 0, 0, 0, 0, 0,
0, 11, 194, 0, 16, 0,
6, 0, 0, 0, 86, 9,
16, 128, 65, 0, 0, 0,
5, 0, 0, 0, 2, 64,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
128, 63, 0, 0, 128, 63,
54, 0, 0, 5, 130, 0,
16, 0, 5, 0, 0, 0,
1, 64, 0, 0, 0, 0,
0, 0, 54, 0, 0, 5,
18, 0, 16, 0, 7, 0,
0, 0, 1, 64, 0, 0,
253, 255, 255, 255, 48, 0,
0, 1, 34, 0, 0, 7,
34, 0, 16, 0, 7, 0,
0, 0, 1, 64, 0, 0,
3, 0, 0, 0, 10, 0,
16, 0, 7, 0, 0, 0,
3, 0, 4, 3, 26, 0,
16, 0, 7, 0, 0, 0,
43, 0, 0, 5, 162, 0,
16, 0, 2, 0, 0, 0,
6, 0, 16, 0, 7, 0,
0, 0, 56, 0, 0, 10,
242, 0, 16, 0, 8, 0,
0, 0, 70, 14, 16, 0,
2, 0, 0, 0, 230, 142,
32, 6, 0, 0, 0, 0,
59, 0, 0, 0, 26, 0,
16, 0, 4, 0, 0, 0,
50, 0, 0, 9, 242, 0,
16, 0, 8, 0, 0, 0,
70, 14, 16, 0, 8, 0,
0, 0, 230, 14, 16, 0,
4, 0, 0, 0, 70, 4,
16, 0, 6, 0, 0, 0,
126, 0, 0, 141, 194, 0,
0, 128, 67, 85, 21, 0,
242, 0, 16, 0, 9, 0,
0, 0, 70, 0, 16, 0,
8, 0, 0, 0, 70, 126,
16, 0, 2, 0, 0, 0,
10, 96, 16, 0, 2, 0,
0, 0, 10, 0, 16, 0,
5, 0, 0, 0, 32, 0,
0, 10, 162, 0, 16, 0,
2, 0, 0, 0, 6, 0,
16, 0, 7, 0, 0, 0,
2, 64, 0, 0, 0, 0,
0, 0, 253, 255, 255, 255,
0, 0, 0, 0, 3, 0,
0, 0, 55, 0, 0, 9,
130, 0, 16, 0, 10, 0,
0, 0, 26, 0, 16, 0,
2, 0, 0, 0, 42, 0,
16, 0, 6, 0, 0, 0,
1, 64, 0, 0, 0, 0,
128, 63, 55, 0, 0, 9,
18, 0, 16, 0, 10, 0,
0, 0, 58, 0, 16, 0,
2, 0, 0, 0, 26, 0,
16, 0, 5, 0, 0, 0,
1, 64, 0, 0, 0, 0,
128, 63, 56, 0, 0, 7,
98, 0, 16, 0, 10, 0,
0, 0, 246, 15, 16, 0,
6, 0, 0, 0, 6, 3,
16, 0, 10, 0, 0, 0,
17, 0, 0, 7, 34, 0,
16, 0, 2, 0, 0, 0,
22, 11, 16, 0, 10, 0,
0, 0, 70, 14, 16, 0,
9, 0, 0, 0, 0, 0,
0, 7, 34, 0, 16, 0,
2, 0, 0, 0, 26, 0,
16, 0, 2, 0, 0, 0,
58, 0, 16, 0, 5, 0,
0, 0, 126, 0, 0, 141,
194, 0, 0, 128, 67, 85,
21, 0, 242, 0, 16, 0,
8, 0, 0, 0, 230, 10,
16, 0, 8, 0, 0, 0,
70, 126, 16, 0, 2, 0,
0, 0, 10, 96, 16, 0,
2, 0, 0, 0, 10, 0,
16, 0, 5, 0, 0, 0,
17, 0, 0, 7, 130, 0,
16, 0, 2, 0, 0, 0,
6, 15, 16, 0, 10, 0,
0, 0, 70, 14, 16, 0,
8, 0, 0, 0, 0, 0,
0, 7, 34, 0, 16, 0,
2, 0, 0, 0, 58, 0,
16, 0, 2, 0, 0, 0,
26, 0, 16, 0, 2, 0,
0, 0, 43, 0, 0, 5,
162, 0, 16, 0, 3, 0,
0, 0, 6, 0, 16, 0,
7, 0, 0, 0, 56, 0,
0, 10, 242, 0, 16, 0,
8, 0, 0, 0, 70, 14,
16, 0, 3, 0, 0, 0,
230, 142, 32, 6, 0, 0,
0, 0, 59, 0, 0, 0,
26, 0, 16, 0, 4, 0,
0, 0, 50, 0, 0, 9,
242, 0, 16, 0, 8, 0,
0, 0, 70, 14, 16, 0,
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16, 0, 4, 0, 0, 0,
70, 4, 16, 0, 6, 0,
0, 0, 126, 0, 0, 141,
194, 0, 0, 128, 67, 85,
21, 0, 242, 0, 16, 0,
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16, 0, 8, 0, 0, 0,
70, 126, 16, 0, 2, 0,
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16, 0, 5, 0, 0, 0,
17, 0, 0, 7, 130, 0,
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6, 15, 16, 0, 10, 0,
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0, 7, 34, 0, 16, 0,
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26, 0, 16, 0, 2, 0,
0, 0, 126, 0, 0, 141,
194, 0, 0, 128, 67, 85,
21, 0, 242, 0, 16, 0,
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16, 0, 8, 0, 0, 0,
70, 126, 16, 0, 2, 0,
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16, 0, 5, 0, 0, 0,
56, 0, 0, 7, 98, 0,
16, 0, 10, 0, 0, 0,
166, 10, 16, 0, 5, 0,
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0, 7, 130, 0, 16, 0,
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16, 0, 10, 0, 0, 0,
70, 14, 16, 0, 8, 0,
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130, 0, 16, 0, 5, 0,
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30, 0, 0, 7, 18, 0,
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0, 1, 56, 0, 0, 7,
34, 0, 16, 0, 2, 0,
0, 0, 58, 0, 16, 0,
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0, 0, 5, 47, 167, 60,
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0, 5, 34, 0, 16, 0,
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0, 0, 0, 0, 128, 63,
21, 0, 0, 1, 51, 0,
0, 7, 18, 0, 16, 0,
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0, 0, 30, 0, 0, 7,
130, 0, 16, 0, 0, 0,
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0, 0, 1, 0, 0, 0,
22, 0, 0, 1, 54, 0,
0, 5, 242, 32, 16, 0,
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16, 0, 4, 0, 0, 0,
62, 0, 0, 1, 83, 84,
65, 84, 148, 0, 0, 0,
90, 0, 0, 0, 11, 0,
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0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 12, 0,
0, 0, 2, 0, 0, 0,
5, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0
};
| {
"language": "Assembly"
} |
.section .init
.global _init
_init:
push %rax
.section .fini
.global _fini
_fini:
push %rax
| {
"language": "Assembly"
} |
; RUN: opt < %s -scalar-evolution -analyze | FileCheck %s
; PR1597
; CHECK: Loop %bb: backedge-taken count is (-1 + (-1 * %x) + %y)
define i32 @f(i32 %x, i32 %y) {
entry:
%tmp63 = icmp ult i32 %x, %y ; <i1> [#uses=1]
br i1 %tmp63, label %bb.preheader, label %bb8
bb.preheader: ; preds = %entry
br label %bb
bb: ; preds = %bb3, %bb.preheader
%x_addr.0 = phi i32 [ %tmp2, %bb3 ], [ %x, %bb.preheader ] ; <i32> [#uses=1]
%tmp2 = add i32 %x_addr.0, 1 ; <i32> [#uses=3]
br label %bb3
bb3: ; preds = %bb
%tmp6 = icmp ult i32 %tmp2, %y ; <i1> [#uses=1]
br i1 %tmp6, label %bb, label %bb8.loopexit
bb8.loopexit: ; preds = %bb3
br label %bb8
bb8: ; preds = %bb8.loopexit, %entry
%x_addr.1 = phi i32 [ %x, %entry ], [ %tmp2, %bb8.loopexit ] ; <i32> [#uses=1]
br label %return
return: ; preds = %bb8
ret i32 %x_addr.1
}
| {
"language": "Assembly"
} |
//------------------------------------------------------------------------//
// this script is only for some version ,so you should be aware of this ; //
// //
// script by heiketian10 //
// //
// 2010.12.17 //
// //
// 增加了自动寻找解包入口的功能，脚本拼接了molbox的解包script，感谢原作者//
// //
// 测试在win7 xp sp2 跑9.7 和10.4的飓风都可以解包。希望大家多提意见 //
//-------------------------------------------------------------------------
VAR temp //定义这几个变量在后面可以用；
VAR tmp
VAR address
VAR end
VAR espstart
VAR if
BPHWCALL // clear hard breakpoint
MOV temp,eip
FIND temp,#39DD7301C35F# //找到关键的call
MOV address ,$RESULT
CMP address ,0
JNZ ok
jmp kkkk
MSG "CAN'T FIND THE STRINGS,PERHAPS,IT'S NOT THE PROPER VERSION."
RET
ok:
ADD address ,6 //在为关键call处下断点做准备
BP address //在关键call下f2断点
ERUN //shift + f9
STI //f7
BC address //qing chu duan dian !
RTR
STI
jmp kkkk
kkkk:
MOV tmp,eip
FIND tmp,#60E84F000000??????# //找到esp定律关键的部分
MOV end,$RESULT
BP end //运行到这个关键的地方
ERUN
BC end //清除断点
STI
MOV espstart,esp
BPHWS espstart,"r" //在esp处下读内存断点
panduan:
ERUN
MOV if,[eip]
CMP if,D0FF5858
jnz panduan
BPHWC espstart //清除这个断点
MSG "点击确定继续运行提取Molbox 封装的内容，请记住，点击确定!"
jmp molbox
// Molebox 2.x Unpacker / OEP Finder Script v1.10 // 这个是拼接的molbox的那个提取脚本，感谢作者：
// by Cherry
//
// Needed tools: OllyDbg with ODbgScript-Plugin
//
// This script will unpack all files in a Molebox 2.x packed file which are visible to the packed program into the subfolder "!UNPACKED!".
// Unfortunately, in many cases the main executable is not included.
//
// 1. Copy "mbunpack.dll" and "filelen.exe" into the executable's folder.
// 2. Open the moleboxed executable in Olly.
// 3. Make sure EIP is at the entry point of Molebox stub, no breakpoints are set and all exceptions are ignored!!!
// 4. Run this script.
// 5. OEP address will be displayed and you will be asked if you want to unpack it or start exploring the file at OEP.
// 6. If you start unpacking, you can follow the progress in the console window which will open. Be patient.
//
// Known bug: All folders in the root directory will be recreated in the "!UNPACKED!" subfolder, ignoring whether it existed in the archive or not.
//
// Have fun!
// Greetings, Cherry
molbox:
var temp
mov temp, eip
sub temp, 440
find temp, #615858FFD0#
cmp $RESULT, 0
jne okaya
sub temp, 0BC0
find temp, #615858FFD0#
cmp $RESULT, 0
jne okaya
sub temp, 1000
find temp, #615858FFD0#
cmp $RESULT, 0
jne okaya
sub temp, 1000
find temp, #615858FFD0#
cmp $RESULT, 0
je failed
okaya:
mov temp, $RESULT
add temp, 3
bphws temp, "x"
run
bphwc temp
sti
itoa eip
msgyn "OEP is at VA " + $RESULT + "! Unpack?"
cmp $RESULT, 0
jne unpack
an 400000
ret
unpack:
var mname
mov mname, eip
mov temp, eip
mov [temp], "mbunpack.dll"
add temp, 0C
mov [temp], #00#
inc temp
var fname
mov fname, temp
mov [temp], "MBUNPACK_ALL@0"
add temp, 0E
mov [temp], #00#
inc temp
var uep
mov uep, temp
mov [temp], #68#
inc temp
mov [temp], mname
add temp, 4
asm temp, "call eax"
add temp, 2
asm temp, "call ebx"
add temp, 2
asm temp, "ret"
mov edx, mname
mov ebx, fname
exec
push edx
call LoadLibraryA
mov edx, eax
push ebx
push edx
call GetProcAddress
mov ebx, eax
push edx
call FreeLibrary
ende
cmp ebx, 100000
jb nolib
mov eip, uep
findmem #558BEC6A00FF7508E8????????59595DC20400#
mov eax, $RESULT
cmp eax, 0
jne okayb
findmem #558BEC8B45086A0050E8????????83C4085DC20400#
mov eax, $RESULT
cmp eax, 0
je failed
okayb:
mov temp, uep
add temp, 9
bphws temp, "x"
run
bphwc temp
ret
failed:
msg "Cannot unpack this file. Make sure EIP is at the EP of Molebox stub, no breakpoints are set and all exceptions are ignored! If everything is fine: Maybe the file is not packed with Molebox 2.x or it's packed with another packer too?"
ret
nolib:
msg "Loading mbunpack.dll failed! Make sure it's in the executable's directory, as well as filelen.exe!"
ret | {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for AMD64, Darwin
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
/* Copyright (C) 2002-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Ulrich Drepper <[email protected]>, 2002.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
#include <stdlib.h>
#include "pthreadP.h"
void
__pthread_exit (void *value)
{
THREAD_SETMEM (THREAD_SELF, result, value);
__do_cancel ();
}
weak_alias (__pthread_exit, pthread_exit)
/* After a thread terminates, __libc_start_main decrements
__nptl_nthreads defined in pthread_create.c. */
PTHREAD_STATIC_FN_REQUIRE (__pthread_create)
| {
"language": "Assembly"
} |
/* fuc microcode util functions for gf100 PGRAPH
*
* Copyright 2011 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifdef INCLUDE_CODE
// queue_put - add request to queue
//
// In : $r13 queue pointer
// $r14 command
// $r15 data
//
queue_put:
// make sure we have space..
ld b32 $r8 D[$r13 + 0x0] // GET
ld b32 $r9 D[$r13 + 0x4] // PUT
xor $r8 8
cmpu b32 $r8 $r9
bra ne #queue_put_next
mov $r15 E_CMD_OVERFLOW
call(error)
ret
// store cmd/data on queue
queue_put_next:
and $r8 $r9 7
shl b32 $r8 3
add b32 $r8 $r13
add b32 $r8 8
st b32 D[$r8 + 0x0] $r14
st b32 D[$r8 + 0x4] $r15
// update PUT
add b32 $r9 1
and $r9 0xf
st b32 D[$r13 + 0x4] $r9
ret
// queue_get - fetch request from queue
//
// In : $r13 queue pointer
//
// Out: $p1 clear on success (data available)
// $r14 command
// $r15 data
//
queue_get:
bset $flags $p1
ld b32 $r8 D[$r13 + 0x0] // GET
ld b32 $r9 D[$r13 + 0x4] // PUT
cmpu b32 $r8 $r9
bra e #queue_get_done
// fetch first cmd/data pair
and $r9 $r8 7
shl b32 $r9 3
add b32 $r9 $r13
add b32 $r9 8
ld b32 $r14 D[$r9 + 0x0]
ld b32 $r15 D[$r9 + 0x4]
// update GET
add b32 $r8 1
and $r8 0xf
st b32 D[$r13 + 0x0] $r8
bclr $flags $p1
queue_get_done:
ret
// nv_rd32 - read 32-bit value from nv register
//
// In : $r14 register
// Out: $r15 value
//
nv_rd32:
mov b32 $r12 $r14
bset $r12 31 // MMIO_CTRL_PENDING
nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
nv_rd32_wait:
nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
xbit $r12 $r12 31
bra ne #nv_rd32_wait
mov $r10 6 // DONE_MMIO_RD
call(wait_doneo)
nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0)
ret
// nv_wr32 - write 32-bit value to nv register
//
// In : $r14 register
// $r15 value
//
nv_wr32:
nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15)
mov b32 $r12 $r14
bset $r12 31 // MMIO_CTRL_PENDING
bset $r12 30 // MMIO_CTRL_WRITE
nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12)
nv_wr32_wait:
nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0)
xbit $r12 $r12 31
bra ne #nv_wr32_wait
ret
// wait_donez - wait on FUC_DONE bit to become clear
//
// In : $r10 bit to wait on
//
wait_donez:
trace_set(T_WAIT);
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
wait_donez_ne:
nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
xbit $r8 $r8 $r10
bra ne #wait_donez_ne
trace_clr(T_WAIT)
ret
// wait_doneo - wait on FUC_DONE bit to become set
//
// In : $r10 bit to wait on
//
wait_doneo:
trace_set(T_WAIT);
nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
wait_doneo_e:
nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
xbit $r8 $r8 $r10
bra e #wait_doneo_e
trace_clr(T_WAIT)
ret
// mmctx_size - determine size of a mmio list transfer
//
// In : $r14 mmio list head
// $r15 mmio list tail
// Out: $r15 transfer size (in bytes)
//
mmctx_size:
clear b32 $r9
nv_mmctx_size_loop:
ld b32 $r8 D[$r14]
shr b32 $r8 26
add b32 $r8 1
shl b32 $r8 2
add b32 $r9 $r8
add b32 $r14 4
cmpu b32 $r14 $r15
bra ne #nv_mmctx_size_loop
mov b32 $r15 $r9
ret
// mmctx_xfer - execute a list of mmio transfers
//
// In : $r10 flags
// bit 0: direction (0 = save, 1 = load)
// bit 1: set if first transfer
// bit 2: set if last transfer
// $r11 base
// $r12 mmio list head
// $r13 mmio list tail
// $r14 multi_stride
// $r15 multi_mask
//
mmctx_xfer:
trace_set(T_MMCTX)
clear b32 $r9
or $r11 $r11
bra e #mmctx_base_disabled
nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11)
bset $r9 0 // BASE_EN
mmctx_base_disabled:
or $r14 $r14
bra e #mmctx_multi_disabled
nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14)
nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15)
bset $r9 1 // MULTI_EN
mmctx_multi_disabled:
xbit $r11 $r10 0
shl b32 $r11 16 // DIR
bset $r11 12 // QLIMIT = 0x10
xbit $r14 $r10 1
shl b32 $r14 17
or $r11 $r14 // START_TRIGGER
nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
// loop over the mmio list, and send requests to the hw
mmctx_exec_loop:
// wait for space in mmctx queue
mmctx_wait_free:
nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
and $r14 0x1f
bra e #mmctx_wait_free
// queue up an entry
ld b32 $r14 D[$r12]
or $r14 $r9
nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14)
add b32 $r12 4
cmpu b32 $r12 $r13
bra ne #mmctx_exec_loop
xbit $r11 $r10 2
bra ne #mmctx_stop
// wait for queue to empty
mmctx_fini_wait:
nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
and $r11 0x1f
cmpu b32 $r11 0x10
bra ne #mmctx_fini_wait
mov $r10 5 // DONE_MMCTX
call(wait_donez)
bra #mmctx_done
mmctx_stop:
xbit $r11 $r10 0
shl b32 $r11 16 // DIR
bset $r11 12 // QLIMIT = 0x10
bset $r11 18 // STOP_TRIGGER
nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11)
mmctx_stop_wait:
// wait for STOP_TRIGGER to clear
nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0)
xbit $r11 $r11 18
bra ne #mmctx_stop_wait
mmctx_done:
trace_clr(T_MMCTX)
ret
// Wait for DONE_STRAND
//
strand_wait:
push $r10
mov $r10 2
call(wait_donez)
pop $r10
ret
// unknown - call before issuing strand commands
//
strand_pre:
mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
call(strand_wait)
ret
// unknown - call after issuing strand commands
//
strand_post:
mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9)
call(strand_wait)
ret
// Selects strand set?!
//
// In: $r14 id
//
strand_set:
mov $r12 0xf
nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call(strand_wait)
ret
// Initialise strand context data
//
// In : $r15 context base
// Out: $r15 context size (in bytes)
//
// Strandset(?) 3 hardcoded currently
//
strand_ctx_init:
trace_set(T_STRINIT)
call(strand_pre)
mov $r14 3
call(strand_set)
clear b32 $r12
nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call(strand_wait)
sub b32 $r12 $r0 1
nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12)
mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO
nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12)
call(strand_wait)
call(strand_post)
// read the size of each strand, poke the context offset of
// each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
// about it later then.
nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00)
nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00)
shr b32 $r14 $r15 8
ctx_init_strand_loop:
iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE
iowr I[$r8 + 0x100] $r14 // STRAND_LOAD_SWBASE
iord $r10 I[$r8 + 0x200] // STRAND_SIZE
shr b32 $r10 6
add b32 $r10 1
add b32 $r14 $r10
add b32 $r8 4
sub b32 $r9 1
bra ne #ctx_init_strand_loop
shl b32 $r14 8
sub b32 $r15 $r14 $r15
trace_clr(T_STRINIT)
ret
#endif
| {
"language": "Assembly"
} |
/*
synth_neon_accurate: ARM NEON optimized synth (MPEG compliant 16-bit output version)
copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define WINDOW r0
#define B0 r1
#define SAMPLES r2
/*
int synth_1to1_real_neon_accurate_asm(real *window, real *b0, real *samples, int bo1);
return value: number of clipped samples (0)
*/
.text
.globl ASM_NAME(synth_1to1_neon_accurate_asm)
ASM_NAME(synth_1to1_neon_accurate_asm):
push {r4-r6, lr}
vpush {q4-q7}
mov r6, sp
sub sp, sp, #16
bic sp, #0xff
add WINDOW, WINDOW, #64
sub WINDOW, WINDOW, r3, lsl #2
mov r3, #4
mov r4, #128
mov r5, #64
.Loop_start_1:
vld1.32 {q0,q1}, [WINDOW], r4
vld1.32 {q2,q3}, [WINDOW], r4
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW]
sub WINDOW, WINDOW, #352
vld1.32 {q8,q9}, [B0, :128], r5
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128]
vswp q1, q4
vswp q3, q6
sub B0, B0, #160
vmul.f32 q0, q0, q8
vmul.f32 q2, q2, q10
vmul.f32 q1, q1, q12
vmul.f32 q3, q3, q14
vmla.f32 q0, q4, q9
vmla.f32 q2, q6, q11
vmla.f32 q1, q5, q13
vmla.f32 q3, q7, q15
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW], r4
vld1.32 {q8,q9}, [WINDOW], r4
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128], r5
vswp q5, q6
vswp q11, q12
vmla.f32 q0, q4, q10
vmla.f32 q2, q5, q11
vmla.f32 q1, q8, q14
vld1.32 {q4,q5}, [WINDOW]
vld1.32 {q10,q11}, [B0, :128]!
add WINDOW, WINDOW, #96
vmla.f32 q3, q4, q10
vmla.f32 q0, q6, q12
vmla.f32 q2, q7, q13
vmla.f32 q1, q9, q15
vmla.f32 q3, q5, q11
vmov.i32 q4, #0x4b000000
vmvn.i32 q5, #0xb9000000
vorr.i32 q4, #0x00400000
vpadd.f32 d0, d0, d1
vpadd.f32 d4, d4, d5
vpadd.f32 d2, d2, d3
vpadd.f32 d6, d6, d7
vld1.32 {q6}, [sp, :128]
vpadd.f32 d0, d0, d4
vpadd.f32 d1, d2, d6
vadd.f32 q3, q0, q4
vacgt.f32 q5, q0, q5
vld2.16 {d4,d5}, [SAMPLES]
vshl.i32 q3, q3, #10
vqshrn.s32 d3, q3, #10
vshr.u32 q5, q5, #31
vst2.16 {d3,d5}, [SAMPLES]!
vadd.i32 q5, q5, q6
vst1.32 {q5}, [sp, :128]
subs r3, r3, #1
bne .Loop_start_1
mov r3, #4
mov r5, #-64
.Loop_start_2:
vld1.32 {q0,q1}, [WINDOW], r4
vld1.32 {q2,q3}, [WINDOW], r4
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW]
sub WINDOW, WINDOW, #352
vld1.32 {q8,q9}, [B0, :128], r5
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128]
vswp q1, q4
vswp q3, q6
add B0, B0, #224
vmul.f32 q0, q0, q8
vmul.f32 q2, q2, q10
vmul.f32 q1, q1, q12
vmul.f32 q3, q3, q14
vmla.f32 q0, q4, q9
vmla.f32 q2, q6, q11
vmla.f32 q1, q5, q13
vmla.f32 q3, q7, q15
vld1.32 {q4,q5}, [WINDOW], r4
vld1.32 {q6,q7}, [WINDOW], r4
vld1.32 {q8,q9}, [WINDOW], r4
vld1.32 {q10,q11}, [B0, :128], r5
vld1.32 {q12,q13}, [B0, :128], r5
vld1.32 {q14,q15}, [B0, :128], r5
vswp q5, q6
vswp q11, q12
vmla.f32 q0, q4, q10
vmla.f32 q2, q5, q11
vmla.f32 q1, q8, q14
vld1.32 {q4,q5}, [WINDOW]
vld1.32 {q10,q11}, [B0, :128]
add WINDOW, WINDOW, #96
sub B0, B0, #96
vmla.f32 q3, q4, q10
vmla.f32 q0, q6, q12
vmla.f32 q2, q7, q13
vmla.f32 q1, q9, q15
vmla.f32 q3, q5, q11
vmov.i32 q4, #0x4b000000
vmvn.i32 q5, #0xb9000000
vorr.i32 q4, #0x00400000
vpadd.f32 d0, d0, d1
vpadd.f32 d4, d4, d5
vpadd.f32 d2, d2, d3
vpadd.f32 d6, d6, d7
vld1.32 {q6}, [sp, :128]
vpadd.f32 d0, d0, d4
vpadd.f32 d1, d2, d6
vadd.f32 q3, q0, q4
vacgt.f32 q5, q0, q5
vld2.16 {d4,d5}, [SAMPLES]
vshl.i32 q3, q3, #10
vqshrn.s32 d3, q3, #10
vshr.u32 q5, q5, #31
vst2.16 {d3,d5}, [SAMPLES]!
vadd.i32 q5, q5, q6
vst1.32 {q5}, [sp, :128]
subs r3, r3, #1
bne .Loop_start_2
vld1.32 {q0}, [sp, :128]
vpadd.i32 d0, d0, d1
vpadd.i32 d0, d0, d0
vmov.32 r0, d0[0]
mov sp, r6
vpop {q4-q7}
pop {r4-r6, pc}
| {
"language": "Assembly"
} |
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshl z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqshl z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x08,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 08 44 <unknown>
sqshl z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqshl z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x48,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 48 44 <unknown>
sqshl z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqshl z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 88 44 <unknown>
sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c8 44 <unknown>
sqshl z0.b, p0/m, z0.b, #0
// CHECK-INST: sqshl z0.b, p0/m, z0.b, #0
// CHECK-ENCODING: [0x00,0x81,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 81 06 04 <unknown>
sqshl z31.b, p0/m, z31.b, #7
// CHECK-INST: sqshl z31.b, p0/m, z31.b, #7
// CHECK-ENCODING: [0xff,0x81,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 81 06 04 <unknown>
sqshl z0.h, p0/m, z0.h, #0
// CHECK-INST: sqshl z0.h, p0/m, z0.h, #0
// CHECK-ENCODING: [0x00,0x82,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 82 06 04 <unknown>
sqshl z31.h, p0/m, z31.h, #15
// CHECK-INST: sqshl z31.h, p0/m, z31.h, #15
// CHECK-ENCODING: [0xff,0x83,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 06 04 <unknown>
sqshl z0.s, p0/m, z0.s, #0
// CHECK-INST: sqshl z0.s, p0/m, z0.s, #0
// CHECK-ENCODING: [0x00,0x80,0x46,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 46 04 <unknown>
sqshl z31.s, p0/m, z31.s, #31
// CHECK-INST: sqshl z31.s, p0/m, z31.s, #31
// CHECK-ENCODING: [0xff,0x83,0x46,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 46 04 <unknown>
sqshl z0.d, p0/m, z0.d, #0
// CHECK-INST: sqshl z0.d, p0/m, z0.d, #0
// CHECK-ENCODING: [0x00,0x80,0x86,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 86 04 <unknown>
sqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqshl z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqshl z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 c8 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c8 44 <unknown>
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
| {
"language": "Assembly"
} |
;-------------------------------------------------------------------------------
; sys_core.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
.ref _c_int00
.def _reset
.asmfunc
_reset
;-------------------------------------------------------------------------------
; Initialize CPU Registers
; After reset, the CPU is in the Supervisor mode (M = 10011)
mov r0, lr
mov r1, #0x0000
mov r2, #0x0000
mov r3, #0x0000
mov r4, #0x0000
mov r5, #0x0000
mov r6, #0x0000
mov r7, #0x0000
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
mov r13, #0x0000
mrs r1, cpsr
msr spsr_cxsf, r1
; Switch to FIQ mode (M = 10001)
cps #17
mov lr, r0
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
mrs r1, cpsr
msr spsr_cxsf, r1
; Switch to IRQ mode (M = 10010)
cps #18
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
; Switch to Abort mode (M = 10111)
cps #23
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
; Switch to Undefined Instruction Mode (M = 11011)
cps #27
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
; Switch to System Mode ( Shares User Mode registers ) (M = 11111)
cps #31
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
; Switch back to Supervisor Mode (M = 10011)
cps #19
; Turn on FPV coprocessor
mrc p15, #0x00, r2, c1, c0, #0x02
orr r2, r2, #0xF00000
mcr p15, #0x00, r2, c1, c0, #0x02
.if (RT_VFP_LAZY_STACKING) = 0
fmrx r2, fpexc
orr r2, r2, #0x40000000
fmxr fpexc, r2
fmdrr d0, r1, r1
fmdrr d1, r1, r1
fmdrr d2, r1, r1
fmdrr d3, r1, r1
fmdrr d4, r1, r1
fmdrr d5, r1, r1
fmdrr d6, r1, r1
fmdrr d7, r1, r1
fmdrr d8, r1, r1
fmdrr d9, r1, r1
fmdrr d10, r1, r1
fmdrr d11, r1, r1
fmdrr d12, r1, r1
fmdrr d13, r1, r1
fmdrr d14, r1, r1
fmdrr d15, r1, r1
.endif
;-------------------------------------------------------------------------------
; Initialize Stack Pointers
cps #17
ldr sp, fiqSp
cps #18
ldr sp, irqSp
cps #23
ldr sp, abortSp
cps #27
ldr sp, undefSp
cps #31
ldr sp, userSp
cps #19
ldr sp, svcSp
bl next1
next1
bl next2
next2
bl next3
next3
bl next4
next4
ldr lr, int00ad
bx lr
int00ad .word _c_int00
userSp .word 0x08000000+0x00001000
svcSp .word 0x08000000+0x00001000+0x00000100
fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100
irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
.endasmfunc
;-------------------------------------------------------------------------------
; Enable RAM ECC Support
.def _coreEnableRamEcc_
.asmfunc
_coreEnableRamEcc_
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x0C000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable RAM ECC Support
.def _coreDisableRamEcc_
.asmfunc
_coreDisableRamEcc_
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
bic r0, r0, #0x0C000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Flash ECC Support
.def _coreEnableFlashEcc_
.asmfunc
_coreEnableFlashEcc_
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x02000000
dmb
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Flash ECC Support
.def _coreDisableFlashEcc_
.asmfunc
_coreDisableFlashEcc_
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
bic r0, r0, #0x02000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get data fault status register
.def _coreGetDataFault_
.asmfunc
_coreGetDataFault_
mrc p15, #0, r0, c5, c0, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear data fault status register
.def _coreClearDataFault_
.asmfunc
_coreClearDataFault_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c0, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get instruction fault status register
.def _coreGetInstructionFault_
.asmfunc
_coreGetInstructionFault_
mrc p15, #0, r0, c5, c0, #1
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear instruction fault status register
.def _coreClearInstructionFault_
.asmfunc
_coreClearInstructionFault_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c0, #1
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get data fault address register
.def _coreGetDataFaultAddress_
.asmfunc
_coreGetDataFaultAddress_
mrc p15, #0, r0, c6, c0, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear data fault address register
.def _coreClearDataFaultAddress_
.asmfunc
_coreClearDataFaultAddress_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c6, c0, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get instruction fault address register
.def _coreGetInstructionFaultAddress_
.asmfunc
_coreGetInstructionFaultAddress_
mrc p15, #0, r0, c6, c0, #2
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear instruction fault address register
.def _coreClearInstructionFaultAddress_
.asmfunc
_coreClearInstructionFaultAddress_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c6, c0, #2
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get auxiliary data fault status register
.def _coreGetAuxiliaryDataFault_
.asmfunc
_coreGetAuxiliaryDataFault_
mrc p15, #0, r0, c5, c1, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear auxiliary data fault status register
.def _coreClearAuxiliaryDataFault_
.asmfunc
_coreClearAuxiliaryDataFault_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c1, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get auxiliary instruction fault status register
.def _coreGetAuxiliaryInstructionFault_
.asmfunc
_coreGetAuxiliaryInstructionFault_
mrc p15, #0, r0, c5, c1, #1
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear auxiliary instruction fault status register
.def _coreClearAuxiliaryInstructionFault_
.asmfunc
_coreClearAuxiliaryInstructionFault_
stmfd sp!, {r0}
mov r0, #0
mrc p15, #0, r0, c5, c1, #1
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear ESM CCM errorss
.def _esmCcmErrorsClear_
.asmfunc
_esmCcmErrorsClear_
stmfd sp!, {r0-r2}
ldr r0, ESMSR1_REG ; load the ESMSR1 status register address
ldr r2, ESMSR1_ERR_CLR
str r2, [r0] ; clear the ESMSR1 register
ldr r0, ESMSR2_REG ; load the ESMSR2 status register address
ldr r2, ESMSR2_ERR_CLR
str r2, [r0] ; clear the ESMSR2 register
ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address
ldr r2, ESMSSR2_ERR_CLR
str r2, [r0] ; clear the ESMSSR2 register
ldr r0, ESMKEY_REG ; load the ESMKEY register address
mov r2, #0x5 ; load R2 with 0x5
str r2, [r0] ; clear the ESMKEY register
ldr r0, VIM_INTREQ ; load the INTREQ register address
ldr r2, VIM_INT_CLR
str r2, [r0] ; clear the INTREQ register
ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address
ldr r2, CCMR4_ERR_CLR
str r2, [r0] ; clear the CCMR4 status register
ldmfd sp!, {r0-r2}
bx lr
ESMSR1_REG .word 0xFFFFF518
ESMSR2_REG .word 0xFFFFF51C
ESMSR3_REG .word 0xFFFFF520
ESMKEY_REG .word 0xFFFFF538
ESMSSR2_REG .word 0xFFFFF53C
CCMR4_STAT_REG .word 0xFFFFF600
ERR_CLR_WRD .word 0xFFFFFFFF
CCMR4_ERR_CLR .word 0x00010000
ESMSR1_ERR_CLR .word 0x80000000
ESMSR2_ERR_CLR .word 0x00000004
ESMSSR2_ERR_CLR .word 0x00000004
VIM_INT_CLR .word 0x00000001
VIM_INTREQ .word 0xFFFFFE20
.endasmfunc
;-------------------------------------------------------------------------------
; Work Around for Errata CORTEX-R4#57:
;
; Errata Description:
; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
; Workaround:
; Disable out-of-order single-precision floating point
; multiply-accumulate instruction completion
.def _errata_CORTEXR4_57_
.asmfunc
_errata_CORTEXR4_57_
push {r0}
mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
pop {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Work Around for Errata CORTEX-R4#66:
;
; Errata Description:
; Register Corruption During A Load-Multiple Instruction At
; an Exception Vector
; Workaround:
; Disable out-of-order completion for divide instructions in
; Auxiliary Control register
.def _errata_CORTEXR4_66_
.asmfunc
_errata_CORTEXR4_66_
push {r0}
mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register
orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
; for divide instructions.)
mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register
pop {r0}
bx lr
.endasmfunc
.def turnon_VFP
.asmfunc
turnon_VFP
; Enable FPV
STMDB sp!, {r0}
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
LDMIA sp!, {r0}
subs pc, lr, #4
.endasmfunc
_push_svc_reg .macro
sub sp, sp, #17 * 4 ;/* Sizeof(struct rt_hw_exp_stack) */
stmia sp, {r0 - r12} ;/* Calling r0-r12 */
mov r0, sp
mrs r6, spsr ;/* Save CPSR */
str lr, [r0, #15*4] ;/* Push PC */
str r6, [r0, #16*4] ;/* Push CPSR */
cps #0x13
str sp, [r0, #13*4] ;/* Save calling SP */
str lr, [r0, #14*4] ;/* Save calling PC */
.endm
.ref rt_hw_trap_svc
.def vector_svc
.asmfunc
vector_svc:
_push_svc_reg
bl rt_hw_trap_svc
sub pc, pc, #-4
.endasmfunc
.ref rt_hw_trap_pabt
.def vector_pabort
.asmfunc
vector_pabort:
_push_svc_reg
bl rt_hw_trap_pabt
sub pc, pc, #-4
.endasmfunc
.ref rt_hw_trap_dabt
.def vector_dabort
.asmfunc
vector_dabort:
_push_svc_reg
bl rt_hw_trap_dabt
sub pc, pc, #-4
.endasmfunc
.ref rt_hw_trap_resv
.def vector_resv
.asmfunc
vector_resv:
_push_svc_reg
bl rt_hw_trap_resv
sub pc, pc, #-4
.endasmfunc
;-------------------------------------------------------------------------------
; C++ construct table pointers
.def __TI_PINIT_Base, __TI_PINIT_Limit
.weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit
__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base
__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
;-------------------------------------------------------------------------------
| {
"language": "Assembly"
} |
// Test host codegen.
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
// Test target codegen - host bc file has to be created first.
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// SIMD-ONLY1-NOT: {{__kmpc|__tgt}}
// expected-no-diagnostics
#ifndef HEADER
#define HEADER
// CHECK-DAG: [[TT:%.+]] = type { i64, i8 }
// CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 }
// TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}}, i32, i32 }
// CHECK-DAG: [[SIZET:@.+]] = private unnamed_addr constant [2 x i64] [i64 0, i64 4]
// CHECK-DAG: [[MAPT:@.+]] = private unnamed_addr constant [2 x i64] [i64 544, i64 800]
// CHECK-DAG: @{{.*}} = weak constant i8 0
// TCHECK: @{{.+}} = weak constant [[ENTTY]]
// TCHECK: @{{.+}} = {{.*}}constant [[ENTTY]]
// TCHECK-NOT: @{{.+}} = weak constant [[ENTTY]]
// Check target registration is registered as a Ctor.
// CHECK: appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* @.omp_offloading.requires_reg, i8* null }]
template<typename tx, typename ty>
struct TT{
tx X;
ty Y;
};
int global;
extern int global;
// CHECK: define {{.*}}[[FOO:@.+]](
int foo(int n) {
int a = 0;
short aa = 0;
float b[10];
float bn[n];
double c[5][10];
double cn[5][n];
TT<long long, char> d;
static long *plocal;
// CHECK: [[ADD:%.+]] = add nsw i32
// CHECK: store i32 [[ADD]], i32* [[DEVICE_CAP:%.+]],
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* [[ID:@.+]], i32 [[GTID:%.+]], i32 1, i[[SZ]] {{20|40}}, i[[SZ]] 4, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY0:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY0:%.+]]*
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 3
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call void @__kmpc_omp_wait_deps(%struct.ident_t* [[ID]], i32 [[GTID]], i32 4, i8* [[DEP]], i32 0, i8* null)
// CHECK: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* [[ID]], i32 [[GTID]], i8* [[TASK]])
// CHECK: call i32 [[TASK_ENTRY0]](i32 [[GTID]], [[TASK_TY0]]* [[BC_TASK]])
// CHECK: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* [[ID]], i32 [[GTID]], i8* [[TASK]])
#pragma omp target teams distribute device(global + a) depend(in: global) depend(out: a, b, cn[4])
for (int i = 0; i < 10; ++i) {
}
// CHECK: [[ADD:%.+]] = add nsw i32
// CHECK: store i32 [[ADD]], i32* [[DEVICE_CAP:%.+]],
// CHECK: [[BOOL:%.+]] = icmp ne i32 %{{.+}}, 0
// CHECK: br i1 [[BOOL]], label %[[THEN:.+]], label %[[ELSE:.+]]
// CHECK: [[THEN]]:
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%.+]], i32 0, i32 0
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%.+]], i32 0, i32 0
// CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]**
// CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]**
// CHECK-DAG: store i[[SZ]]* [[BP0:%[^,]+]], i[[SZ]]** [[CBPADDR0]]
// CHECK-DAG: store i[[SZ]]* [[BP0]], i[[SZ]]** [[CPADDR0]]
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1
// CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]*
// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]*
// CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]]
// CHECK-DAG: store i[[SZ]] [[BP1]], i[[SZ]]* [[CPADDR1]]
// CHECK-DAG: getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0
// CHECK-DAG: getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[DEV1:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEV2:%.+]] = sext i32 [[DEV1]] to i64
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* [[ID]], i32 [[GTID]], i32 1, i[[SZ]] {{104|60}}, i[[SZ]] {{16|12}}, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY1_:@.+]] to i32 (i32, i8*)*), i64 [[DEV2]])
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY1_:%.+]]*
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* [[ID]], i32 [[GTID]], i8* [[TASK]], i32 3, i8* [[DEP]], i32 0, i8* null)
// CHECK: br label %[[EXIT:.+]]
// CHECK: [[ELSE]]:
// CHECK-NOT: getelementptr inbounds [2 x i8*], [2 x i8*]*
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[DEV1:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEV2:%.+]] = sext i32 [[DEV1]] to i64
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* [[ID]], i32 [[GTID]], i32 1, i[[SZ]] {{56|28}}, i[[SZ]] {{16|12}}, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY1__:@.+]] to i32 (i32, i8*)*), i64 [[DEV2]])
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY1__:%.+]]*
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* [[ID]], i32 [[GTID]], i8* [[TASK]], i32 3, i8* [[DEP]], i32 0, i8* null)
// CHECK: br label %[[EXIT:.+]]
// CHECK: [[EXIT]]:
#pragma omp target teams distribute device(global + a) nowait depend(inout: global, a, bn) if(a)
for (int i = 0; i < *plocal; ++i) {
static int local1;
*plocal = global;
local1 = global;
}
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* [[ID]], i32 [[GTID]], i32 1, i[[SZ]] {{48|24}}, i[[SZ]] 4, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY2:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY2:%.+]]*
// CHECK: getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call void @__kmpc_omp_wait_deps(%struct.ident_t* [[ID]], i32 [[GTID]], i32 1, i8* [[DEP]], i32 0, i8* null)
// CHECK: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* [[ID]], i32 [[GTID]], i8* [[TASK]])
// CHECK: call i32 [[TASK_ENTRY2]](i32 [[GTID]], [[TASK_TY2]]* [[BC_TASK]])
// CHECK: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* [[ID]], i32 [[GTID]], i8* [[TASK]])
#pragma omp target teams distribute if(0) firstprivate(global) depend(out:global)
for (int i = 0; i < global; ++i) {
global += 1;
}
return a;
}
// Check that the offloading functions are emitted and that the arguments are
// correct and loaded correctly for the target regions in foo().
// CHECK: define internal void [[HVT0:@.+]]()
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1)
// CHECK: store void (i8*, ...)* null, void (i8*, ...)** %
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEVICE:%.+]] = sext i32 [[DEV]] to i64
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams(i64 [[DEVICE]], i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i64* null, i64* null, i32 0, i32 0)
// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT0]]()
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
// CHECK: ret i32 0
// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}})
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1)
// CHECK: call void (i8*, ...) %
// CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEVICE:%.+]] = sext i32 [[DEV]] to i64
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams_nowait(i64 [[DEVICE]], i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i64* [[SZT]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* [[MAPT]], i32 0, i32 0), i32 0, i32 0)
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: [[BP0:%.+]] = load i[[SZ]]*, i[[SZ]]** %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]])
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
// CHECK: ret i32 0
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1)
// CHECK: call void (i8*, ...) %
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[BP0:%.+]] = load i[[SZ]]*, i[[SZ]]** %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]])
// CHECK: ret i32 0
// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}})
// Create stack storage and store argument in there.
// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align
// CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align
// CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32*
// CHECK-64: load i32, i32* [[AA_CADDR]], align
// CHECK-32: load i32, i32* [[AA_ADDR]], align
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1)
// CHECK: call void (i8*, ...) %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT2]](i[[SZ]] [[BP1]])
// CHECK: ret i32 0
#endif
| {
"language": "Assembly"
} |
MoveHorizon = 50
TimeMng_Init:
virtual at 0
.ply rd 1
.lend rb 0
end virtual
.localsize = ((.lend+15) and (-16))
stp x21, x30, [sp, -16]!
stp x26, x27, [sp, -16]!
stp x22, x23, [sp, -16]!
stp x24, x25, [sp, -16]!
sub sp, sp, TimeMng_Init.localsize
mov w26, w1
str w2, [sp, TimeMng_Init.ply]
_lea x6, limits
ldr x0, [x6, Limits.startTime]
_lea x6, time
str x0, [x6, Time.startTime]
_lea x6, limits + Limits.time
ldr w0, [x6, x26, lsl 2]
_lea x6, options
ldr w1, [x6, Options.minThinkTime]
cmp w0, w1
csel w0, w1, w0, lo
mov w22, w0
mov w23, w0
_lea x6, limits
ldr w0, [x6, Limits.movestogo]
mov w1, MoveHorizon
tst w0, w0
csel w0, w1, w0, eq
cmp w0, w1
csel w0, w1, w0, hi
mov w24, w0
mov w27, 0
TimeMng_Init.loop:
add w27, w27, 1
cmp w27, w24
bhi TimeMng_Init.loopdone
mov w0, 40
cmp w0, w27
csel w0, w27, w0, hi
add w0, w0, 2
_lea x6, options
ldr w2, [x6, Options.moveOverhead]
mul x0, x0, x2
_lea x6, limits + Limits.time
ldr w1, [x6, x26, lsl 2]
sub x1, x1, x0
_lea x6, limits + Limits.incr
ldr w0, [x6, x26, lsl 2]
sub w2, w27, 1
mul x0, x0, x2
adds x1, x1, x0
csel x1, xzr, x1, mi
mov x21, x1
mov w2, w27
ldr w8, [sp, TimeMng_Init.ply]
fmov d4, 1.0
fmov d5, xzr
bl TimeMng_Init.remaining
_lea x6, options
ldr w2, [x6, Options.minThinkTime]
add x0, x0, x2
cmp x22, x0
csel x22, x0, x22, hi
mov x1, x21
mov w2, w27
ldr w8, [sp, TimeMng_Init.ply]
ldr d4, TimeMng_Init.MaxRatio
ldr d5, TimeMng_Init.StealRatio
bl TimeMng_Init.remaining
_lea x6, options
ldr w2, [x6, Options.minThinkTime]
add w0, w0, w2
cmp x23, x0
csel x23, x0, x23, hi
b TimeMng_Init.loop
TimeMng_Init.loopdone:
_lea x6, options
ldrb w0, [x6, Options.ponder]
cbz w0, TimeMng_Init.noponder
add x22, x22, x22, lsr 2
TimeMng_Init.noponder:
_lea x6, time
str x22, [x6, Time.optimumTime]
str x23, [x6, Time.maximumTime]
Display 1, "optimumTime: %I22 maximumTime: %I23\n"
add sp, sp, TimeMng_Init.localsize
ldp x24, x25, [sp], 16
ldp x22, x23, [sp], 16
ldp x26, x27, [sp], 16
ldp x21, x30, [sp], 16
ret
TimeMng_Init.remaining:
stp x29, x30, [sp, -16]!
fmov d2, xzr
scvtf d3, x1
bl TimeMng_Init.move_importance
_lea x6, options
ldr w4, [x6, Options.slowMover]
scvtf d1, w4
fmul d6, d0, d1
ldr d7, TimeMng_Init.constd.100p0
fdiv d6, d6, d7
fmov d2, xzr
add w1, w8, w2, lsl 1
TimeMng_Init.otherLoop:
add w8, w8, 2
cmp w8, w1
bhs TimeMng_Init.otherDone
bl TimeMng_Init.move_importance
fadd d2, d2, d0
b TimeMng_Init.otherLoop
TimeMng_Init.otherDone:
fmul d4, d4, d6
fmul d5, d5, d2
fadd d0, d4, d2
fdiv d4, d4, d0
fadd d5, d5, d6
fadd d0, d6, d2
fdiv d5, d5, d0
fmin d4, d4, d5
fmul d3, d3, d4
fcvtzs x0, d3
ldp x29, x30, [sp], 16
ret
TimeMng_Init.move_importance:
stp x1, x30, [sp, -16]!
stp x2, x8, [sp, -16]!
stp d1, d2, [sp, -16]!
stp d3, d4, [sp, -16]!
stp d5, d6, [sp, -16]!
scvtf d0, w8
ldr d1, TimeMng_Init.XShift
ldr d2, TimeMng_Init.XScale
fsub d0, d0, d1
fdiv d0, d0, d2
bl Math_exp_d_d
fmov d2, 1.0
fadd d0, d0, d2
ldr d1, TimeMng_Init.mSkew
bl Math_pow_d_dd
ldr d1, TimeMng_Init.mind
fadd d0, d0, d1
ldp d5, d6, [sp], 16
ldp d3, d4, [sp], 16
ldp d1, d2, [sp], 16
ldp x2, x8, [sp], 16
ldp x1, x30, [sp], 16
ret
TimeMng_Init.XShift:
dq 64.5
TimeMng_Init.XScale:
dq 6.85
TimeMng_Init.mSkew:
dq -0.171
TimeMng_Init.MaxRatio:
dq 7.3
TimeMng_Init.StealRatio:
dq 0.34
TimeMng_Init.mind:
dd 0
dd 1048576
TimeMng_Init.constd.100p0:
dd 0
dd 1079574528
| {
"language": "Assembly"
} |
// Prettify
.prettyprinted
padding: 0
margin-bottom: 25px
background-color: #f9f9f9
border: 1px solid #F0F0F0
border-radius: 3px
.linenums
list-style-position: inside
color: #333
li
padding: 5px 0 5px 10px
font-size: 14px !important
color: rgba(0, 0, 0, 0.3) !important
word-wrap: break-word
code
white-space: normal
background: transparent
font-size: 14px !important
&:nth-child(even)
background: rgba(0, 0, 0, .02)
&:hover
background: rgba(0, 0, 0, .07)
pre ol,
pre ul
margin-bottom: 0 !important
padding-bottom: 0 !important
li
margin: 0 !important
.pln
color: #4d4d4c
@media screen
.str
color: #718c00
.kwd
color: #8959a8
.com
color: #8e908c
.typ
color: #4271ae
.lit
color: #f5871f
.pun
color: #4d4d4c
.opn
color: #4d4d4c
.clo
color: #4d4d4c
.tag
color: #c82829
.atn
color: #f5871f
.atv
color: #3e999f
.dec
color: #f5871f
.var
color: #c82829
.fun
color: #4271ae
@media print, projection
.str
color: #006600
.kwd
color: #006
font-weight: bold
.com
color: #600
font-style: italic
.typ
color: #404
font-weight: bold
.lit
color: #004444
.pun, .opn, .clo
color: #444400
.tag
color: #006
font-weight: bold
.atn
color: #440044
.atv
color: #006600
/* Specify class=linenums on a pre to get line numbering */
ol.linenums
margin-top: 0
margin-bottom: 0
| {
"language": "Assembly"
} |
# RUN: llvm-mc -disassemble -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s
# CHECK: vadd.f16 s0, s1, s0
[0x80,0x09,0x30,0xee]
# CHECK: vsub.f16 s0, s1, s0
[0xc0,0x09,0x30,0xee]
# CHECK: vdiv.f16 s0, s1, s0
[0x80,0x09,0x80,0xee]
# CHECK: vmul.f16 s0, s1, s0
[0x80,0x09,0x20,0xee]
# CHECK: vnmul.f16 s0, s1, s0
[0xc0,0x09,0x20,0xee]
# CHECK: vmla.f16 s1, s2, s0
[0x00,0x09,0x41,0xee]
# CHECK: vmls.f16 s1, s2, s0
[0x40,0x09,0x41,0xee]
# CHECK: vnmla.f16 s1, s2, s0
[0x40,0x09,0x51,0xee]
# CHECK: vnmls.f16 s1, s2, s0
[0x00,0x09,0x51,0xee]
# CHECK: vcmp.f16 s0, s1
[0x60,0x09,0xb4,0xee]
# CHECK: vcmp.f16 s2, #0
[0x40,0x19,0xb5,0xee]
# CHECK: vcmpe.f16 s1, s0
[0xc0,0x09,0xf4,0xee]
# CHECK: vcmpe.f16 s0, #0
[0xc0,0x09,0xb5,0xee]
# CHECK: vabs.f16 s0, s0
[0xc0,0x09,0xb0,0xee]
# CHECK: vneg.f16 s0, s0
[0x40,0x09,0xb1,0xee]
# CHECK: vsqrt.f16 s0, s0
[0xc0,0x09,0xb1,0xee]
# CHECK: vcvt.f16.s32 s0, s0
# CHECK: vcvt.f16.u32 s0, s0
# CHECK: vcvt.s32.f16 s0, s0
# CHECK: vcvt.u32.f16 s0, s0
[0xc0,0x09,0xb8,0xee]
[0x40,0x09,0xb8,0xee]
[0xc0,0x09,0xbd,0xee]
[0xc0,0x09,0xbc,0xee]
# CHECK: vcvtr.s32.f16 s0, s1
# CHECK: vcvtr.u32.f16 s0, s1
[0x60,0x09,0xbd,0xee]
[0x60,0x09,0xbc,0xee]
# CHECK: vcvt.f16.u32 s0, s0, #20
# CHECK: vcvt.f16.u16 s0, s0, #1
# CHECK: vcvt.f16.s32 s1, s1, #20
# CHECK: vcvt.f16.s16 s17, s17, #1
# CHECK: vcvt.u32.f16 s12, s12, #20
# CHECK: vcvt.u16.f16 s28, s28, #1
# CHECK: vcvt.s32.f16 s1, s1, #20
# CHECK: vcvt.s16.f16 s17, s17, #1
[0xc6,0x09,0xbb,0xee]
[0x67,0x09,0xbb,0xee]
[0xc6,0x09,0xfa,0xee]
[0x67,0x89,0xfa,0xee]
[0xc6,0x69,0xbf,0xee]
[0x67,0xe9,0xbf,0xee]
[0xc6,0x09,0xfe,0xee]
[0x67,0x89,0xfe,0xee]
# CHECK: vcvta.s32.f16 s2, s3
[0xe1,0x19,0xbc,0xfe]
# CHECK: vcvtn.s32.f16 s6, s23
[0xeb,0x39,0xbd,0xfe]
# CHECK: vcvtp.s32.f16 s0, s4
[0xc2,0x09,0xbe,0xfe]
# CHECK: vcvtm.s32.f16 s17, s8
[0xc4,0x89,0xff,0xfe]
# CHECK: vcvta.u32.f16 s2, s3
[0x61,0x19,0xbc,0xfe]
# CHECK: vcvtn.u32.f16 s6, s23
[0x6b,0x39,0xbd,0xfe]
# CHECK: vcvtp.u32.f16 s0, s4
[0x42,0x09,0xbe,0xfe]
# CHECK: vcvtm.u32.f16 s17, s8
[0x44,0x89,0xff,0xfe]
# CHECK: vselge.f16 s4, s1, s23
[0xab,0x29,0x20,0xfe]
# CHECK: vselgt.f16 s0, s1, s0
[0x80,0x09,0x30,0xfe]
# CHECK: vseleq.f16 s30, s28, s23
[0x2b,0xf9,0x0e,0xfe]
# CHECK: vselvs.f16 s21, s16, s14
[0x07,0xa9,0x58,0xfe]
# CHECK: vmaxnm.f16 s5, s12, s0
[0x00,0x29,0xc6,0xfe]
# CHECK: vminnm.f16 s0, s0, s12
[0x46,0x09,0x80,0xfe]
# CHECK: vrintz.f16 s3, s24
[0xcc,0x19,0xf6,0xee]
# CHECK: vrintr.f16 s0, s9
[0x64,0x09,0xb6,0xee]
# CHECK: vrintx.f16 s10, s14
[0x47,0x59,0xb7,0xee]
# CHECK: vrinta.f16 s12, s1
[0x60,0x69,0xb8,0xfe]
# CHECK: vrintn.f16 s12, s1
[0x60,0x69,0xb9,0xfe]
# CHECK: vrintp.f16 s12, s1
[0x60,0x69,0xba,0xfe]
# CHECK: vrintm.f16 s12, s1
[0x60,0x69,0xbb,0xfe]
# CHECK: vfma.f16 s2, s7, s4
[0x82,0x19,0xa3,0xee]
# CHECK: vfms.f16 s2, s7, s4
[0xc2,0x19,0xa3,0xee]
# CHECK: vfnma.f16 s2, s7, s4
[0xc2,0x19,0x93,0xee]
# CHECK: vfnms.f16 s2, s7, s4
[0x82,0x19,0x93,0xee]
# CHECK: vmovx.f16 s2, s5
# CHECK: vins.f16 s2, s5
[0x62,0x1a,0xb0,0xfe]
[0xe2,0x1a,0xb0,0xfe]
# CHECK: vldr.16 s1, [pc, #6]
# CHECK: vldr.16 s2, [pc, #510]
# CHECK: vldr.16 s3, [pc, #-510]
# CHECK: vldr.16 s4, [r4, #-18]
[0x03,0x09,0xdf,0xed]
[0xff,0x19,0x9f,0xed]
[0xff,0x19,0x5f,0xed]
[0x09,0x29,0x14,0xed]
# CHECK: vstr.16 s1, [pc, #6]
# CHECK: vstr.16 s2, [pc, #510]
# CHECK: vstr.16 s3, [pc, #-510]
# CHECK: vstr.16 s4, [r4, #-18]
[0x03,0x09,0xcf,0xed]
[0xff,0x19,0x8f,0xed]
[0xff,0x19,0x4f,0xed]
[0x09,0x29,0x04,0xed]
# CHECK: vmov.f16 s0, #1.0
[0x00,0x09,0xb7,0xee]
# CHECK: vmov.f16 s1, r2
# CHECK: vmov.f16 r3, s4
[0x90,0x29,0x00,0xee]
[0x10,0x39,0x12,0xee]
| {
"language": "Assembly"
} |
.subttl 'wd1770.src'
.page
wdtest .macro
.ife <*!.$03 ; lower two bits cannot be zero
nop ; fill address error
.endif
.endm
nodrrd .macro ; read nodrv,x absolute
.byte $bd,$ff,$00
.endm
nodrwr .macro ; write nodrv,x absolute
.byte $9d,$ff,$00
.endm
| {
"language": "Assembly"
} |
/* -----------------------------------------------------------------------
darwin.S - Copyright (c) 1996, 1998, 2001, 2002, 2003, 2005 Red Hat, Inc.
Copyright (C) 2008 Free Software Foundation, Inc.
X86 Foreign Function Interface
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
``Software''), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
-----------------------------------------------------------------------
*/
#ifndef __x86_64__
#define LIBFFI_ASM
#include <fficonfig.h>
#include <ffi.h>
.text
.globl _ffi_prep_args
.align 4
.globl _ffi_call_SYSV
_ffi_call_SYSV:
.LFB1:
pushl %ebp
.LCFI0:
movl %esp,%ebp
.LCFI1:
subl $8,%esp
/* Make room for all of the new args. */
movl 16(%ebp),%ecx
subl %ecx,%esp
movl %esp,%eax
/* Place all of the ffi_prep_args in position */
subl $8,%esp
pushl 12(%ebp)
pushl %eax
call *8(%ebp)
/* Return stack to previous state and call the function */
addl $16,%esp
call *28(%ebp)
/* Load %ecx with the return type code */
movl 20(%ebp),%ecx
/* Protect %esi. We're going to pop it in the epilogue. */
pushl %esi
/* If the return value pointer is NULL, assume no return value. */
cmpl $0,24(%ebp)
jne 0f
/* Even if there is no space for the return value, we are
obliged to handle floating-point values. */
cmpl $FFI_TYPE_FLOAT,%ecx
jne noretval
fstp %st(0)
jmp epilogue
0:
.align 4
call 1f
.Lstore_table:
.long noretval-.Lstore_table /* FFI_TYPE_VOID */
.long retint-.Lstore_table /* FFI_TYPE_INT */
.long retfloat-.Lstore_table /* FFI_TYPE_FLOAT */
.long retdouble-.Lstore_table /* FFI_TYPE_DOUBLE */
.long retlongdouble-.Lstore_table /* FFI_TYPE_LONGDOUBLE */
.long retuint8-.Lstore_table /* FFI_TYPE_UINT8 */
.long retsint8-.Lstore_table /* FFI_TYPE_SINT8 */
.long retuint16-.Lstore_table /* FFI_TYPE_UINT16 */
.long retsint16-.Lstore_table /* FFI_TYPE_SINT16 */
.long retint-.Lstore_table /* FFI_TYPE_UINT32 */
.long retint-.Lstore_table /* FFI_TYPE_SINT32 */
.long retint64-.Lstore_table /* FFI_TYPE_UINT64 */
.long retint64-.Lstore_table /* FFI_TYPE_SINT64 */
.long retstruct-.Lstore_table /* FFI_TYPE_STRUCT */
.long retint-.Lstore_table /* FFI_TYPE_POINTER */
.long retstruct1b-.Lstore_table /* FFI_TYPE_SMALL_STRUCT_1B */
.long retstruct2b-.Lstore_table /* FFI_TYPE_SMALL_STRUCT_2B */
1:
pop %esi
add (%esi, %ecx, 4), %esi
jmp *%esi
/* Sign/zero extend as appropriate. */
retsint8:
movsbl %al, %eax
jmp retint
retsint16:
movswl %ax, %eax
jmp retint
retuint8:
movzbl %al, %eax
jmp retint
retuint16:
movzwl %ax, %eax
jmp retint
retfloat:
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
fstps (%ecx)
jmp epilogue
retdouble:
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
fstpl (%ecx)
jmp epilogue
retlongdouble:
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
fstpt (%ecx)
jmp epilogue
retint64:
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movl %eax,0(%ecx)
movl %edx,4(%ecx)
jmp epilogue
retstruct1b:
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movb %al,0(%ecx)
jmp epilogue
retstruct2b:
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movw %ax,0(%ecx)
jmp epilogue
retint:
/* Load %ecx with the pointer to storage for the return value */
movl 24(%ebp),%ecx
movl %eax,0(%ecx)
retstruct:
/* Nothing to do! */
noretval:
epilogue:
popl %esi
movl %ebp,%esp
popl %ebp
ret
.LFE1:
.ffi_call_SYSV_end:
.align 4
FFI_HIDDEN (ffi_closure_SYSV)
.globl _ffi_closure_SYSV
_ffi_closure_SYSV:
.LFB2:
pushl %ebp
.LCFI2:
movl %esp, %ebp
.LCFI3:
subl $40, %esp
leal -24(%ebp), %edx
movl %edx, -12(%ebp) /* resp */
leal 8(%ebp), %edx
movl %edx, 4(%esp) /* args = __builtin_dwarf_cfa () */
leal -12(%ebp), %edx
movl %edx, (%esp) /* &resp */
movl %ebx, 8(%esp)
.LCFI7:
call L_ffi_closure_SYSV_inner$stub
movl 8(%esp), %ebx
movl -12(%ebp), %ecx
cmpl $FFI_TYPE_INT, %eax
je .Lcls_retint
/* Handle FFI_TYPE_UINT8, FFI_TYPE_SINT8, FFI_TYPE_UINT16,
FFI_TYPE_SINT16, FFI_TYPE_UINT32, FFI_TYPE_SINT32. */
cmpl $FFI_TYPE_UINT64, %eax
jge 0f
cmpl $FFI_TYPE_UINT8, %eax
jge .Lcls_retint
0: cmpl $FFI_TYPE_FLOAT, %eax
je .Lcls_retfloat
cmpl $FFI_TYPE_DOUBLE, %eax
je .Lcls_retdouble
cmpl $FFI_TYPE_LONGDOUBLE, %eax
je .Lcls_retldouble
cmpl $FFI_TYPE_SINT64, %eax
je .Lcls_retllong
cmpl $FFI_TYPE_SMALL_STRUCT_1B, %eax
je .Lcls_retstruct1b
cmpl $FFI_TYPE_SMALL_STRUCT_2B, %eax
je .Lcls_retstruct2b
cmpl $FFI_TYPE_STRUCT, %eax
je .Lcls_retstruct
.Lcls_epilogue:
movl %ebp, %esp
popl %ebp
ret
.Lcls_retint:
movl (%ecx), %eax
jmp .Lcls_epilogue
.Lcls_retfloat:
flds (%ecx)
jmp .Lcls_epilogue
.Lcls_retdouble:
fldl (%ecx)
jmp .Lcls_epilogue
.Lcls_retldouble:
fldt (%ecx)
jmp .Lcls_epilogue
.Lcls_retllong:
movl (%ecx), %eax
movl 4(%ecx), %edx
jmp .Lcls_epilogue
.Lcls_retstruct1b:
movsbl (%ecx), %eax
jmp .Lcls_epilogue
.Lcls_retstruct2b:
movswl (%ecx), %eax
jmp .Lcls_epilogue
.Lcls_retstruct:
lea -8(%ebp),%esp
movl %ebp, %esp
popl %ebp
ret $4
.LFE2:
#if !FFI_NO_RAW_API
#define RAW_CLOSURE_CIF_OFFSET ((FFI_TRAMPOLINE_SIZE + 3) & ~3)
#define RAW_CLOSURE_FUN_OFFSET (RAW_CLOSURE_CIF_OFFSET + 4)
#define RAW_CLOSURE_USER_DATA_OFFSET (RAW_CLOSURE_FUN_OFFSET + 4)
#define CIF_FLAGS_OFFSET 20
.align 4
FFI_HIDDEN (ffi_closure_raw_SYSV)
.globl _ffi_closure_raw_SYSV
_ffi_closure_raw_SYSV:
.LFB3:
pushl %ebp
.LCFI4:
movl %esp, %ebp
.LCFI5:
pushl %esi
.LCFI6:
subl $36, %esp
movl RAW_CLOSURE_CIF_OFFSET(%eax), %esi /* closure->cif */
movl RAW_CLOSURE_USER_DATA_OFFSET(%eax), %edx /* closure->user_data */
movl %edx, 12(%esp) /* user_data */
leal 8(%ebp), %edx /* __builtin_dwarf_cfa () */
movl %edx, 8(%esp) /* raw_args */
leal -24(%ebp), %edx
movl %edx, 4(%esp) /* &res */
movl %esi, (%esp) /* cif */
call *RAW_CLOSURE_FUN_OFFSET(%eax) /* closure->fun */
movl CIF_FLAGS_OFFSET(%esi), %eax /* rtype */
cmpl $FFI_TYPE_INT, %eax
je .Lrcls_retint
/* Handle FFI_TYPE_UINT8, FFI_TYPE_SINT8, FFI_TYPE_UINT16,
FFI_TYPE_SINT16, FFI_TYPE_UINT32, FFI_TYPE_SINT32. */
cmpl $FFI_TYPE_UINT64, %eax
jge 0f
cmpl $FFI_TYPE_UINT8, %eax
jge .Lrcls_retint
0:
cmpl $FFI_TYPE_FLOAT, %eax
je .Lrcls_retfloat
cmpl $FFI_TYPE_DOUBLE, %eax
je .Lrcls_retdouble
cmpl $FFI_TYPE_LONGDOUBLE, %eax
je .Lrcls_retldouble
cmpl $FFI_TYPE_SINT64, %eax
je .Lrcls_retllong
.Lrcls_epilogue:
addl $36, %esp
popl %esi
popl %ebp
ret
.Lrcls_retint:
movl -24(%ebp), %eax
jmp .Lrcls_epilogue
.Lrcls_retfloat:
flds -24(%ebp)
jmp .Lrcls_epilogue
.Lrcls_retdouble:
fldl -24(%ebp)
jmp .Lrcls_epilogue
.Lrcls_retldouble:
fldt -24(%ebp)
jmp .Lrcls_epilogue
.Lrcls_retllong:
movl -24(%ebp), %eax
movl -20(%ebp), %edx
jmp .Lrcls_epilogue
.LFE3:
#endif
.section __IMPORT,__jump_table,symbol_stubs,self_modifying_code+pure_instructions,5
L_ffi_closure_SYSV_inner$stub:
.indirect_symbol _ffi_closure_SYSV_inner
hlt ; hlt ; hlt ; hlt ; hlt
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
EH_frame1:
.set L$set$0,LECIE1-LSCIE1
.long L$set$0
LSCIE1:
.long 0x0
.byte 0x1
.ascii "zR\0"
.byte 0x1
.byte 0x7c
.byte 0x8
.byte 0x1
.byte 0x10
.byte 0xc
.byte 0x5
.byte 0x4
.byte 0x88
.byte 0x1
.align 2
LECIE1:
.globl _ffi_call_SYSV.eh
_ffi_call_SYSV.eh:
LSFDE1:
.set L$set$1,LEFDE1-LASFDE1
.long L$set$1
LASFDE1:
.long LASFDE1-EH_frame1
.long .LFB1-.
.set L$set$2,.LFE1-.LFB1
.long L$set$2
.byte 0x0
.byte 0x4
.set L$set$3,.LCFI0-.LFB1
.long L$set$3
.byte 0xe
.byte 0x8
.byte 0x84
.byte 0x2
.byte 0x4
.set L$set$4,.LCFI1-.LCFI0
.long L$set$4
.byte 0xd
.byte 0x4
.align 2
LEFDE1:
.globl _ffi_closure_SYSV.eh
_ffi_closure_SYSV.eh:
LSFDE2:
.set L$set$5,LEFDE2-LASFDE2
.long L$set$5
LASFDE2:
.long LASFDE2-EH_frame1
.long .LFB2-.
.set L$set$6,.LFE2-.LFB2
.long L$set$6
.byte 0x0
.byte 0x4
.set L$set$7,.LCFI2-.LFB2
.long L$set$7
.byte 0xe
.byte 0x8
.byte 0x84
.byte 0x2
.byte 0x4
.set L$set$8,.LCFI3-.LCFI2
.long L$set$8
.byte 0xd
.byte 0x4
.align 2
LEFDE2:
#if !FFI_NO_RAW_API
.globl _ffi_closure_raw_SYSV.eh
_ffi_closure_raw_SYSV.eh:
LSFDE3:
.set L$set$10,LEFDE3-LASFDE3
.long L$set$10
LASFDE3:
.long LASFDE3-EH_frame1
.long .LFB3-.
.set L$set$11,.LFE3-.LFB3
.long L$set$11
.byte 0x0
.byte 0x4
.set L$set$12,.LCFI4-.LFB3
.long L$set$12
.byte 0xe
.byte 0x8
.byte 0x84
.byte 0x2
.byte 0x4
.set L$set$13,.LCFI5-.LCFI4
.long L$set$13
.byte 0xd
.byte 0x4
.byte 0x4
.set L$set$14,.LCFI6-.LCFI5
.long L$set$14
.byte 0x85
.byte 0x3
.align 2
LEFDE3:
#endif
#endif /* ifndef __x86_64__ */
| {
"language": "Assembly"
} |
; Tests for SSE1 and below, without SSE2+.
; RUN: llc < %s -mtriple=i386-unknown-unknown -march=x86 -mcpu=pentium3 -O3 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s
; PR7993
;define <4 x i32> @test3(<4 x i16> %a) nounwind {
; %c = sext <4 x i16> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
; ret <4 x i32> %c
;}
; This should not emit shuffles to populate the top 2 elements of the 4-element
; vector that this ends up returning.
; rdar://8368414
define <2 x float> @test4(<2 x float> %A, <2 x float> %B) nounwind {
; CHECK-LABEL: test4:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: movaps %xmm0, %xmm2
; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
; CHECK-NEXT: subss %xmm1, %xmm2
; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: ret
entry:
%tmp7 = extractelement <2 x float> %A, i32 0
%tmp5 = extractelement <2 x float> %A, i32 1
%tmp3 = extractelement <2 x float> %B, i32 0
%tmp1 = extractelement <2 x float> %B, i32 1
%add.r = fadd float %tmp7, %tmp3
%add.i = fsub float %tmp5, %tmp1
%tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
%tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
ret <2 x float> %tmp9
}
; We used to get stuck in type legalization for this example when lowering the
; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
; is not. We used to ping pong between splitting the vselect for the v4i
; condition operand and widening the resulting vselect for the v4f32 result.
; PR18036
define <4 x float> @vselect(<4 x float>*%p, <4 x i32> %q) {
; CHECK-LABEL: vselect:
; CHECK: ret
entry:
%a1 = icmp eq <4 x i32> %q, zeroinitializer
%a14 = select <4 x i1> %a1, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+0> , <4 x float> zeroinitializer
ret <4 x float> %a14
}
| {
"language": "Assembly"
} |
/* wait4 -- wait for process to change state. Linux/Alpha version.
Copyright (C) 2019-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#include <shlib-compat.h>
#undef weak_alias
#define weak_alias(a, b)
#include <sysdeps/unix/sysv/linux/wait4.c>
versioned_symbol (libc, __wait4, wait4, GLIBC_2_1);
/* GLIBC_2_0 version is implemented at osf_wait4.c. */
| {
"language": "Assembly"
} |
/* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
import OptionalParams.*;
import com.adobe.test.Assert;
// var SECTION = "Definitions"; // provide a document reference (ie, ECMA section)
// var VERSION = "AS 3.0"; // Version of JavaScript or ECMA
// var TITLE = "Override a method defined in a namespace"; // Provide ECMA section title or a description
var BUGNUMBER = "";
var base = new BaseClass();
var obj = new OverrideWithOptionalParams();
Assert.expectEq( "base.setInt(), base.i", 0, ( base.setInt(), base.i ) );
Assert.expectEq( "base.setInt(3), base.i", 3, ( base.setInt(3), base.i ) );
Assert.expectEq( "base.setString(), base.s", "default", ( base.setString(), base.s ) );
Assert.expectEq( "base.setString('here'), base.s", "here", ( base.setString("here"), base.s ) );
Assert.expectEq( "base.setAll(), base.i base.s", "0default", ( base.setAll(), (base.i + base.s) ) );
Assert.expectEq( "base.setAll(6, 'here'), base.i base.s", "6here", ( base.setAll(6, "here"), (base.i + base.s) ) );
Assert.expectEq( "obj.setInt(), obj.i", 1, ( obj.setInt(), obj.i ) );
Assert.expectEq( "obj.setInt(3), obj.i", 3, ( obj.setInt(3), obj.i ) );
Assert.expectEq( "obj.setString(), obj.s", "override", ( obj.setString(), obj.s ) );
Assert.expectEq( "obj.setString('here'), obj.s", "here", ( obj.setString("here"), obj.s ) );
Assert.expectEq( "obj.setAll(), obj.i obj.s", "1override", ( obj.setAll(), (obj.i + obj.s) ) );
Assert.expectEq( "obj.setAll(6, 'here'), obj.i obj.s", "6here", ( obj.setAll(6, "here"), (obj.i + obj.s) ) );
// This function is for executing the test case and then
// displaying the result on to the console or the LOG file.
| {
"language": "Assembly"
} |
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
foo:
lsr r31
lsr r25
lsr r5
lsr r0
; CHECK: lsr r31 ; encoding: [0xf6,0x95]
; CHECK: lsr r25 ; encoding: [0x96,0x95]
; CHECK: lsr r5 ; encoding: [0x56,0x94]
; CHECK: lsr r0 ; encoding: [0x06,0x94]
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -o - | FileCheck %s
// rdar: // 8027844
// CHECK: call void @llvm.memset
int main() {
id foo;
for (id a in foo) {
}
}
| {
"language": "Assembly"
} |
// Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for ppc64, AIX are implemented in runtime/syscall_aix.go
//
TEXT ·syscall6(SB),NOSPLIT,$0-88
JMP syscall·syscall6(SB)
TEXT ·rawSyscall6(SB),NOSPLIT,$0-88
JMP syscall·rawSyscall6(SB)
| {
"language": "Assembly"
} |
#!/usr/bin/env perl
#
# ====================================================================
# Written by Andy Polyakov <[email protected]> for the OpenSSL
# project. Rights for redistribution and usage in source and binary
# forms are granted according to the OpenSSL license.
# ====================================================================
#
# Version 1.1
#
# The major reason for undertaken effort was to mitigate the hazard of
# cache-timing attack. This is [currently and initially!] addressed in
# two ways. 1. S-boxes are compressed from 5KB to 2KB+256B size each.
# 2. References to them are scheduled for L2 cache latency, meaning
# that the tables don't have to reside in L1 cache. Once again, this
# is an initial draft and one should expect more countermeasures to
# be implemented...
#
# Version 1.1 prefetches T[ed]4 in order to mitigate attack on last
# round.
#
# Even though performance was not the primary goal [on the contrary,
# extra shifts "induced" by compressed S-box and longer loop epilogue
# "induced" by scheduling for L2 have negative effect on performance],
# the code turned out to run in ~23 cycles per processed byte en-/
# decrypted with 128-bit key. This is pretty good result for code
# with mentioned qualities and UltraSPARC core. Compared to Sun C
# generated code my encrypt procedure runs just few percents faster,
# while decrypt one - whole 50% faster [yes, Sun C failed to generate
# optimal decrypt procedure]. Compared to GNU C generated code both
# procedures are more than 60% faster:-)
$bits=32;
for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
if ($bits==64) { $bias=2047; $frame=192; }
else { $bias=0; $frame=112; }
$locals=16;
$acc0="%l0";
$acc1="%o0";
$acc2="%o1";
$acc3="%o2";
$acc4="%l1";
$acc5="%o3";
$acc6="%o4";
$acc7="%o5";
$acc8="%l2";
$acc9="%o7";
$acc10="%g1";
$acc11="%g2";
$acc12="%l3";
$acc13="%g3";
$acc14="%g4";
$acc15="%g5";
$t0="%l4";
$t1="%l5";
$t2="%l6";
$t3="%l7";
$s0="%i0";
$s1="%i1";
$s2="%i2";
$s3="%i3";
$tbl="%i4";
$key="%i5";
$rounds="%i7"; # aliases with return address, which is off-loaded to stack
sub _data_word()
{ my $i;
while(defined($i=shift)) { $code.=sprintf"\t.long\t0x%08x,0x%08x\n",$i,$i; }
}
$code.=<<___ if ($bits==64);
.register %g2,#scratch
.register %g3,#scratch
___
$code.=<<___;
.section ".text",#alloc,#execinstr
.align 256
AES_Te:
___
&_data_word(
0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d,
0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554,
0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d,
0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a,
0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87,
0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b,
0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea,
0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b,
0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a,
0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f,
0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108,
0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f,
0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e,
0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5,
0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d,
0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f,
0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e,
0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb,
0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce,
0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497,
0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c,
0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed,
0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b,
0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a,
0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16,
0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594,
0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81,
0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3,
0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a,
0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504,
0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163,
0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d,
0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f,
0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739,
0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47,
0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395,
0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f,
0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883,
0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c,
0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76,
0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e,
0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4,
0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6,
0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b,
0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7,
0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0,
0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25,
0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818,
0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72,
0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651,
0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21,
0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85,
0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa,
0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12,
0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0,
0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9,
0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133,
0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7,
0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920,
0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a,
0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17,
0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8,
0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11,
0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a);
$code.=<<___;
.byte 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
.byte 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
.byte 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
.byte 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
.byte 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
.byte 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
.byte 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
.byte 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
.byte 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
.byte 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
.byte 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
.byte 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
.byte 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
.byte 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
.byte 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
.byte 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
.byte 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
.byte 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
.byte 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
.byte 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
.byte 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
.byte 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
.byte 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
.byte 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
.byte 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
.byte 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
.byte 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
.byte 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
.byte 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
.byte 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
.byte 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
.byte 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
.type AES_Te,#object
.size AES_Te,(.-AES_Te)
.align 64
.skip 16
_sparcv9_AES_encrypt:
save %sp,-$frame-$locals,%sp
stx %i7,[%sp+$bias+$frame+0] ! off-load return address
ld [$key+240],$rounds
ld [$key+0],$t0
ld [$key+4],$t1 !
ld [$key+8],$t2
srl $rounds,1,$rounds
xor $t0,$s0,$s0
ld [$key+12],$t3
srl $s0,21,$acc0
xor $t1,$s1,$s1
ld [$key+16],$t0
srl $s1,13,$acc1 !
xor $t2,$s2,$s2
ld [$key+20],$t1
xor $t3,$s3,$s3
ld [$key+24],$t2
and $acc0,2040,$acc0
ld [$key+28],$t3
nop
.Lenc_loop:
srl $s2,5,$acc2 !
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $s3,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
srl $s1,21,$acc4
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2 !
srl $s2,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $s3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4
fmovs %f0,%f0
sll $s0,3,$acc7 !
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $s2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
srl $s3,13,$acc9
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7 !
srl $s0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $s1,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9
fmovs %f0,%f0
srl $s3,21,$acc12 !
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $s0,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
srl $s1,5,$acc14
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12 !
sll $s2,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
and $acc15,2040,$acc15
add $key,32,$key
ldx [$tbl+$acc14],$acc14
fmovs %f0,%f0
subcc $rounds,1,$rounds !
ldx [$tbl+$acc15],$acc15
bz,a,pn %icc,.Lenc_last
add $tbl,2048,$rounds
srlx $acc1,8,$acc1
xor $acc0,$t0,$t0
ld [$key+0],$s0
fmovs %f0,%f0
srlx $acc2,16,$acc2 !
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3 !
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
fmovs %f0,%f0
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10 !
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15 !
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,21,$acc0
xor $acc14,$t3,$t3
srl $t1,13,$acc1
xor $acc15,$t3,$t3
and $acc0,2040,$acc0 !
srl $t2,5,$acc2
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $t3,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
fmovs %f0,%f0
srl $t1,21,$acc4 !
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2
srl $t2,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $t3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4 !
sll $t0,3,$acc7
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $t2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
fmovs %f0,%f0
srl $t3,13,$acc9 !
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7
srl $t0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $t1,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9 !
srl $t3,21,$acc12
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $t0,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
fmovs %f0,%f0
srl $t1,5,$acc14 !
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12
sll $t2,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
srlx $acc1,8,$acc1
and $acc15,2040,$acc15
ldx [$tbl+$acc14],$acc14 !
srlx $acc2,16,$acc2
xor $acc0,$s0,$s0
ldx [$tbl+$acc15],$acc15
srlx $acc3,24,$acc3
xor $acc1,$s0,$s0
ld [$key+16],$t0
fmovs %f0,%f0
srlx $acc5,8,$acc5 !
xor $acc2,$s0,$s0
ld [$key+20],$t1
srlx $acc6,16,$acc6
xor $acc3,$s0,$s0
ld [$key+24],$t2
srlx $acc7,24,$acc7
xor $acc4,$s1,$s1
ld [$key+28],$t3 !
srlx $acc9,8,$acc9
xor $acc5,$s1,$s1
ldx [$tbl+2048+0],%g0 ! prefetch te4
srlx $acc10,16,$acc10
xor $acc6,$s1,$s1
ldx [$tbl+2048+32],%g0 ! prefetch te4
srlx $acc11,24,$acc11
xor $acc7,$s1,$s1
ldx [$tbl+2048+64],%g0 ! prefetch te4
srlx $acc13,8,$acc13
xor $acc8,$s2,$s2
ldx [$tbl+2048+96],%g0 ! prefetch te4
srlx $acc14,16,$acc14 !
xor $acc9,$s2,$s2
ldx [$tbl+2048+128],%g0 ! prefetch te4
srlx $acc15,24,$acc15
xor $acc10,$s2,$s2
ldx [$tbl+2048+160],%g0 ! prefetch te4
srl $s0,21,$acc0
xor $acc11,$s2,$s2
ldx [$tbl+2048+192],%g0 ! prefetch te4
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
ldx [$tbl+2048+224],%g0 ! prefetch te4
srl $s1,13,$acc1 !
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ba .Lenc_loop
and $acc0,2040,$acc0
.align 32
.Lenc_last:
srlx $acc1,8,$acc1 !
xor $acc0,$t0,$t0
ld [$key+0],$s0
srlx $acc2,16,$acc2
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2 !
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9 !
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14 !
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,24,$acc0
xor $acc14,$t3,$t3
srl $t1,16,$acc1 !
xor $acc15,$t3,$t3
srl $t2,8,$acc2
and $acc1,255,$acc1
ldub [$rounds+$acc0],$acc0
srl $t1,24,$acc4
and $acc2,255,$acc2
ldub [$rounds+$acc1],$acc1
srl $t2,16,$acc5 !
and $t3,255,$acc3
ldub [$rounds+$acc2],$acc2
ldub [$rounds+$acc3],$acc3
srl $t3,8,$acc6
and $acc5,255,$acc5
ldub [$rounds+$acc4],$acc4
fmovs %f0,%f0
srl $t2,24,$acc8 !
and $acc6,255,$acc6
ldub [$rounds+$acc5],$acc5
srl $t3,16,$acc9
and $t0,255,$acc7
ldub [$rounds+$acc6],$acc6
ldub [$rounds+$acc7],$acc7
fmovs %f0,%f0
srl $t0,8,$acc10 !
and $acc9,255,$acc9
ldub [$rounds+$acc8],$acc8
srl $t3,24,$acc12
and $acc10,255,$acc10
ldub [$rounds+$acc9],$acc9
srl $t0,16,$acc13
and $t1,255,$acc11
ldub [$rounds+$acc10],$acc10 !
srl $t1,8,$acc14
and $acc13,255,$acc13
ldub [$rounds+$acc11],$acc11
ldub [$rounds+$acc12],$acc12
and $acc14,255,$acc14
ldub [$rounds+$acc13],$acc13
and $t2,255,$acc15
ldub [$rounds+$acc14],$acc14 !
sll $acc0,24,$acc0
xor $acc3,$s0,$s0
ldub [$rounds+$acc15],$acc15
sll $acc1,16,$acc1
xor $acc0,$s0,$s0
ldx [%sp+$bias+$frame+0],%i7 ! restore return address
fmovs %f0,%f0
sll $acc2,8,$acc2 !
xor $acc1,$s0,$s0
sll $acc4,24,$acc4
xor $acc2,$s0,$s0
sll $acc5,16,$acc5
xor $acc7,$s1,$s1
sll $acc6,8,$acc6
xor $acc4,$s1,$s1
sll $acc8,24,$acc8 !
xor $acc5,$s1,$s1
sll $acc9,16,$acc9
xor $acc11,$s2,$s2
sll $acc10,8,$acc10
xor $acc6,$s1,$s1
sll $acc12,24,$acc12
xor $acc8,$s2,$s2
sll $acc13,16,$acc13 !
xor $acc9,$s2,$s2
sll $acc14,8,$acc14
xor $acc10,$s2,$s2
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ret
restore
.type _sparcv9_AES_encrypt,#function
.size _sparcv9_AES_encrypt,(.-_sparcv9_AES_encrypt)
.align 32
.globl AES_encrypt
AES_encrypt:
or %o0,%o1,%g1
andcc %g1,3,%g0
bnz,pn %xcc,.Lunaligned_enc
save %sp,-$frame,%sp
ld [%i0+0],%o0
ld [%i0+4],%o1
ld [%i0+8],%o2
ld [%i0+12],%o3
1: call .+8
add %o7,AES_Te-1b,%o4
call _sparcv9_AES_encrypt
mov %i2,%o5
st %o0,[%i1+0]
st %o1,[%i1+4]
st %o2,[%i1+8]
st %o3,[%i1+12]
ret
restore
.align 32
.Lunaligned_enc:
ldub [%i0+0],%l0
ldub [%i0+1],%l1
ldub [%i0+2],%l2
sll %l0,24,%l0
ldub [%i0+3],%l3
sll %l1,16,%l1
ldub [%i0+4],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+5],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+6],%l6
sll %l5,16,%l5
or %l0,%l2,%o0
ldub [%i0+7],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
ldub [%i0+8],%l0
or %l7,%l6,%l6
ldub [%i0+9],%l1
or %l4,%l6,%o1
ldub [%i0+10],%l2
sll %l0,24,%l0
ldub [%i0+11],%l3
sll %l1,16,%l1
ldub [%i0+12],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+13],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+14],%l6
sll %l5,16,%l5
or %l0,%l2,%o2
ldub [%i0+15],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
or %l7,%l6,%l6
or %l4,%l6,%o3
1: call .+8
add %o7,AES_Te-1b,%o4
call _sparcv9_AES_encrypt
mov %i2,%o5
srl %o0,24,%l0
srl %o0,16,%l1
stb %l0,[%i1+0]
srl %o0,8,%l2
stb %l1,[%i1+1]
stb %l2,[%i1+2]
srl %o1,24,%l4
stb %o0,[%i1+3]
srl %o1,16,%l5
stb %l4,[%i1+4]
srl %o1,8,%l6
stb %l5,[%i1+5]
stb %l6,[%i1+6]
srl %o2,24,%l0
stb %o1,[%i1+7]
srl %o2,16,%l1
stb %l0,[%i1+8]
srl %o2,8,%l2
stb %l1,[%i1+9]
stb %l2,[%i1+10]
srl %o3,24,%l4
stb %o2,[%i1+11]
srl %o3,16,%l5
stb %l4,[%i1+12]
srl %o3,8,%l6
stb %l5,[%i1+13]
stb %l6,[%i1+14]
stb %o3,[%i1+15]
ret
restore
.type AES_encrypt,#function
.size AES_encrypt,(.-AES_encrypt)
___
$code.=<<___;
.align 256
AES_Td:
___
&_data_word(
0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96,
0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393,
0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25,
0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f,
0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1,
0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6,
0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da,
0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844,
0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd,
0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4,
0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45,
0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94,
0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7,
0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a,
0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5,
0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c,
0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1,
0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a,
0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75,
0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051,
0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46,
0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff,
0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77,
0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb,
0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000,
0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e,
0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927,
0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a,
0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e,
0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16,
0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d,
0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8,
0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd,
0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34,
0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163,
0xd731dcca, 0x42638510, 0x13972240, 0x84c61120,
0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d,
0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0,
0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422,
0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef,
0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36,
0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4,
0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662,
0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5,
0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3,
0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b,
0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8,
0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6,
0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6,
0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0,
0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815,
0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f,
0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df,
0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f,
0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e,
0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713,
0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89,
0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c,
0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf,
0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86,
0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f,
0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541,
0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190,
0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742);
$code.=<<___;
.byte 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
.byte 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
.byte 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
.byte 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
.byte 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
.byte 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
.byte 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
.byte 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
.byte 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
.byte 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
.byte 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
.byte 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
.byte 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
.byte 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
.byte 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
.byte 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
.byte 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
.byte 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
.byte 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
.byte 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
.byte 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
.byte 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
.byte 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
.byte 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
.byte 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
.byte 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
.byte 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
.byte 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
.byte 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
.byte 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
.byte 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
.byte 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
.type AES_Td,#object
.size AES_Td,(.-AES_Td)
.align 64
.skip 16
_sparcv9_AES_decrypt:
save %sp,-$frame-$locals,%sp
stx %i7,[%sp+$bias+$frame+0] ! off-load return address
ld [$key+240],$rounds
ld [$key+0],$t0
ld [$key+4],$t1 !
ld [$key+8],$t2
ld [$key+12],$t3
srl $rounds,1,$rounds
xor $t0,$s0,$s0
ld [$key+16],$t0
xor $t1,$s1,$s1
ld [$key+20],$t1
srl $s0,21,$acc0 !
xor $t2,$s2,$s2
ld [$key+24],$t2
xor $t3,$s3,$s3
and $acc0,2040,$acc0
ld [$key+28],$t3
srl $s3,13,$acc1
nop
.Ldec_loop:
srl $s2,5,$acc2 !
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $s1,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
srl $s1,21,$acc4
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2 !
srl $s0,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $s3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4
fmovs %f0,%f0
sll $s2,3,$acc7 !
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $s2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
srl $s1,13,$acc9
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7 !
srl $s0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $s3,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9
fmovs %f0,%f0
srl $s3,21,$acc12 !
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $s2,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
srl $s1,5,$acc14
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12 !
sll $s0,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
and $acc15,2040,$acc15
add $key,32,$key
ldx [$tbl+$acc14],$acc14
fmovs %f0,%f0
subcc $rounds,1,$rounds !
ldx [$tbl+$acc15],$acc15
bz,a,pn %icc,.Ldec_last
add $tbl,2048,$rounds
srlx $acc1,8,$acc1
xor $acc0,$t0,$t0
ld [$key+0],$s0
fmovs %f0,%f0
srlx $acc2,16,$acc2 !
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3 !
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
fmovs %f0,%f0
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10 !
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15 !
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,21,$acc0
xor $acc14,$t3,$t3
xor $acc15,$t3,$t3
srl $t3,13,$acc1
and $acc0,2040,$acc0 !
srl $t2,5,$acc2
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $t1,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
fmovs %f0,%f0
srl $t1,21,$acc4 !
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2
srl $t0,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $t3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4 !
sll $t2,3,$acc7
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $t2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
fmovs %f0,%f0
srl $t1,13,$acc9 !
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7
srl $t0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $t3,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9 !
srl $t3,21,$acc12
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $t2,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
fmovs %f0,%f0
srl $t1,5,$acc14 !
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12
sll $t0,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
srlx $acc1,8,$acc1
and $acc15,2040,$acc15
ldx [$tbl+$acc14],$acc14 !
srlx $acc2,16,$acc2
xor $acc0,$s0,$s0
ldx [$tbl+$acc15],$acc15
srlx $acc3,24,$acc3
xor $acc1,$s0,$s0
ld [$key+16],$t0
fmovs %f0,%f0
srlx $acc5,8,$acc5 !
xor $acc2,$s0,$s0
ld [$key+20],$t1
srlx $acc6,16,$acc6
xor $acc3,$s0,$s0
ld [$key+24],$t2
srlx $acc7,24,$acc7
xor $acc4,$s1,$s1
ld [$key+28],$t3 !
srlx $acc9,8,$acc9
xor $acc5,$s1,$s1
ldx [$tbl+2048+0],%g0 ! prefetch td4
srlx $acc10,16,$acc10
xor $acc6,$s1,$s1
ldx [$tbl+2048+32],%g0 ! prefetch td4
srlx $acc11,24,$acc11
xor $acc7,$s1,$s1
ldx [$tbl+2048+64],%g0 ! prefetch td4
srlx $acc13,8,$acc13
xor $acc8,$s2,$s2
ldx [$tbl+2048+96],%g0 ! prefetch td4
srlx $acc14,16,$acc14 !
xor $acc9,$s2,$s2
ldx [$tbl+2048+128],%g0 ! prefetch td4
srlx $acc15,24,$acc15
xor $acc10,$s2,$s2
ldx [$tbl+2048+160],%g0 ! prefetch td4
srl $s0,21,$acc0
xor $acc11,$s2,$s2
ldx [$tbl+2048+192],%g0 ! prefetch td4
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
ldx [$tbl+2048+224],%g0 ! prefetch td4
and $acc0,2040,$acc0 !
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ba .Ldec_loop
srl $s3,13,$acc1
.align 32
.Ldec_last:
srlx $acc1,8,$acc1 !
xor $acc0,$t0,$t0
ld [$key+0],$s0
srlx $acc2,16,$acc2
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2 !
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9 !
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14 !
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,24,$acc0
xor $acc14,$t3,$t3
xor $acc15,$t3,$t3 !
srl $t3,16,$acc1
srl $t2,8,$acc2
and $acc1,255,$acc1
ldub [$rounds+$acc0],$acc0
srl $t1,24,$acc4
and $acc2,255,$acc2
ldub [$rounds+$acc1],$acc1
srl $t0,16,$acc5 !
and $t1,255,$acc3
ldub [$rounds+$acc2],$acc2
ldub [$rounds+$acc3],$acc3
srl $t3,8,$acc6
and $acc5,255,$acc5
ldub [$rounds+$acc4],$acc4
fmovs %f0,%f0
srl $t2,24,$acc8 !
and $acc6,255,$acc6
ldub [$rounds+$acc5],$acc5
srl $t1,16,$acc9
and $t2,255,$acc7
ldub [$rounds+$acc6],$acc6
ldub [$rounds+$acc7],$acc7
fmovs %f0,%f0
srl $t0,8,$acc10 !
and $acc9,255,$acc9
ldub [$rounds+$acc8],$acc8
srl $t3,24,$acc12
and $acc10,255,$acc10
ldub [$rounds+$acc9],$acc9
srl $t2,16,$acc13
and $t3,255,$acc11
ldub [$rounds+$acc10],$acc10 !
srl $t1,8,$acc14
and $acc13,255,$acc13
ldub [$rounds+$acc11],$acc11
ldub [$rounds+$acc12],$acc12
and $acc14,255,$acc14
ldub [$rounds+$acc13],$acc13
and $t0,255,$acc15
ldub [$rounds+$acc14],$acc14 !
sll $acc0,24,$acc0
xor $acc3,$s0,$s0
ldub [$rounds+$acc15],$acc15
sll $acc1,16,$acc1
xor $acc0,$s0,$s0
ldx [%sp+$bias+$frame+0],%i7 ! restore return address
fmovs %f0,%f0
sll $acc2,8,$acc2 !
xor $acc1,$s0,$s0
sll $acc4,24,$acc4
xor $acc2,$s0,$s0
sll $acc5,16,$acc5
xor $acc7,$s1,$s1
sll $acc6,8,$acc6
xor $acc4,$s1,$s1
sll $acc8,24,$acc8 !
xor $acc5,$s1,$s1
sll $acc9,16,$acc9
xor $acc11,$s2,$s2
sll $acc10,8,$acc10
xor $acc6,$s1,$s1
sll $acc12,24,$acc12
xor $acc8,$s2,$s2
sll $acc13,16,$acc13 !
xor $acc9,$s2,$s2
sll $acc14,8,$acc14
xor $acc10,$s2,$s2
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ret
restore
.type _sparcv9_AES_decrypt,#function
.size _sparcv9_AES_decrypt,(.-_sparcv9_AES_decrypt)
.align 32
.globl AES_decrypt
AES_decrypt:
or %o0,%o1,%g1
andcc %g1,3,%g0
bnz,pn %xcc,.Lunaligned_dec
save %sp,-$frame,%sp
ld [%i0+0],%o0
ld [%i0+4],%o1
ld [%i0+8],%o2
ld [%i0+12],%o3
1: call .+8
add %o7,AES_Td-1b,%o4
call _sparcv9_AES_decrypt
mov %i2,%o5
st %o0,[%i1+0]
st %o1,[%i1+4]
st %o2,[%i1+8]
st %o3,[%i1+12]
ret
restore
.align 32
.Lunaligned_dec:
ldub [%i0+0],%l0
ldub [%i0+1],%l1
ldub [%i0+2],%l2
sll %l0,24,%l0
ldub [%i0+3],%l3
sll %l1,16,%l1
ldub [%i0+4],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+5],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+6],%l6
sll %l5,16,%l5
or %l0,%l2,%o0
ldub [%i0+7],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
ldub [%i0+8],%l0
or %l7,%l6,%l6
ldub [%i0+9],%l1
or %l4,%l6,%o1
ldub [%i0+10],%l2
sll %l0,24,%l0
ldub [%i0+11],%l3
sll %l1,16,%l1
ldub [%i0+12],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+13],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+14],%l6
sll %l5,16,%l5
or %l0,%l2,%o2
ldub [%i0+15],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
or %l7,%l6,%l6
or %l4,%l6,%o3
1: call .+8
add %o7,AES_Td-1b,%o4
call _sparcv9_AES_decrypt
mov %i2,%o5
srl %o0,24,%l0
srl %o0,16,%l1
stb %l0,[%i1+0]
srl %o0,8,%l2
stb %l1,[%i1+1]
stb %l2,[%i1+2]
srl %o1,24,%l4
stb %o0,[%i1+3]
srl %o1,16,%l5
stb %l4,[%i1+4]
srl %o1,8,%l6
stb %l5,[%i1+5]
stb %l6,[%i1+6]
srl %o2,24,%l0
stb %o1,[%i1+7]
srl %o2,16,%l1
stb %l0,[%i1+8]
srl %o2,8,%l2
stb %l1,[%i1+9]
stb %l2,[%i1+10]
srl %o3,24,%l4
stb %o2,[%i1+11]
srl %o3,16,%l5
stb %l4,[%i1+12]
srl %o3,8,%l6
stb %l5,[%i1+13]
stb %l6,[%i1+14]
stb %o3,[%i1+15]
ret
restore
.type AES_decrypt,#function
.size AES_decrypt,(.-AES_decrypt)
___
# fmovs instructions substituting for FP nops were originally added
# to meet specific instruction alignment requirements to maximize ILP.
# As UltraSPARC T1, a.k.a. Niagara, has shared FPU, FP nops can have
# undesired effect, so just omit them and sacrifice some portion of
# percent in performance...
$code =~ s/fmovs.*$//gm;
print $code;
close STDOUT; # ensure flush
| {
"language": "Assembly"
} |
// go run mkasm_darwin.go 386
// Code generated by the command above; DO NOT EDIT.
// +build go1.13
#include "textflag.h"
TEXT ·libc_fdopendir_trampoline(SB),NOSPLIT,$0-0
JMP libc_fdopendir(SB)
TEXT ·libc_closedir_trampoline(SB),NOSPLIT,$0-0
JMP libc_closedir(SB)
TEXT ·libc_readdir_r_trampoline(SB),NOSPLIT,$0-0
JMP libc_readdir_r(SB)
| {
"language": "Assembly"
} |
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# ScanMem16.Asm
#
# Abstract:
#
# ScanMem16 function
#
# Notes:
#
# The following BaseMemoryLib instances contain the same copy of this file:
#
# BaseMemoryLibRepStr
# BaseMemoryLibMmx
# BaseMemoryLibSse2
# BaseMemoryLibOptDxe
# BaseMemoryLibOptPei
#
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InternalMemScanMem16)
#------------------------------------------------------------------------------
# CONST VOID *
# EFIAPI
# InternalMemScanMem16 (
# IN CONST VOID *Buffer,
# IN UINTN Length,
# IN UINT16 Value
# );
#------------------------------------------------------------------------------
ASM_PFX(InternalMemScanMem16):
push %edi
movl 12(%esp), %ecx
movl 8(%esp), %edi
movl 16(%esp), %eax
repne scasw
leal -2(%edi), %eax
cmovnz %ecx, %eax
pop %edi
ret
| {
"language": "Assembly"
} |
#include <stdio.h>
#include <frozen/map.h>
#define ELF_RELOC(name, value) name = value,
/** i386 relocations. */
enum class RELOC_i386 {
/* TODO: this is just a subset */
ELF_RELOC(R_386_NONE, 0)
ELF_RELOC(R_386_32, 1)
ELF_RELOC(R_386_PC32, 2)
ELF_RELOC(R_386_GOT32, 3)
ELF_RELOC(R_386_PLT32, 4)
ELF_RELOC(R_386_COPY, 5)
ELF_RELOC(R_386_GLOB_DAT, 6)
ELF_RELOC(R_386_JUMP_SLOT, 7)
ELF_RELOC(R_386_RELATIVE, 8)
ELF_RELOC(R_386_GOTOFF, 9)
};
constexpr frozen::map<RELOC_i386, const char*, 10> e2s = {
{ RELOC_i386::R_386_NONE, "NONE"},
{ RELOC_i386::R_386_32, "R32"},
{ RELOC_i386::R_386_PC32, "PC32"},
{ RELOC_i386::R_386_GOT32, "GOT32"},
{ RELOC_i386::R_386_PLT32, "PLT32"},
{ RELOC_i386::R_386_COPY, "COPY"},
{ RELOC_i386::R_386_GLOB_DAT, "GLOB_DAT"},
{ RELOC_i386::R_386_JUMP_SLOT, "JUMP_SLOT"},
{ RELOC_i386::R_386_RELATIVE, "RELATIVE"},
{ RELOC_i386::R_386_GOTOFF, "GOTOFF"}
};
int main()
{
printf("%s\n", e2s.at(RELOC_i386::R_386_GOT32));
return 0;
}
| {
"language": "Assembly"
} |
// Test code-completion in the presence of tabs
struct Point { int x, y; };
void f(struct Point *p) {
p->
// RUN: c-index-test -code-completion-at=%s:5:5 %s | FileCheck -check-prefix=CHECK-CC1 %s
// CHECK-CC1: {TypedText x}
// CHECK-CC1: {TypedText y}
| {
"language": "Assembly"
} |
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
@G1 = global i32 0
@G2 = global i32 0
define i1 @test0(i1 %A) {
; CHECK-LABEL: @test0(
; CHECK-NEXT: ret i1 [[A:%.*]]
;
%B = xor i1 %A, false
ret i1 %B
}
define i32 @test1(i32 %A) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: ret i32 [[A:%.*]]
;
%B = xor i32 %A, 0
ret i32 %B
}
define i1 @test2(i1 %A) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: ret i1 false
;
%B = xor i1 %A, %A
ret i1 %B
}
define i32 @test3(i32 %A) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: ret i32 0
;
%B = xor i32 %A, %A
ret i32 %B
}
define i32 @test4(i32 %A) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: ret i32 -1
;
%NotA = xor i32 -1, %A
%B = xor i32 %A, %NotA
ret i32 %B
}
define i32 @test5(i32 %A) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -124
; CHECK-NEXT: ret i32 [[TMP1]]
;
%t1 = or i32 %A, 123
%r = xor i32 %t1, 123
ret i32 %r
}
define i8 @test6(i8 %A) {
; CHECK-LABEL: @test6(
; CHECK-NEXT: ret i8 [[A:%.*]]
;
%B = xor i8 %A, 17
%C = xor i8 %B, 17
ret i8 %C
}
define i32 @test7(i32 %A, i32 %B) {
; CHECK-LABEL: @test7(
; CHECK-NEXT: [[A1:%.*]] = and i32 [[A:%.*]], 7
; CHECK-NEXT: [[B1:%.*]] = and i32 [[B:%.*]], 128
; CHECK-NEXT: [[C11:%.*]] = or i32 [[A1]], [[B1]]
; CHECK-NEXT: ret i32 [[C11]]
;
%A1 = and i32 %A, 7
%B1 = and i32 %B, 128
%C1 = xor i32 %A1, %B1
ret i32 %C1
}
define i8 @test8(i1 %c) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: br i1 [[C:%.*]], label [[FALSE:%.*]], label [[TRUE:%.*]]
; CHECK: True:
; CHECK-NEXT: ret i8 1
; CHECK: False:
; CHECK-NEXT: ret i8 3
;
%d = xor i1 %c, true
br i1 %d, label %True, label %False
True:
ret i8 1
False:
ret i8 3
}
define i1 @test9(i8 %A) {
; CHECK-LABEL: @test9(
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A:%.*]], 89
; CHECK-NEXT: ret i1 [[C]]
;
%B = xor i8 %A, 123
%C = icmp eq i8 %B, 34
ret i1 %C
}
define <2 x i1> @test9vec(<2 x i8> %a) {
; CHECK-LABEL: @test9vec(
; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[A:%.*]], <i8 89, i8 89>
; CHECK-NEXT: ret <2 x i1> [[C]]
;
%b = xor <2 x i8> %a, <i8 123, i8 123>
%c = icmp eq <2 x i8> %b, <i8 34, i8 34>
ret <2 x i1> %c
}
define i8 @test10(i8 %A) {
; CHECK-LABEL: @test10(
; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 3
; CHECK-NEXT: [[C1:%.*]] = or i8 [[B]], 4
; CHECK-NEXT: ret i8 [[C1]]
;
%B = and i8 %A, 3
%C = xor i8 %B, 4
ret i8 %C
}
define i8 @test11(i8 %A) {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -13
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[B]], 8
; CHECK-NEXT: ret i8 [[TMP1]]
;
%B = or i8 %A, 12
%C = xor i8 %B, 4
ret i8 %C
}
define i1 @test12(i8 %A) {
; CHECK-LABEL: @test12(
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A:%.*]], 4
; CHECK-NEXT: ret i1 [[C]]
;
%B = xor i8 %A, 4
%c = icmp ne i8 %B, 0
ret i1 %c
}
define <2 x i1> @test12vec(<2 x i8> %a) {
; CHECK-LABEL: @test12vec(
; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[A:%.*]], <i8 4, i8 4>
; CHECK-NEXT: ret <2 x i1> [[C]]
;
%b = xor <2 x i8> %a, <i8 4, i8 4>
%c = icmp ne <2 x i8> %b, zeroinitializer
ret <2 x i1> %c
}
define i32 @test18(i32 %A) {
; CHECK-LABEL: @test18(
; CHECK-NEXT: [[C:%.*]] = add i32 [[A:%.*]], 124
; CHECK-NEXT: ret i32 [[C]]
;
%B = xor i32 %A, -1
%C = sub i32 123, %B
ret i32 %C
}
define i32 @test19(i32 %A, i32 %B) {
; CHECK-LABEL: @test19(
; CHECK-NEXT: ret i32 [[B:%.*]]
;
%C = xor i32 %A, %B
%D = xor i32 %C, %A
ret i32 %D
}
define void @test20(i32 %A, i32 %B) {
; CHECK-LABEL: @test20(
; CHECK-NEXT: store i32 [[B:%.*]], i32* @G1, align 4
; CHECK-NEXT: store i32 [[A:%.*]], i32* @G2, align 4
; CHECK-NEXT: ret void
;
%t2 = xor i32 %B, %A
%t5 = xor i32 %t2, %B
%t8 = xor i32 %t5, %t2
store i32 %t8, i32* @G1
store i32 %t5, i32* @G2
ret void
}
define i32 @test22(i1 %X) {
; CHECK-LABEL: @test22(
; CHECK-NEXT: [[Z:%.*]] = zext i1 [[X:%.*]] to i32
; CHECK-NEXT: ret i32 [[Z]]
;
%Y = xor i1 %X, true
%Z = zext i1 %Y to i32
%Q = xor i32 %Z, 1
ret i32 %Q
}
; Look through a zext between xors.
define i32 @fold_zext_xor_sandwich(i1 %X) {
; CHECK-LABEL: @fold_zext_xor_sandwich(
; CHECK-NEXT: [[Z:%.*]] = zext i1 [[X:%.*]] to i32
; CHECK-NEXT: [[Q:%.*]] = xor i32 [[Z]], 3
; CHECK-NEXT: ret i32 [[Q]]
;
%Y = xor i1 %X, true
%Z = zext i1 %Y to i32
%Q = xor i32 %Z, 2
ret i32 %Q
}
define <2 x i32> @fold_zext_xor_sandwich_vec(<2 x i1> %X) {
; CHECK-LABEL: @fold_zext_xor_sandwich_vec(
; CHECK-NEXT: [[Z:%.*]] = zext <2 x i1> [[X:%.*]] to <2 x i32>
; CHECK-NEXT: [[Q:%.*]] = xor <2 x i32> [[Z]], <i32 3, i32 3>
; CHECK-NEXT: ret <2 x i32> [[Q]]
;
%Y = xor <2 x i1> %X, <i1 true, i1 true>
%Z = zext <2 x i1> %Y to <2 x i32>
%Q = xor <2 x i32> %Z, <i32 2, i32 2>
ret <2 x i32> %Q
}
define i1 @test23(i32 %a, i32 %b) {
; CHECK-LABEL: @test23(
; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[B:%.*]], 0
; CHECK-NEXT: ret i1 [[T4]]
;
%t2 = xor i32 %b, %a
%t4 = icmp eq i32 %t2, %a
ret i1 %t4
}
define i1 @test24(i32 %c, i32 %d) {
; CHECK-LABEL: @test24(
; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[D:%.*]], 0
; CHECK-NEXT: ret i1 [[T4]]
;
%t2 = xor i32 %d, %c
%t4 = icmp ne i32 %t2, %c
ret i1 %t4
}
define i32 @test25(i32 %g, i32 %h) {
; CHECK-LABEL: @test25(
; CHECK-NEXT: [[T4:%.*]] = and i32 [[H:%.*]], [[G:%.*]]
; CHECK-NEXT: ret i32 [[T4]]
;
%h2 = xor i32 %h, -1
%t2 = and i32 %h2, %g
%t4 = xor i32 %t2, %g
ret i32 %t4
}
define i32 @test27(i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: @test27(
; CHECK-NEXT: [[T6:%.*]] = icmp eq i32 [[B:%.*]], [[C:%.*]]
; CHECK-NEXT: [[T7:%.*]] = zext i1 [[T6]] to i32
; CHECK-NEXT: ret i32 [[T7]]
;
%t2 = xor i32 %d, %b
%t5 = xor i32 %d, %c
%t6 = icmp eq i32 %t2, %t5
%t7 = zext i1 %t6 to i32
ret i32 %t7
}
define i32 @test28(i32 %indvar) {
; CHECK-LABEL: @test28(
; CHECK-NEXT: [[T214:%.*]] = add i32 [[INDVAR:%.*]], 1
; CHECK-NEXT: ret i32 [[T214]]
;
%t7 = add i32 %indvar, -2147483647
%t214 = xor i32 %t7, -2147483648
ret i32 %t214
}
define <2 x i32> @test28vec(<2 x i32> %indvar) {
; CHECK-LABEL: @test28vec(
; CHECK-NEXT: [[T214:%.*]] = add <2 x i32> [[INDVAR:%.*]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i32> [[T214]]
;
%t7 = add <2 x i32> %indvar, <i32 -2147483647, i32 -2147483647>
%t214 = xor <2 x i32> %t7, <i32 -2147483648, i32 -2147483648>
ret <2 x i32> %t214
}
define i32 @test28_sub(i32 %indvar) {
; CHECK-LABEL: @test28_sub(
; CHECK-NEXT: [[T214:%.*]] = sub i32 1, [[INDVAR:%.*]]
; CHECK-NEXT: ret i32 [[T214]]
;
%t7 = sub i32 -2147483647, %indvar
%t214 = xor i32 %t7, -2147483648
ret i32 %t214
}
define <2 x i32> @test28_subvec(<2 x i32> %indvar) {
; CHECK-LABEL: @test28_subvec(
; CHECK-NEXT: [[T214:%.*]] = sub <2 x i32> <i32 1, i32 1>, [[INDVAR:%.*]]
; CHECK-NEXT: ret <2 x i32> [[T214]]
;
%t7 = sub <2 x i32> <i32 -2147483647, i32 -2147483647>, %indvar
%t214 = xor <2 x i32> %t7, <i32 -2147483648, i32 -2147483648>
ret <2 x i32> %t214
}
define i32 @test29(i1 %C) {
; CHECK-LABEL: @test29(
; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 915, i32 113
; CHECK-NEXT: ret i32 [[V]]
;
%A = select i1 %C, i32 1000, i32 10
%V = xor i32 %A, 123
ret i32 %V
}
define <2 x i32> @test29vec(i1 %C) {
; CHECK-LABEL: @test29vec(
; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 915, i32 915>, <2 x i32> <i32 113, i32 113>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10>
%V = xor <2 x i32> %A, <i32 123, i32 123>
ret <2 x i32> %V
}
define <2 x i32> @test29vec2(i1 %C) {
; CHECK-LABEL: @test29vec2(
; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 915, i32 2185>, <2 x i32> <i32 113, i32 339>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%A = select i1 %C, <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
%V = xor <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %V
}
define i32 @test30(i1 %which) {
; CHECK-LABEL: @test30(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi i32 [ 915, [[ENTRY:%.*]] ], [ 113, [[DELAY]] ]
; CHECK-NEXT: ret i32 [[A]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi i32 [ 1000, %entry ], [ 10, %delay ]
%value = xor i32 %A, 123
ret i32 %value
}
define <2 x i32> @test30vec(i1 %which) {
; CHECK-LABEL: @test30vec(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 915, i32 915>, [[ENTRY:%.*]] ], [ <i32 113, i32 113>, [[DELAY]] ]
; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 1000>, %entry ], [ <i32 10, i32 10>, %delay ]
%value = xor <2 x i32> %A, <i32 123, i32 123>
ret <2 x i32> %value
}
define <2 x i32> @test30vec2(i1 %which) {
; CHECK-LABEL: @test30vec2(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 915, i32 2185>, [[ENTRY:%.*]] ], [ <i32 113, i32 339>, [[DELAY]] ]
; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 2500>, %entry ], [ <i32 10, i32 30>, %delay ]
%value = xor <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %value
}
; B ^ (B | A) --> A & ~B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @or_xor_commute1(i32 %p1, i32 %p2) {
; CHECK-LABEL: @or_xor_commute1(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = or i32 %b, %a
%r = xor i32 %b, %o
ret i32 %r
}
; B ^ (B | A) --> A & ~B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @or_xor_commute2(i32 %p1, i32 %p2) {
; CHECK-LABEL: @or_xor_commute2(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = or i32 %a, %b
%r = xor i32 %o, %b
ret i32 %r
}
; B ^ (B | A) --> A & ~B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @or_xor_commute3(i32 %p1, i32 %p2) {
; CHECK-LABEL: @or_xor_commute3(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = or i32 %b, %a
%r = xor i32 %o, %b
ret i32 %r
}
; B ^ (B | A) --> A & ~B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @or_xor_commute4(i32 %p1, i32 %p2) {
; CHECK-LABEL: @or_xor_commute4(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = or i32 %a, %b
%r = xor i32 %b, %o
ret i32 %r
}
define i32 @or_xor_extra_use(i32 %a, i32 %b, i32* %p) {
; CHECK-LABEL: @or_xor_extra_use(
; CHECK-NEXT: [[O:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: store i32 [[O]], i32* [[P:%.*]], align 4
; CHECK-NEXT: [[R:%.*]] = xor i32 [[O]], [[B]]
; CHECK-NEXT: ret i32 [[R]]
;
%o = or i32 %a, %b
store i32 %o, i32* %p
%r = xor i32 %b, %o
ret i32 %r
}
; B ^ (B & A) --> ~A & B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @and_xor_commute1(i32 %p1, i32 %p2) {
; CHECK-LABEL: @and_xor_commute1(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[B]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = and i32 %b, %a
%r = xor i32 %b, %o
ret i32 %r
}
; B ^ (B & A) --> ~A & B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @and_xor_commute2(i32 %p1, i32 %p2) {
; CHECK-LABEL: @and_xor_commute2(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[B]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = and i32 %a, %b
%r = xor i32 %o, %b
ret i32 %r
}
; B ^ (B & A) --> ~A & B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @and_xor_commute3(i32 %p1, i32 %p2) {
; CHECK-LABEL: @and_xor_commute3(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[B]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = and i32 %b, %a
%r = xor i32 %o, %b
ret i32 %r
}
; B ^ (B & A) --> ~A & B
; The division ops are here to thwart complexity-based canonicalization: all ops are binops.
define i32 @and_xor_commute4(i32 %p1, i32 %p2) {
; CHECK-LABEL: @and_xor_commute4(
; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[P1:%.*]]
; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[P2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A]], -1
; CHECK-NEXT: [[R:%.*]] = and i32 [[B]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = udiv i32 42, %p1
%b = udiv i32 42, %p2
%o = and i32 %a, %b
%r = xor i32 %b, %o
ret i32 %r
}
define i32 @and_xor_extra_use(i32 %a, i32 %b, i32* %p) {
; CHECK-LABEL: @and_xor_extra_use(
; CHECK-NEXT: [[O:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: store i32 [[O]], i32* [[P:%.*]], align 4
; CHECK-NEXT: [[R:%.*]] = xor i32 [[O]], [[B]]
; CHECK-NEXT: ret i32 [[R]]
;
%o = and i32 %a, %b
store i32 %o, i32* %p
%r = xor i32 %b, %o
ret i32 %r
}
; (~X | C2) ^ C1 --> ((X & ~C2) ^ -1) ^ C1 --> (X & ~C2) ^ ~C1
; The extra use (store) is here because the simpler case
; may be transformed using demanded bits.
define i8 @xor_or_not(i8 %x, i8* %p) {
; CHECK-LABEL: @xor_or_not(
; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
; CHECK-NEXT: store i8 [[NX]], i8* [[P:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X]], -8
; CHECK-NEXT: [[R:%.*]] = xor i8 [[TMP1]], -13
; CHECK-NEXT: ret i8 [[R]]
;
%nx = xor i8 %x, -1
store i8 %nx, i8* %p
%or = or i8 %nx, 7
%r = xor i8 %or, 12
ret i8 %r
}
; Don't do this if the 'or' has extra uses.
define i8 @xor_or_not_uses(i8 %x, i8* %p) {
; CHECK-LABEL: @xor_or_not_uses(
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], 7
; CHECK-NEXT: [[OR:%.*]] = xor i8 [[TMP1]], -8
; CHECK-NEXT: store i8 [[OR]], i8* [[P:%.*]], align 1
; CHECK-NEXT: [[R:%.*]] = xor i8 [[TMP1]], -12
; CHECK-NEXT: ret i8 [[R]]
;
%nx = xor i8 %x, -1
%or = or i8 %nx, 7
store i8 %or, i8* %p
%r = xor i8 %or, 12
ret i8 %r
}
; (~X & C2) ^ C1 --> ((X | ~C2) ^ -1) ^ C1 --> (X | ~C2) ^ ~C1
; The extra use (store) is here because the simpler case
; may be transformed using demanded bits.
define i8 @xor_and_not(i8 %x, i8* %p) {
; CHECK-LABEL: @xor_and_not(
; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
; CHECK-NEXT: store i8 [[NX]], i8* [[P:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X]], -43
; CHECK-NEXT: [[R:%.*]] = xor i8 [[TMP1]], -32
; CHECK-NEXT: ret i8 [[R]]
;
%nx = xor i8 %x, -1
store i8 %nx, i8* %p
%and = and i8 %nx, 42
%r = xor i8 %and, 31
ret i8 %r
}
; Don't do this if the 'and' has extra uses.
define i8 @xor_and_not_uses(i8 %x, i8* %p) {
; CHECK-LABEL: @xor_and_not_uses(
; CHECK-NEXT: [[NX:%.*]] = and i8 [[X:%.*]], 42
; CHECK-NEXT: [[AND:%.*]] = xor i8 [[NX]], 42
; CHECK-NEXT: store i8 [[AND]], i8* [[P:%.*]], align 1
; CHECK-NEXT: [[R:%.*]] = xor i8 [[NX]], 53
; CHECK-NEXT: ret i8 [[R]]
;
%nx = xor i8 %x, -1
%and = and i8 %nx, 42
store i8 %and, i8* %p
%r = xor i8 %and, 31
ret i8 %r
}
; The tests 39-47 are related to the canonicalization:
; %notx = xor i32 %x, -1
; %cmp = icmp sgt i32 %notx, %y
; %smax = select i1 %cmp, i32 %notx, i32 %y
; %res = xor i32 %smax, -1
; =>
; %noty = xor i32 %y, -1
; %cmp2 = icmp slt %x, %noty
; %res = select i1 %cmp2, i32 %x, i32 %noty
;
; Same transformations is valid for smin/umax/umin.
define i32 @test39(i32 %x) {
; CHECK-LABEL: @test39(
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 255
; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 255
; CHECK-NEXT: ret i32 [[RES]]
;
%1 = xor i32 %x, -1
%2 = icmp sgt i32 %1, -256
%3 = select i1 %2, i32 %1, i32 -256
%res = xor i32 %3, -1
ret i32 %res
}
define i32 @test40(i32 %x, i32 %y) {
; CHECK-LABEL: @test40(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP2]], i32 [[X]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp sgt i32 %notx, %y
%smax = select i1 %cmp1, i32 %notx, i32 %y
%res = xor i32 %smax, -1
ret i32 %res
}
define i32 @test41(i32 %x, i32 %y) {
; CHECK-LABEL: @test41(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP2]], i32 [[X]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp slt i32 %notx, %y
%smin = select i1 %cmp1, i32 %notx, i32 %y
%res = xor i32 %smin, -1
ret i32 %res
}
define i32 @test42(i32 %x, i32 %y) {
; CHECK-LABEL: @test42(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP2]], i32 [[X]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp ugt i32 %notx, %y
%umax = select i1 %cmp1, i32 %notx, i32 %y
%res = xor i32 %umax, -1
ret i32 %res
}
define i32 @test43(i32 %x, i32 %y) {
; CHECK-LABEL: @test43(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP2]], i32 [[X]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp ult i32 %notx, %y
%umin = select i1 %cmp1, i32 %notx, i32 %y
%res = xor i32 %umin, -1
ret i32 %res
}
define i32 @test44(i32 %x, i32 %y) {
; CHECK-LABEL: @test44(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 -4, [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[X]]
; CHECK-NEXT: ret i32 [[RES]]
;
%z = add i32 %y, 3 ; thwart complexity-based canonicalization
%notx = xor i32 %x, -1
%cmp1 = icmp ult i32 %z, %notx
%umin = select i1 %cmp1, i32 %z, i32 %notx
%res = xor i32 %umin, -1
ret i32 %res
}
define i32 @test45(i32 %x, i32 %y) {
; CHECK-LABEL: @test45(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[Y]], i32 [[X]]
; CHECK-NEXT: ret i32 [[TMP2]]
;
%z = xor i32 %y, -1
%notx = xor i32 %x, -1
%cmp1 = icmp ult i32 %z, %notx
%umin = select i1 %cmp1, i32 %z, i32 %notx
%res = xor i32 %umin, -1
ret i32 %res
}
; Check that we work with splat vectors also.
define <4 x i32> @test46(<4 x i32> %x) {
; CHECK-LABEL: @test46(
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[X:%.*]], <i32 255, i32 255, i32 255, i32 255>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> <i32 255, i32 255, i32 255, i32 255>
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%1 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%2 = icmp sgt <4 x i32> %1, <i32 -256, i32 -256, i32 -256, i32 -256>
%3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 -256, i32 -256, i32 -256, i32 -256>
%4 = xor <4 x i32> %3, <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %4
}
; Test case when select pattern has more than one use.
define i32 @test47(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @test47(
; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X:%.*]], -1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[NOTX]], [[Y:%.*]]
; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[CMP1]], i32 [[NOTX]], i32 [[Y]]
; CHECK-NEXT: [[UMIN:%.*]] = xor i32 [[UMAX]], -1
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[UMAX]], [[Z:%.*]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[ADD]], [[UMIN]]
; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp ugt i32 %notx, %y
%umax = select i1 %cmp1, i32 %notx, i32 %y
%umin = xor i32 %umax, -1
%add = add i32 %umax, %z
%res = mul i32 %umin, %add
ret i32 %res
}
define i32 @test48(i32 %x) {
; CHECK-LABEL: @test48(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], -1
; CHECK-NEXT: [[D:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 -1
; CHECK-NEXT: ret i32 [[D]]
;
%a = sub i32 -2, %x
%b = icmp sgt i32 %a, 0
%c = select i1 %b, i32 %a, i32 0
%d = xor i32 %c, -1
ret i32 %d
}
define <2 x i32> @test48vec(<2 x i32> %x) {
; CHECK-LABEL: @test48vec(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[TMP1]], <i32 -1, i32 -1>
; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP1]], <2 x i32> <i32 -1, i32 -1>
; CHECK-NEXT: ret <2 x i32> [[D]]
;
%a = sub <2 x i32> <i32 -2, i32 -2>, %x
%b = icmp sgt <2 x i32> %a, zeroinitializer
%c = select <2 x i1> %b, <2 x i32> %a, <2 x i32> zeroinitializer
%d = xor <2 x i32> %c, <i32 -1, i32 -1>
ret <2 x i32> %d
}
define i32 @test49(i32 %x) {
; CHECK-LABEL: @test49(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 1, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], 0
; CHECK-NEXT: [[D:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0
; CHECK-NEXT: ret i32 [[D]]
;
%a = add i32 %x, -2
%b = icmp slt i32 %a, -1
%c = select i1 %b, i32 %a, i32 -1
%d = xor i32 %c, -1
ret i32 %d
}
define <2 x i32> @test49vec(<2 x i32> %x) {
; CHECK-LABEL: @test49vec(
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> <i32 1, i32 1>, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <2 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP1]], <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[D]]
;
%a = add <2 x i32> %x, <i32 -2, i32 -2>
%b = icmp slt <2 x i32> %a, <i32 -1, i32 -1>
%c = select <2 x i1> %b, <2 x i32> %a, <2 x i32> <i32 -1, i32 -1>
%d = xor <2 x i32> %c, <i32 -1, i32 -1>
ret <2 x i32> %d
}
define i32 @test50(i32 %x, i32 %y) {
; CHECK-LABEL: @test50(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 1, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[Y:%.*]], 1
; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: [[E:%.*]] = select i1 [[TMP3]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[E]]
;
%a = add i32 %x, -2
%b = sub i32 -2, %y
%c = icmp slt i32 %a, %b
%d = select i1 %c, i32 %a, i32 %b
%e = xor i32 %d, -1
ret i32 %e
}
define <2 x i32> @test50vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @test50vec(
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> <i32 1, i32 1>, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[TMP2]], [[TMP1]]
; CHECK-NEXT: [[E:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]]
; CHECK-NEXT: ret <2 x i32> [[E]]
;
%a = add <2 x i32> %x, <i32 -2, i32 -2>
%b = sub <2 x i32> <i32 -2, i32 -2>, %y
%c = icmp slt <2 x i32> %a, %b
%d = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
%e = xor <2 x i32> %d, <i32 -1, i32 -1>
ret <2 x i32> %e
}
define i32 @test51(i32 %x, i32 %y) {
; CHECK-LABEL: @test51(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 -3, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[Y:%.*]], -3
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: [[E:%.*]] = select i1 [[TMP3]], i32 [[TMP1]], i32 [[TMP2]]
; CHECK-NEXT: ret i32 [[E]]
;
%a = add i32 %x, 2
%b = sub i32 2, %y
%c = icmp sgt i32 %a, %b
%d = select i1 %c, i32 %a, i32 %b
%e = xor i32 %d, -1
ret i32 %e
}
define <2 x i32> @test51vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @test51vec(
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> <i32 -3, i32 -3>, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 -3, i32 -3>
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <2 x i32> [[TMP2]], [[TMP1]]
; CHECK-NEXT: [[E:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]]
; CHECK-NEXT: ret <2 x i32> [[E]]
;
%a = add <2 x i32> %x, <i32 2, i32 2>
%b = sub <2 x i32> <i32 2, i32 2>, %y
%c = icmp sgt <2 x i32> %a, %b
%d = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
%e = xor <2 x i32> %d, <i32 -1, i32 -1>
ret <2 x i32> %e
}
| {
"language": "Assembly"
} |
dnl AMD K6 mpn_add/sub_n -- mpn addition or subtraction.
dnl Copyright 1999-2002 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C K6: normal 3.25 cycles/limb, in-place 2.75 cycles/limb.
ifdef(`OPERATION_add_n', `
define(M4_inst, adcl)
define(M4_function_n, mpn_add_n)
define(M4_function_nc, mpn_add_nc)
define(M4_description, add)
',`ifdef(`OPERATION_sub_n', `
define(M4_inst, sbbl)
define(M4_function_n, mpn_sub_n)
define(M4_function_nc, mpn_sub_nc)
define(M4_description, subtract)
',`m4_error(`Need OPERATION_add_n or OPERATION_sub_n
')')')
MULFUNC_PROLOGUE(mpn_add_n mpn_add_nc mpn_sub_n mpn_sub_nc)
C mp_limb_t M4_function_n (mp_ptr dst, mp_srcptr src1, mp_srcptr src2,
C mp_size_t size);
C mp_limb_t M4_function_nc (mp_ptr dst, mp_srcptr src1, mp_srcptr src2,
C mp_size_t size, mp_limb_t carry);
C
C Calculate src1,size M4_description src2,size, and store the result in
C dst,size. The return value is the carry bit from the top of the result
C (1 or 0).
C
C The _nc version accepts 1 or 0 for an initial carry into the low limb of
C the calculation. Note values other than 1 or 0 here will lead to garbage
C results.
C
C Instruction decoding limits a normal dst=src1+src2 operation to 3 c/l, and
C an in-place dst+=src to 2.5 c/l. The unrolled loops have 1 cycle/loop of
C loop control, which with 4 limbs/loop means an extra 0.25 c/l.
define(PARAM_CARRY, `FRAME+20(%esp)')
define(PARAM_SIZE, `FRAME+16(%esp)')
define(PARAM_SRC2, `FRAME+12(%esp)')
define(PARAM_SRC1, `FRAME+8(%esp)')
define(PARAM_DST, `FRAME+4(%esp)')
deflit(`FRAME',0)
dnl minimum 5 because the unrolled code can't handle less
deflit(UNROLL_THRESHOLD, 5)
TEXT
ALIGN(32)
PROLOGUE(M4_function_nc)
movl PARAM_CARRY, %eax
jmp L(start)
EPILOGUE()
PROLOGUE(M4_function_n)
xorl %eax, %eax
L(start):
movl PARAM_SIZE, %ecx
pushl %ebx
FRAME_pushl()
movl PARAM_SRC1, %ebx
pushl %edi
FRAME_pushl()
movl PARAM_SRC2, %edx
cmpl $UNROLL_THRESHOLD, %ecx
movl PARAM_DST, %edi
jae L(unroll)
shrl %eax C initial carry flag
C offset 0x21 here, close enough to aligned
L(simple):
C eax scratch
C ebx src1
C ecx counter
C edx src2
C esi
C edi dst
C ebp
C
C The store to (%edi) could be done with a stosl; it'd be smaller
C code, but there's no speed gain and a cld would have to be added
C (per mpn/x86/README).
movl (%ebx), %eax
leal 4(%ebx), %ebx
M4_inst (%edx), %eax
movl %eax, (%edi)
leal 4(%edi), %edi
leal 4(%edx), %edx
loop L(simple)
movl $0, %eax
popl %edi
setc %al
popl %ebx
ret
C -----------------------------------------------------------------------------
L(unroll):
C eax carry
C ebx src1
C ecx counter
C edx src2
C esi
C edi dst
C ebp
cmpl %edi, %ebx
pushl %esi
je L(inplace)
ifdef(`OPERATION_add_n',`
cmpl %edi, %edx
je L(inplace_reverse)
')
movl %ecx, %esi
andl $-4, %ecx
andl $3, %esi
leal (%ebx,%ecx,4), %ebx
leal (%edx,%ecx,4), %edx
leal (%edi,%ecx,4), %edi
negl %ecx
shrl %eax
ALIGN(32)
L(normal_top):
C eax counter, qwords, negative
C ebx src1
C ecx scratch
C edx src2
C esi
C edi dst
C ebp
movl (%ebx,%ecx,4), %eax
leal 5(%ecx), %ecx
M4_inst -20(%edx,%ecx,4), %eax
movl %eax, -20(%edi,%ecx,4)
movl 4-20(%ebx,%ecx,4), %eax
M4_inst 4-20(%edx,%ecx,4), %eax
movl %eax, 4-20(%edi,%ecx,4)
movl 8-20(%ebx,%ecx,4), %eax
M4_inst 8-20(%edx,%ecx,4), %eax
movl %eax, 8-20(%edi,%ecx,4)
movl 12-20(%ebx,%ecx,4), %eax
M4_inst 12-20(%edx,%ecx,4), %eax
movl %eax, 12-20(%edi,%ecx,4)
loop L(normal_top)
decl %esi
jz L(normal_finish_one)
js L(normal_done)
C two or three more limbs
movl (%ebx), %eax
M4_inst (%edx), %eax
movl %eax, (%edi)
movl 4(%ebx), %eax
M4_inst 4(%edx), %eax
decl %esi
movl %eax, 4(%edi)
jz L(normal_done)
movl $2, %ecx
L(normal_finish_one):
movl (%ebx,%ecx,4), %eax
M4_inst (%edx,%ecx,4), %eax
movl %eax, (%edi,%ecx,4)
L(normal_done):
popl %esi
popl %edi
movl $0, %eax
popl %ebx
setc %al
ret
C -----------------------------------------------------------------------------
ifdef(`OPERATION_add_n',`
L(inplace_reverse):
C dst==src2
movl %ebx, %edx
')
L(inplace):
C eax initial carry
C ebx
C ecx size
C edx src
C esi
C edi dst
C ebp
leal -1(%ecx), %esi
decl %ecx
andl $-4, %ecx
andl $3, %esi
movl (%edx), %ebx C src low limb
leal (%edx,%ecx,4), %edx
leal (%edi,%ecx,4), %edi
negl %ecx
shrl %eax
ALIGN(32)
L(inplace_top):
C eax
C ebx next src limb
C ecx size
C edx src
C esi
C edi dst
C ebp
M4_inst %ebx, (%edi,%ecx,4)
movl 4(%edx,%ecx,4), %eax
leal 5(%ecx), %ecx
M4_inst %eax, 4-20(%edi,%ecx,4)
movl 8-20(%edx,%ecx,4), %eax
movl 12-20(%edx,%ecx,4), %ebx
M4_inst %eax, 8-20(%edi,%ecx,4)
M4_inst %ebx, 12-20(%edi,%ecx,4)
movl 16-20(%edx,%ecx,4), %ebx
loop L(inplace_top)
C now %esi is 0 to 3 representing respectively 1 to 4 limbs more
M4_inst %ebx, (%edi)
decl %esi
jz L(inplace_finish_one)
js L(inplace_done)
C two or three more limbs
movl 4(%edx), %eax
movl 8(%edx), %ebx
M4_inst %eax, 4(%edi)
M4_inst %ebx, 8(%edi)
decl %esi
movl $2, %ecx
jz L(normal_done)
L(inplace_finish_one):
movl 4(%edx,%ecx,4), %eax
M4_inst %eax, 4(%edi,%ecx,4)
L(inplace_done):
popl %esi
popl %edi
movl $0, %eax
popl %ebx
setc %al
ret
EPILOGUE()
| {
"language": "Assembly"
} |
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build linux
// +build mips64 mips64le
// +build !gccgo
#include "textflag.h"
//
// System calls for mips64, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
JAL runtime·entersyscall(SB)
MOVV a1+8(FP), R4
MOVV a2+16(FP), R5
MOVV a3+24(FP), R6
MOVV R0, R7
MOVV R0, R8
MOVV R0, R9
MOVV trap+0(FP), R2 // syscall entry
SYSCALL
MOVV R2, r1+32(FP)
MOVV R3, r2+40(FP)
JAL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVV a1+8(FP), R4
MOVV a2+16(FP), R5
MOVV a3+24(FP), R6
MOVV R0, R7
MOVV R0, R8
MOVV R0, R9
MOVV trap+0(FP), R2 // syscall entry
SYSCALL
MOVV R2, r1+32(FP)
MOVV R3, r2+40(FP)
RET
| {
"language": "Assembly"
} |
.globl main
.globl Cmm.global_area
.globl Cmm.globalsig.aQOYZWMPACZAJaMABGMOZeCCPY
.section .data
/* memory for global registers */
Cmm.globalsig.aQOYZWMPACZAJaMABGMOZeCCPY:
Cmm.global_area:
.globl Cmm_stack_growth
.section .data
.align 4
Cmm_stack_growth:
.long 0xffffffff
.section .text
main:
leal -8(%esp), %esp
leal 8(%esp), %eax
movl (%eax),%eax
movl %eax,4(%esp)
.Linitialize_continuations_l3:
.Lproc_body_start_l2:
movl $0,%ecx
leal 8(%esp), %eax
movl $-8,%edx
addl %edx,%eax
movl %ecx,(%eax)
call exit
.Lcall_successor_l6:
int $3
.section .pcmap_data
.Lstackdata_l13:
.long 0
.section .pcmap
.long .Lcall_successor_l6
.long .Lframe_l14
.section .pcmap_data
.Lframe_l14:
.long 0x80000004
.long 0xfffffff8
.long 0xfffffffc
.long .Lstackdata_l13
.long 4
.long 0
.long 0
.long 1
.long 11
.long 0
.long 10
.long 0
.long 9
.long 0
.long 7
.long 0
.long 0
.section .text
| {
"language": "Assembly"
} |
#
# Copyright (c) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <abi/asmtool.h>
#include <arch/arch.h>
#include <arch/regname.h>
.macro SMC_COHERENCY addr
dcbst 0, \addr
sync
icbi 0, \addr
sync
isync
.endm
.macro FLUSH_DCACHE addr
dcbst 0, \addr
sync
isync
.endm
.macro TLB_FLUSH reg
li \reg, 0
sync
.rept 64
tlbie \reg
addi \reg, \reg, 0x1000
.endr
eieio
tlbsync
sync
.endm
.macro BAT_COMPUTE base size mask lower upper
# less than 128 KB -> no BAT
lis \upper, 0x0002
cmpw \size, \upper
blt no_bat
# mask = total >> 18
li \upper, 18
srw \mask, \size, \upper
# create Block Length mask by replicating
# the leading logical one 14 times
li \upper, 14
mtctr \mask
li \upper, 1
0:
# mask = (mask >> 1) | mask
srw \lower, \mask, \upper
or \mask, \mask, \lower
bdnz 0b
# mask = mask & 0x07ff
# (BAT can map up to 256 MB)
andi. \mask, \mask, 0x07ff
# mask = (mask << 2) | 0x0002
# (priviledged access only)
li \upper, 2
slw \mask, \mask, \upper
ori \mask, \mask, 0x0002
lis \upper, (0x8000 + \base)
or \upper, \upper, \mask
lis \lower, \base
ori \lower, \lower, 0x0002
.endm
.section BOOTSTRAP, "ax"
SYMBOL(start)
lis r4, ofw_cif@ha
addi r4, r4, ofw_cif@l
stw r5, 0(r4)
bl ofw_init
b bootstrap
.text
FUNCTION_BEGIN(halt)
b halt
FUNCTION_END(halt)
FUNCTION_BEGIN(jump_to_kernel)
# arguments:
# r3 = bootinfo (physical address)
# r4 = translate table (physical address)
# r5 = pages to translate
# r6 = real mode meeting point (physical address)
# r7 = kernel entry point (virtual address in kernel's address space)
# disable interrupts
mfmsr r31
rlwinm r31, r31, 0, 17, 15
mtmsr r31
# set real mode meeting point physical address
mtspr srr0, r6
# jump to real_mode
mfmsr r31
lis r30, ~0@h
ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
and r31, r31, r30
mtspr srr1, r31
sync
isync
rfi
FUNCTION_END(jump_to_kernel)
SYMBOL(real_mode)
# arguments:
# r3 = bootinfo (physical address)
# r4 = translate table (physical address)
# r5 = pages to translate
# r7 = kernel entry point (virtual address in kernel's address space)
# move the images of components to the proper
# location using the translate table
li r31, PAGE_SIZE >> 2
li r30, 0
page_copy:
cmpwi r5, 0
beq copy_end
mtctr r31
lwz r29, 0(r4)
copy_loop:
lwz r28, 0(r29)
stw r28, 0(r30)
SMC_COHERENCY r30
addi r29, r29, 4
addi r30, r30, 4
bdnz copy_loop
addi r4, r4, 4
subi r5, r5, 1
b page_copy
copy_end:
# initially fill segment registers
li r31, 0
li r29, 8
mtctr r29
li r30, 0 # ASID 0 (VSIDs 0 .. 7)
seg_fill_uspace:
mtsrin r30, r31
addi r30, r30, 1
addis r31, r31, 0x1000 # move to next SR
bdnz seg_fill_uspace
li r29, 8
mtctr r29
lis r30, 0x4000 # priviledged access only
ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
seg_fill_kernel:
mtsrin r30, r31
addi r30, r30, 1
addis r31, r31, 0x1000 # move to next SR
bdnz seg_fill_kernel
# invalidate block address translation registers
li r30, 0
mtspr ibat0u, r30
mtspr ibat0l, r30
mtspr ibat1u, r30
mtspr ibat1l, r30
mtspr ibat2u, r30
mtspr ibat2l, r30
mtspr ibat3u, r30
mtspr ibat3l, r30
mtspr dbat0u, r30
mtspr dbat0l, r30
mtspr dbat1u, r30
mtspr dbat1l, r30
mtspr dbat2u, r30
mtspr dbat2l, r30
mtspr dbat3u, r30
mtspr dbat3l, r30
# create empty Page Hash Table
# on top of memory, size 64 KB
lwz r31, 4(r3) # r31 = memory size
lis r30, 65536@h
ori r30, r30, 65536@l # r30 = 65536
subi r29, r30, 1 # r29 = 65535
sub r31, r31, r30
andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
mtsdr1 r31
li r29, 2
srw r30, r30, r29 # r30 = 16384
li r29, 0
pht_clear:
# write zeroes
stw r29, 0(r31)
FLUSH_DCACHE r31
addi r31, r31, 4
subi r30, r30, 4
cmpwi r30, 0
beq clear_end
bdnz pht_clear
clear_end:
# create BAT identity mapping
lwz r31, 4(r3) # r31 = memory size
lis r30, 268435456@h
ori r30, r30, 268435456@l # r30 = 256 MB
# BAT0
# r29 = min(r31, r30)
cmpw r31, r30
blt bat0_r31
mr r29, r30
b bat0_r30
bat0_r31:
mr r29, r31
bat0_r30:
BAT_COMPUTE 0x0000 r29 r28 r27 r26
mtspr ibat0u, r26
mtspr ibat0l, r27
mtspr dbat0u, r26
mtspr dbat0l, r27
# BAT1
sub r31, r31, r29 # r31 = r31 - r29
# r29 = min(r31, r30)
cmpw r31, r30
blt bat1_r31
mr r29, r30
b bat1_r30
bat1_r31:
mr r29, r31
bat1_r30:
BAT_COMPUTE 0x1000 r29 r28 r27 r26
mtspr ibat1u, r26
mtspr ibat1l, r27
mtspr dbat1u, r26
mtspr dbat1l, r27
# BAT2
sub r31, r31, r29 # r31 = r31 - r29
# r29 = min(r31, r30)
cmpw r31, r30
blt bat2_r31
mr r29, r30
b bat2_r30
bat2_r31:
mr r29, r31
bat2_r30:
BAT_COMPUTE 0x2000 r29 r28 r27 r26
mtspr ibat2u, r26
mtspr ibat2l, r27
mtspr dbat2u, r26
mtspr dbat2l, r27
# BAT3
sub r31, r31, r29 # r31 = r31 - r29
# r29 = min(r31, r30)
cmpw r31, r30
blt bat3_r31
mr r29, r30
b bat3_r30
bat3_r31:
mr r29, r31
bat3_r30:
BAT_COMPUTE 0x3000 r29 r28 r27 r26
mtspr ibat3u, r26
mtspr ibat3l, r27
mtspr dbat3u, r26
mtspr dbat3l, r27
no_bat:
# flush TLB
TLB_FLUSH r31
# start the kernel
#
# pc = kernel's entry point (r7)
# r3 = bootinfo (physical address)
# sprg3 = physical memory size
# sp = 0 (enforces the usage of sprg0 as exception stack)
mtspr srr0, r7
# Clear sprg0. Kernel will set it.
li r31, 0
mtsprg0 r31
# bootinfo starts with a 64 bit integer containing
# the physical memory size, get the lower 4 bytes
// FIXME: unchecked magic offset
lwz r31, 4(r3)
mtsprg3 r31
li sp, 0
mfmsr r31
ori r31, r31, (msr_ir | msr_dr)@l
mtspr srr1, r31
sync
isync
rfi
| {
"language": "Assembly"
} |
charset_map koi8-r windows-1251 {
80 88 ; # euro
95 95 ; # bullet
9A A0 ; #
9E B7 ; # ·
A3 B8 ; # small yo
A4 BA ; # small Ukrainian ye
A6 B3 ; # small Ukrainian i
A7 BF ; # small Ukrainian yi
AD B4 ; # small Ukrainian soft g
AE A2 ; # small Byelorussian short u
B0 B0 ; # °
B3 A8 ; # capital YO
B4 AA ; # capital Ukrainian YE
B6 B2 ; # capital Ukrainian I
B7 AF ; # capital Ukrainian YI
B9 B9 ; # numero sign
BD A5 ; # capital Ukrainian soft G
BE A1 ; # capital Byelorussian short U
BF A9 ; # (C)
C0 FE ; # small yu
C1 E0 ; # small a
C2 E1 ; # small b
C3 F6 ; # small ts
C4 E4 ; # small d
C5 E5 ; # small ye
C6 F4 ; # small f
C7 E3 ; # small g
C8 F5 ; # small kh
C9 E8 ; # small i
CA E9 ; # small j
CB EA ; # small k
CC EB ; # small l
CD EC ; # small m
CE ED ; # small n
CF EE ; # small o
D0 EF ; # small p
D1 FF ; # small ya
D2 F0 ; # small r
D3 F1 ; # small s
D4 F2 ; # small t
D5 F3 ; # small u
D6 E6 ; # small zh
D7 E2 ; # small v
D8 FC ; # small soft sign
D9 FB ; # small y
DA E7 ; # small z
DB F8 ; # small sh
DC FD ; # small e
DD F9 ; # small shch
DE F7 ; # small ch
DF FA ; # small hard sign
E0 DE ; # capital YU
E1 C0 ; # capital A
E2 C1 ; # capital B
E3 D6 ; # capital TS
E4 C4 ; # capital D
E5 C5 ; # capital YE
E6 D4 ; # capital F
E7 C3 ; # capital G
E8 D5 ; # capital KH
E9 C8 ; # capital I
EA C9 ; # capital J
EB CA ; # capital K
EC CB ; # capital L
ED CC ; # capital M
EE CD ; # capital N
EF CE ; # capital O
F0 CF ; # capital P
F1 DF ; # capital YA
F2 D0 ; # capital R
F3 D1 ; # capital S
F4 D2 ; # capital T
F5 D3 ; # capital U
F6 C6 ; # capital ZH
F7 C2 ; # capital V
F8 DC ; # capital soft sign
F9 DB ; # capital Y
FA C7 ; # capital Z
FB D8 ; # capital SH
FC DD ; # capital E
FD D9 ; # capital SHCH
FE D7 ; # capital CH
FF DA ; # capital hard sign
}
| {
"language": "Assembly"
} |
//Original:/testcases/core/c_dsp32alu_search/c_dsp32alu_search.dsp
// Spec Reference: dsp32alu search
# mach: bfin
.include "testutils.inc"
start
imm32 p0, 0x11234556;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
( R0 , R1 ) = SEARCH R2 (GE);
( R2 , R3 ) = SEARCH R4 (GT);
( R4 , R5 ) = SEARCH R0 (LE);
( R7 , R6 ) = SEARCH R1 (LT);
CHECKREG r0, 0x11234556;
CHECKREG r1, 0x11234556;
CHECKREG r2, 0x11234556;
CHECKREG r3, 0x46667717;
CHECKREG r4, 0x11234556;
CHECKREG r5, 0x11234556;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x86667777;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
( R2 , R1 ) = SEARCH R3 (LE);
( R6 , R3 ) = SEARCH R5 (GT);
( R4 , R7 ) = SEARCH R2 (GE);
( R0 , R5 ) = SEARCH R4 (LT);
CHECKREG r0, 0x11234556;
CHECKREG r1, 0x6689ABCD;
CHECKREG r2, 0x47445555;
CHECKREG r3, 0x68667777;
CHECKREG r4, 0x11234556;
CHECKREG r5, 0x11234556;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x11234556;
imm32 r0, 0x516789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x73445555;
imm32 r3, 0x84667777;
imm32 r0, 0x956789ab;
imm32 r1, 0xa689abcd;
imm32 r2, 0xb7445555;
imm32 r3, 0xc86def77;
( R3 , R4 ) = SEARCH R5 (GT);
( R0 , R7 ) = SEARCH R6 (GE);
( R6 , R1 ) = SEARCH R2 (LT);
( R2 , R5 ) = SEARCH R4 (LE);
CHECKREG r0, 0x11234556;
CHECKREG r1, 0xA689ABCD;
CHECKREG r2, 0xB7445555;
CHECKREG r3, 0xC86DEF77;
CHECKREG r4, 0x11234556;
CHECKREG r5, 0x11234556;
CHECKREG r6, 0x11234556;
CHECKREG r7, 0x11234556;
pass
| {
"language": "Assembly"
} |
comment "qt5virtualkeyboard needs an OpenGL-capable backend"
depends on BR2_PACKAGE_QT5_JSCORE_AVAILABLE
depends on !BR2_PACKAGE_QT5_GL_AVAILABLE
config BR2_PACKAGE_QT5VIRTUALKEYBOARD
bool "qt5virtualkeyboard"
depends on BR2_PACKAGE_QT5_JSCORE_AVAILABLE # qt5declarative
depends on BR2_PACKAGE_QT5_GL_AVAILABLE || BR2_PACKAGE_QT5_VERSION_LATEST # qt5declarative/quick
select BR2_PACKAGE_QT5DECLARATIVE
select BR2_PACKAGE_QT5DECLARATIVE_QUICK
select BR2_PACKAGE_QT5SVG
help
Qt Virtual Keyboard is a virtual keyboard framework that
consists of a C++ backend supporting custom input methods as
well as a UI frontend implemented in QML.
if BR2_PACKAGE_QT5VIRTUALKEYBOARD
config BR2_PACKAGE_QT5VIRTUALKEYBOARD_LANGUAGE_LAYOUTS
string "language layouts"
default "en_GB"
help
The Virtual Keyboard supports the following languages:
- Arabic (ar_AR)
- Danish (da_DK)
- English (en_GB)
- Finnish (fi_FI)
- French (fr_FR)
- German (de_DE)
- Hindi (hi_IN)
- Italian (it_IT)
- Japanese (ja_JP)
- Korean (ko_KR)
- Norwegian (nb_NO)
- Persian/Farsi (fa_FA)
- Polish (pl_PL)
- Portugese (pt_PT)
- Romanian (ro_RO)
- Russian (ru_RU)
- Simplified Chinese (zh_CN)
- Traditional Chinese (zh_TW)
- Spanish (es_ES)
- Swedish (sv_SE)
Note: the special value "all" can be used to install support
for all supported languages.
config BR2_PACKAGE_QT5VIRTUALKEYBOARD_HANDWRITING
bool "handwriting"
help
Handwriting support, with gestures for fullscreen input.
Lipi Toolkit (LipiTk) is an open source toolkit for online
Handwriting Recognition.
config BR2_PACKAGE_QT5VIRTUALKEYBOARD_ARROW_KEY_NAVIGATION
bool "Arrow key navigation"
help
Allows controlling the keyboard using the arrow and return
keys.
endif
| {
"language": "Assembly"
} |
/*
* linux/arch/arm/mm/cache-fa.S
*
* Copyright (C) 2005 Faraday Corp.
* Copyright (C) 2008-2009 Paulius Zaleckas <[email protected]>
*
* Based on cache-v4wb.S:
* Copyright (C) 1997-2002 Russell king
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Processors: FA520 FA526 FA626
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/memory.h>
#include <asm/page.h>
#include "proc-macros.S"
/*
* The size of one data cache line.
*/
#define CACHE_DLINESIZE 16
/*
* The total size of the data cache.
*/
#ifdef CONFIG_ARCH_GEMINI
#define CACHE_DSIZE 8192
#else
#define CACHE_DSIZE 16384
#endif
/* FIXME: put optimal value here. Current one is just estimation */
#define CACHE_DLIMIT (CACHE_DSIZE * 2)
/*
* flush_icache_all()
*
* Unconditionally clean and invalidate the entire icache.
*/
ENTRY(fa_flush_icache_all)
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mov pc, lr
ENDPROC(fa_flush_icache_all)
/*
* flush_user_cache_all()
*
* Clean and invalidate all cache entries in a particular address
* space.
*/
ENTRY(fa_flush_user_cache_all)
/* FALLTHROUGH */
/*
* flush_kern_cache_all()
*
* Clean and invalidate the entire cache.
*/
ENTRY(fa_flush_kern_cache_all)
mov ip, #0
mov r2, #VM_EXEC
__flush_whole_cache:
mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
tst r2, #VM_EXEC
mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
mov pc, lr
/*
* flush_user_cache_range(start, end, flags)
*
* Invalidate a range of cache entries in the specified
* address space.
*
* - start - start address (inclusive, page aligned)
* - end - end address (exclusive, page aligned)
* - flags - vma_area_struct flags describing address space
*/
ENTRY(fa_flush_user_cache_range)
mov ip, #0
sub r3, r1, r0 @ calculate total size
cmp r3, #CACHE_DLIMIT @ total size >= limit?
bhs __flush_whole_cache @ flush whole D cache
1: tst r2, #VM_EXEC
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
tst r2, #VM_EXEC
mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
mov pc, lr
/*
* coherent_kern_range(start, end)
*
* Ensure coherency between the Icache and the Dcache in the
* region described by start. If you have non-snooping
* Harvard caches, you need to implement this function.
*
* - start - virtual start address
* - end - virtual end address
*/
ENTRY(fa_coherent_kern_range)
/* fall through */
/*
* coherent_user_range(start, end)
*
* Ensure coherency between the Icache and the Dcache in the
* region described by start. If you have non-snooping
* Harvard caches, you need to implement this function.
*
* - start - virtual start address
* - end - virtual end address
*/
ENTRY(fa_coherent_user_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
mov pc, lr
/*
* flush_kern_dcache_area(void *addr, size_t size)
*
* Ensure that the data held in the page kaddr is written back
* to the page in question.
*
* - addr - kernel address
* - size - size of region
*/
ENTRY(fa_flush_kern_dcache_area)
add r1, r0, r1
1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
/*
* dma_inv_range(start, end)
*
* Invalidate (discard) the specified virtual address range.
* May not write back any entries. If 'start' or 'end'
* are not cache line aligned, those lines must be written
* back.
*
* - start - virtual start address
* - end - virtual end address
*/
fa_dma_inv_range:
tst r0, #CACHE_DLINESIZE - 1
bic r0, r0, #CACHE_DLINESIZE - 1
mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
tst r1, #CACHE_DLINESIZE - 1
bic r1, r1, #CACHE_DLINESIZE - 1
mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
/*
* dma_clean_range(start, end)
*
* Clean (write back) the specified virtual address range.
*
* - start - virtual start address
* - end - virtual end address
*/
fa_dma_clean_range:
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
/*
* dma_flush_range(start,end)
* - start - virtual start address of region
* - end - virtual end address of region
*/
ENTRY(fa_dma_flush_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
/*
* dma_map_area(start, size, dir)
* - start - kernel virtual start address
* - size - size of region
* - dir - DMA direction
*/
ENTRY(fa_dma_map_area)
add r1, r1, r0
cmp r2, #DMA_TO_DEVICE
beq fa_dma_clean_range
bcs fa_dma_inv_range
b fa_dma_flush_range
ENDPROC(fa_dma_map_area)
/*
* dma_unmap_area(start, size, dir)
* - start - kernel virtual start address
* - size - size of region
* - dir - DMA direction
*/
ENTRY(fa_dma_unmap_area)
mov pc, lr
ENDPROC(fa_dma_unmap_area)
.globl fa_flush_kern_cache_louis
.equ fa_flush_kern_cache_louis, fa_flush_kern_cache_all
__INITDATA
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions fa
| {
"language": "Assembly"
} |
/*
Copyright (c) 2013 Andes Technology Corporation.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of the company may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.text
.global _getpid
.type _getpid, @function
.align 2
_getpid:
/* The getpid() function shall always be successful and
no return value is reserved to indicate an error. */
movi $r0, 1 /* A minimal implementation, success. */
ret
.size _getpid, .-_getpid
| {
"language": "Assembly"
} |
/*
Copyright Rene Rivera 2008-2015
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
#ifndef BOOST_PREDEF_ARCHITECTURE_X86_64_H
#define BOOST_PREDEF_ARCHITECTURE_X86_64_H
#include <boost/predef/version_number.h>
#include <boost/predef/make.h>
/*`
[heading `BOOST_ARCH_X86_64`]
[@http://en.wikipedia.org/wiki/Ia64 Intel IA-64] architecture.
[table
[[__predef_symbol__] [__predef_version__]]
[[`__x86_64`] [__predef_detection__]]
[[`__x86_64__`] [__predef_detection__]]
[[`__amd64__`] [__predef_detection__]]
[[`__amd64`] [__predef_detection__]]
[[`_M_X64`] [__predef_detection__]]
]
*/
#define BOOST_ARCH_X86_64 BOOST_VERSION_NUMBER_NOT_AVAILABLE
#if defined(__x86_64) || defined(__x86_64__) || \
defined(__amd64__) || defined(__amd64) || \
defined(_M_X64)
# undef BOOST_ARCH_X86_64
# define BOOST_ARCH_X86_64 BOOST_VERSION_NUMBER_AVAILABLE
#endif
#if BOOST_ARCH_X86_64
# define BOOST_ARCH_X86_64_AVAILABLE
#endif
#define BOOST_ARCH_X86_64_NAME "Intel x86-64"
#include <boost/predef/architecture/x86.h>
#endif
#include <boost/predef/detail/test.h>
BOOST_PREDEF_DECLARE_TEST(BOOST_ARCH_X86_64,BOOST_ARCH_X86_64_NAME)
| {
"language": "Assembly"
} |
# cr16 testcase for beq disp16
# mach(): cr16
.include "testutils.inc"
start
.global beq
beq:
mvi_h_condbit 0
movw $2, r4
movw $1, r5
cmpw r4, r5
bgt ok
not_ok:
fail
ok:
pass
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for AMD64, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
CALL runtime·entersyscall(SB)
MOVQ a1+8(FP), DI
MOVQ a2+16(FP), SI
MOVQ a3+24(FP), DX
MOVQ $0, R10
MOVQ $0, R8
MOVQ $0, R9
MOVQ trap+0(FP), AX // syscall entry
SYSCALL
MOVQ AX, r1+32(FP)
MOVQ DX, r2+40(FP)
CALL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVQ a1+8(FP), DI
MOVQ a2+16(FP), SI
MOVQ a3+24(FP), DX
MOVQ $0, R10
MOVQ $0, R8
MOVQ $0, R9
MOVQ trap+0(FP), AX // syscall entry
SYSCALL
MOVQ AX, r1+32(FP)
MOVQ DX, r2+40(FP)
RET
TEXT ·gettimeofday(SB),NOSPLIT,$0-16
JMP syscall·gettimeofday(SB)
| {
"language": "Assembly"
} |
/**
******************************************************************************
* @file lwipopts.h
* @author MCD Application Team
* @version V1.1.0
* @date 31-July-2013
* @brief lwIP Options Configuration.
* This file is based on Utilities\lwip_v1.4.1\src\include\lwip\opt.h
* and contains the lwIP configuration for the STM32F4x7 demonstration.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
* critical regions during buffer allocation, deallocation and memory
* allocation and deallocation.
*/
#define SYS_LIGHTWEIGHT_PROT 0
/**
* NO_SYS==1: Provides VERY minimal functionality. Otherwise,
* use lwIP facilities.
*/
#define NO_SYS 1
/**
* NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
* Mainly for compatibility to old versions.
*/
#define NO_SYS_NO_TIMERS 1
/* ---------- Memory options ---------- */
/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
byte alignment -> define MEM_ALIGNMENT to 2. */
#define MEM_ALIGNMENT 4
/* MEM_SIZE: the size of the heap memory. If the application will send
a lot of data that needs to be copied, this should be set high. */
#define MEM_SIZE (10*1024)
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
sends a lot of data out of ROM (or other static memory), this
should be set high. */
#define MEMP_NUM_PBUF 100
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
per active UDP "connection". */
#define MEMP_NUM_UDP_PCB 6
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
connections. */
#define MEMP_NUM_TCP_PCB 10
/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
connections. */
#define MEMP_NUM_TCP_PCB_LISTEN 6
/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
segments. */
#define MEMP_NUM_TCP_SEG 12
/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
timeouts. */
#define MEMP_NUM_SYS_TIMEOUT 10
/* ---------- Pbuf options ---------- */
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
#define PBUF_POOL_SIZE 10
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
#define PBUF_POOL_BUFSIZE 1000
/* ---------- TCP options ---------- */
#define LWIP_TCP 1
#define TCP_TTL 255
/* Controls if TCP should queue segments that arrive out of
order. Define to 0 if your device is low on memory. */
#define TCP_QUEUE_OOSEQ 0
/* TCP Maximum segment size. */
#define TCP_MSS (1500 - 40)/* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */
/* TCP sender buffer space (bytes). */
#define TCP_SND_BUF (4*TCP_MSS)
/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */
#define TCP_SND_QUEUELEN (2* TCP_SND_BUF/TCP_MSS)
/* TCP receive window. */
#define TCP_WND (2*TCP_MSS)
/* ---------- ICMP options ---------- */
#define LWIP_ICMP 1
/* ---------- DHCP options ---------- */
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
turning this on does currently not work. */
#define LWIP_DHCP 1
/* ---------- UDP options ---------- */
#define LWIP_UDP 1
#define UDP_TTL 255
/* ---------- Statistics options ---------- */
#define LWIP_STATS 0
#define LWIP_PROVIDE_ERRNO 1
/* ---------- link callback options ---------- */
/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
* whenever the link changes (i.e., link down)
*/
#define LWIP_NETIF_LINK_CALLBACK 1
/*
--------------------------------------
---------- Checksum options ----------
--------------------------------------
*/
/*
The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
- To use this feature let the following define uncommented.
- To disable it and process by CPU comment the the checksum.
*/
#define CHECKSUM_BY_HARDWARE
#ifdef CHECKSUM_BY_HARDWARE
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 0
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 0
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 0
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 0
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 0
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 0
/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/
#define CHECKSUM_GEN_ICMP 0
#else
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 1
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 1
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 1
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 1
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 1
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 1
/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/
#define CHECKSUM_GEN_ICMP 1
#endif
/*
----------------------------------------------
---------- Sequential layer options ----------
----------------------------------------------
*/
/**
* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
*/
#define LWIP_NETCONN 0
/*
------------------------------------
---------- Socket options ----------
------------------------------------
*/
/**
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
*/
#define LWIP_SOCKET 0
/*
----------------------------------------
---------- Lwip Debug options ----------
----------------------------------------
*/
//#define LWIP_DEBUG 1
#endif /* __LWIPOPTS_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for ARM64, NetBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
B syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
B syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
B syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
$NetBSD: patch-src_lib_sfio_Stdio__b_vsscanf.c,v 1.1 2013/09/10 14:18:11 joerg Exp $
--- src/lib/sfio/Stdio_b/vsscanf.c.orig 2013-09-10 12:06:32.000000000 +0000
+++ src/lib/sfio/Stdio_b/vsscanf.c
@@ -5,7 +5,7 @@
*/
#if __STD_C
-int vsscanf(char* s, const char* form, va_list args)
+int vsscanf(const char* s, const char* form, va_list args)
#else
int vsscanf(s,form,args)
reg char* s;
| {
"language": "Assembly"
} |
.size 8000
.text@48
jp ff80
.text@100
jp lbegin
.data@98
10
21
32
43
54
65
76
87
.data@143
80 00 00 00 1a 00 03
.text@200
ld sp, c001
ld hl, 3412
push hl
pop hl
ld a, 00
ldff(46), a
ld c, 26
lwaitdma:
dec c
jrnz lwaitdma
ld hl, 55aa
push hl
ld a, (fe9d)
ld c, a
ld a, (fe9e)
ld b, a
pop de
ld sp, cfff
push de
push bc
jp lprint4
.text@150
lbegin:
ld a, 0a
ld(0000), a
ld bc, 0200
ld hl, ff80
ld d, 40
lcopydmaroutine:
ld a, (bc)
ld(hl++), a
inc c
dec d
jrnz lcopydmaroutine
ld b, 90
call lwaitly_b
ld bc, fe00
ld d, a0
ld a, 06
lfill_oam:
ld(bc), a
inc c
dec d
jrnz lfill_oam
ld a, 90
ldff(45), a
ld a, 40
ldff(41), a
xor a, a
ldff(0f), a
ld a, 02
ldff(ff), a
ei
halt
.text@7000
lprint4:
ld b, 90
call lwaitly_b
xor a, a
ldff(40), a
ld bc, 7a00
ld hl, 8000
ld d, 00
lprint_copytiles:
ld a, (bc)
inc bc
ld(hl++), a
dec d
jrnz lprint_copytiles
ld hl, 9800
ld d, 02
lprint_settiles:
pop bc
ld a, c
srl a
srl a
srl a
srl a
ld(hl++), a
ld a, c
and a, 0f
ld(hl++), a
ld a, b
srl a
srl a
srl a
srl a
ld(hl++), a
ld a, b
and a, 0f
ld(hl++), a
dec d
jrnz lprint_settiles
ld a, c0
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
xor a, a
ldff(69), a
ldff(69), a
ldff(43), a
ld a, 91
ldff(40), a
lprint_limbo:
jr lprint_limbo
.text@7400
lwaitly_b:
ld c, 44
lwaitly_b_loop:
ldff a, (c)
cmp a, b
jrnz lwaitly_b_loop
ret
.data@7a00
00 00 7f 7f 41 41 41 41
41 41 41 41 41 41 7f 7f
00 00 08 08 08 08 08 08
08 08 08 08 08 08 08 08
00 00 7f 7f 01 01 01 01
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 01 01 01 01
3f 3f 01 01 01 01 7f 7f
00 00 41 41 41 41 41 41
7f 7f 01 01 01 01 01 01
00 00 7f 7f 40 40 40 40
7e 7e 01 01 01 01 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 41 41 41 41 7f 7f
00 00 7f 7f 01 01 02 02
04 04 08 08 10 10 10 10
00 00 3e 3e 41 41 41 41
3e 3e 41 41 41 41 3e 3e
00 00 7f 7f 41 41 41 41
7f 7f 01 01 01 01 7f 7f
00 00 08 08 22 22 41 41
7f 7f 41 41 41 41 41 41
00 00 7e 7e 41 41 41 41
7e 7e 41 41 41 41 7e 7e
00 00 3e 3e 41 41 40 40
40 40 40 40 41 41 3e 3e
00 00 7e 7e 41 41 41 41
41 41 41 41 41 41 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 40 40 40 40
7f 7f 40 40 40 40 40 40
| {
"language": "Assembly"
} |
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid result register
sqdecb w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb wsp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb wsp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Operands not matching up
sqdecb x0, w1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
// CHECK-NEXT: sqdecb x0, w1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, x1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb x0, x1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Immediate not compatible with encode/decode function.
sqdecb x0, all, mul #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqdecb x0, all, mul #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, all, mul #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqdecb x0, all, mul #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, all, mul #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqdecb x0, all, mul #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate patterns
sqdecb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecb x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdecb x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecb x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
| {
"language": "Assembly"
} |
SUMMARY="Library to use arbitrary fonts in OpenGL applications"
DESCRIPTION="FTGL is a free cross-platform Open Source C++ library that uses \
Freetype2 to simplify rendering fonts in OpenGL applications."
HOMEPAGE="https://sourceforge.net/projects/ftgl"
COPYRIGHT="2001-2004 Unicode, Inc.
2001-2009 Henry Maddocks"
LICENSE="MIT"
REVISION="2"
SOURCE_URI="https://sourceforge.net/projects/canvasdraw/files/5.11.1/Docs%20and%20Sources/ftgl-${portVersion}_Sources.tar.gz"
CHECKSUM_SHA256="690a7f80375846765f5cbbc10d0d859bfb62281441ff5878f818ced447fca763"
SOURCE_DIR="ftgl"
PATCHES="ftgl-$portVersion.patchset"
ARCHITECTURES="x86_gcc2 x86 x86_64"
SECONDARY_ARCHITECTURES="x86_gcc2 x86"
PROVIDES="
ftgl$secondaryArchSuffix = $portVersion compat >= 2
lib:libftgl$secondaryArchSuffix = 2.1.3 compat >= 2
"
REQUIRES="
haiku$secondaryArchSuffix
lib:libbz2$secondaryArchSuffix
lib:libfreetype$secondaryArchSuffix
lib:libgl$secondaryArchSuffix
lib:libglu$secondaryArchSuffix
lib:libpng16$secondaryArchSuffix
lib:libz$secondaryArchSuffix
"
PROVIDES_devel="
ftgl${secondaryArchSuffix}_devel = $portVersion compat >= 1
devel:libftgl$secondaryArchSuffix = 2.1.3 compat >= 2
"
REQUIRES_devel="
ftgl$secondaryArchSuffix == $portVersion base
devel:libfreetype$secondaryArchSuffix
"
BUILD_REQUIRES="
haiku${secondaryArchSuffix}_devel
devel:libfreetype$secondaryArchSuffix
devel:libgl$secondaryArchSuffix
devel:libglu$secondaryArchSuffix
"
BUILD_PREREQUIRES="
cmd:aclocal
cmd:autoconf
cmd:automake
cmd:gcc$secondaryArchSuffix
cmd:g++$secondaryArchSuffix
cmd:ld$secondaryArchSuffix
cmd:libtoolize$secondaryArchSuffix
cmd:make
cmd:pkg_config$secondaryArchSuffix
"
BUILD()
{
touch src/ftgl.dep
make $jobArgs
}
INSTALL()
{
mkdir -p $libDir
mkdir -p $includeDir
cp lib/Haiku11/*.so $libDir
cp -r include/FTGL $includeDir
prepareInstalledDevelLibs libftgl
fixPkgconfig
# devel package
packageEntries devel \
$developDir
}
| {
"language": "Assembly"
} |
StartChar: x.subs
Encoding: 65694 -1 1286
Width: 235
VWidth: -273
Flags: MW
LayerCount: 2
Fore
SplineSet
105 194 m 2
104 198 100 206 90 210 c 0
84 212 79 217 81 224 c 0
83 230 94 234 97 234 c 2
143 234 l 2
157 234 159 235 172 235 c 0
175 235 184 229 182 223 c 0
180 216 173 212 166 209 c 0
161 207 160 195 161 190 c 2
167 162 l 2
171 147 172 155 179 162 c 2
212 195 l 2
213 197 216 209 216 210 c 0
210 212 205 217 207 223 c 0
209 229 221 234 224 234 c 2
288 234 l 2
291 234 301 232 299 226 c 0
297 220 287 212 280 210 c 0
267 206 248 206 234 191 c 18
181 134 l 2
179 132 180 126 181 124 c 2
208 39 l 2
211 31 216 23 226 19 c 0
232 17 239 16 237 9 c 0
235 3 224 0 221 0 c 2
132 0 l 2
129 0 119 3 121 9 c 0
126 27 163 19 155 42 c 2
139 91 l 2
138 94 131 86 130 84 c 2
80 34 l 2
76 30 74 25 84 21 c 0
90 19 95 15 93 9 c 0
91 3 80 0 77 0 c 2
16 0 l 2
5 0 2 2 4 8 c 0
6 15 15 18 22 19 c 0
35 21 57 41 64 48 c 2
125 105 l 2
127 112 129 117 130 122 c 2
105 194 l 2
EndSplineSet
Validated: 33
EndChar
| {
"language": "Assembly"
} |
; RUN: opt -simplifycfg -S -o - < %s | FileCheck %s
; This test case was written to trigger an incorrect assert statement in
; -simplifycfg. Thus we don't actually want to check the output, just that
; -simplifycfg ran successfully. Thus we only check that the function still
; exists, and that it still calls foo().
;
; NOTE: There are some obviously dead blocks and missing branch weight
; metadata. Both of these features were key to triggering the assert.
; Additionally, the not-taken weight of the branch with a weight had to
; be 0 to trigger the assert.
declare void @foo() nounwind uwtable
define void @func(i32 %A) nounwind uwtable {
; CHECK-LABEL: define void @func(
entry:
%cmp11 = icmp eq i32 %A, 1
br i1 %cmp11, label %if.then, label %if.else, !prof !0
if.then:
call void @foo()
; CHECK: call void @foo()
br label %if.else
if.else:
%cmp17 = icmp eq i32 %A, 2
br i1 %cmp17, label %if.then2, label %if.end
if.then2:
br label %if.end
if.end:
ret void
}
!0 = !{!"branch_weights", i32 1, i32 0}
| {
"language": "Assembly"
} |
/*-----------------------------------------------------------------------
/ Low level disk interface modlue include file
/-----------------------------------------------------------------------*/
#ifndef _DISKIO
#define _READONLY 0 /* 1: Remove write functions */
#define _USE_IOCTL 1 /* 1: Use disk_ioctl fucntion */
#include "integer.h"
/* Status of Disk Functions */
typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
/*---------------------------------------*/
/* Prototypes for disk control functions */
int assign_drives (int, int);
DSTATUS disk_initialize (BYTE);
DSTATUS disk_status (BYTE);
DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
#if _READONLY == 0
DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
#endif
DRESULT disk_ioctl (BYTE, BYTE, void*);
DWORD get_fattime (void);
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01 /* Drive not initialized */
#define STA_NODISK 0x02 /* No medium in the drive */
#define STA_PROTECT 0x04 /* Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (defined for FatFs) */
#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */
/* Generic command */
#define CTRL_POWER 5 /* Get/Set power status */
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
#define CTRL_EJECT 7 /* Eject media */
/* MMC/SDC specific ioctl command */
#define MMC_GET_TYPE 10 /* Get card type */
#define MMC_GET_CSD 11 /* Get CSD */
#define MMC_GET_CID 12 /* Get CID */
#define MMC_GET_OCR 13 /* Get OCR */
#define MMC_GET_SDSTAT 14 /* Get SD status */
/* ATA/CF specific ioctl command */
#define ATA_GET_REV 20 /* Get F/W revision */
#define ATA_GET_MODEL 21 /* Get model name */
#define ATA_GET_SN 22 /* Get serial number */
/* NAND specific ioctl command */
#define NAND_FORMAT 30 /* Create physical format */
#define _DISKIO
#endif
| {
"language": "Assembly"
} |
# Si in diamond structure; 60 special points in core; low ecut.
# Similar to paral[01] but it uses mkmem 0, mffmem 0
acell 3*10.26311
densty 1.2
diemac 12.0d0
ecut 5.8
intxc 1
localrdwf 1
natom 2 nband 4
ngfft 3*16
nkpt 60
nline 3
nstep 2
nsym 24
ntypat 1
rprim 0 .5 .5 .5 0 .5 .5 .5 0
symrel
1 0 0 0 1 0 0 0 1
0 1 -1 1 0 -1 0 0 -1
0 -1 1 0 -1 0 1 -1 0
-1 0 0 -1 0 1 -1 1 0
0 1 0 0 0 1 1 0 0
1 0 -1 0 0 -1 0 1 -1
0 -1 0 1 -1 0 0 -1 1
-1 0 1 -1 1 0 -1 0 0
0 0 1 1 0 0 0 1 0
0 0 -1 0 1 -1 1 0 -1
1 -1 0 0 -1 1 0 -1 0
-1 1 0 -1 0 0 -1 0 1
1 0 -1 0 1 -1 0 0 -1
0 1 0 1 0 0 0 0 1
-1 0 1 -1 0 0 -1 1 0
0 -1 0 0 -1 1 1 -1 0
-1 1 0 -1 0 1 -1 0 0
1 -1 0 0 -1 0 0 -1 1
0 0 -1 1 0 -1 0 1 -1
0 0 1 0 1 0 1 0 0
0 -1 1 1 -1 0 0 -1 0
-1 0 0 -1 1 0 -1 0 1
1 0 0 0 0 1 0 1 0
0 1 -1 0 0 -1 1 0 -1
xred 3*0.00d0 3*0.25d0
timopt 2
tnons 72*0.0
tolwfr 1.d-20
typat 1 1
znucl 14
paral_kgb 0
kptopt 0
kpt
.43750000000000 .43750000000000 .43750000000000
.43750000000000 .43750000000000 .31250000000000
.43750000000000 .43750000000000 .18750000000000
.43750000000000 .43750000000000 .06250000000000
.50000000000000 .50000000000000 .06250000000000
.56250000000000 .37500000000000 .00000000000000
.56250000000000 .25000000000000 .00000000000000
.43750000000000 .43750000000000 .56250000000000
.43750000000000 .31250000000000 .31250000000000
.43750000000000 .31250000000000 .18750000000000
.43750000000000 .31250000000000 .06250000000000
.37500000000000 .50000000000000 .06250000000000
.50000000000000 .62500000000000 .18750000000000
.43750000000000 .31250000000000 .68750000000000
.43750000000000 .31250000000000 .56250000000000
.43750000000000 .18750000000000 .18750000000000
.43750000000000 .18750000000000 .06250000000000
.25000000000000 .50000000000000 .06250000000000
.37500000000000 .62500000000000 .18750000000000
.43750000000000 .18750000000000 .68750000000000
.43750000000000 .18750000000000 .56250000000000
.43750000000000 .06250000000000 .06250000000000
.12500000000000 .50000000000000 .06250000000000
.25000000000000 .62500000000000 .18750000000000
.56250000000000 .25000000000000 .62500000000000
.43750000000000 .06250000000000 .56250000000000
.00000000000000 .06250000000000 .50000000000000
.56250000000000 .37500000000000 .50000000000000
.56250000000000 .25000000000000 .50000000000000
.56250000000000 .37500000000000 .37500000000000
.56250000000000 .25000000000000 .37500000000000
.56250000000000 .25000000000000 .25000000000000
.31250000000000 .31250000000000 .31250000000000
.31250000000000 .31250000000000 .18750000000000
.31250000000000 .31250000000000 .06250000000000
.37500000000000 .37500000000000 .06250000000000
.50000000000000 .50000000000000 .18750000000000
.31250000000000 .31250000000000 .68750000000000
.31250000000000 .18750000000000 .18750000000000
.31250000000000 .18750000000000 .06250000000000
.25000000000000 .37500000000000 .06250000000000
.37500000000000 .50000000000000 .18750000000000
.50000000000000 .62500000000000 .31250000000000
.31250000000000 .06250000000000 .06250000000000
.12500000000000 .37500000000000 .06250000000000
.25000000000000 .50000000000000 .18750000000000
.37500000000000 .62500000000000 .31250000000000
.00000000000000 .06250000000000 .37500000000000
.12500000000000 .50000000000000 .18750000000000
.00000000000000 .18750000000000 .50000000000000
.18750000000000 .18750000000000 .18750000000000
.18750000000000 .18750000000000 .06250000000000
.25000000000000 .25000000000000 .06250000000000
.37500000000000 .37500000000000 .18750000000000
.18750000000000 .06250000000000 .06250000000000
.12500000000000 .25000000000000 .06250000000000
.25000000000000 .37500000000000 .18750000000000
.00000000000000 .06250000000000 .25000000000000
.06250000000000 .06250000000000 .06250000000000
.12500000000000 .12500000000000 .06250000000000
kptnrm 1
wtk
.00390625000000 .01171875000000 .01171875000000 .01171875000000
.01171875000000 .01171875000000 .01171875000000 .01171875000000
.01171875000000 .02343750000000 .02343750000000 .02343750000000
.02343750000000 .02343750000000 .02343750000000 .01171875000000
.02343750000000 .02343750000000 .02343750000000 .02343750000000
.02343750000000 .01171875000000 .02343750000000 .02343750000000
.02343750000000 .02343750000000 .01171875000000 .02343750000000
.02343750000000 .01171875000000 .02343750000000 .01171875000000
.00390625000000 .01171875000000 .01171875000000 .01171875000000
.01171875000000 .01171875000000 .01171875000000 .02343750000000
.02343750000000 .02343750000000 .02343750000000 .01171875000000
.02343750000000 .02343750000000 .02343750000000 .01171875000000
.02343750000000 .01171875000000 .00390625000000 .01171875000000
.01171875000000 .01171875000000 .01171875000000 .02343750000000
.02343750000000 .01171875000000 .00390625000000 .01171875000000
#%%<BEGIN TEST_INFO>
#%% [setup]
#%% executable = abinit
#%% [files]
#%% psp_files = 14si.psp
#%% [paral_info]
#%% nprocs_to_test = 1, 2, 4, 10
#%% max_nprocs = 10
#%% [NCPU_1]
#%% files_to_test = t02_MPI1.out, tolnlines= 0, tolabs= 0.0, tolrel= 0.0
#%% [NCPU_2]
#%% files_to_test = t02_MPI2.out, tolnlines= 0, tolabs= 0.0, tolrel= 0.0
#%% [NCPU_4]
#%% files_to_test = t02_MPI4.out, tolnlines= 0, tolabs= 0.0, tolrel= 0.0
#%% [NCPU_10]
#%% files_to_test = t02_MPI10.out, tolnlines= 0, tolabs= 0.0, tolrel= 0.0
#%% [extra_info]
#%% keywords = NC
#%% authors = Unknown
#%% description = Si in diamond structure; 60 special points, not in core; low ecut.
#%%<END TEST_INFO>
| {
"language": "Assembly"
} |
// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build riscv64,!gccgo
#include "textflag.h"
//
// System calls for linux/riscv64.
//
// Where available, just jump to package syscall's implementation of
// these functions.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
CALL runtime·entersyscall(SB)
MOV a1+8(FP), A0
MOV a2+16(FP), A1
MOV a3+24(FP), A2
MOV trap+0(FP), A7 // syscall entry
ECALL
MOV A0, r1+32(FP) // r1
MOV A1, r2+40(FP) // r2
CALL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOV a1+8(FP), A0
MOV a2+16(FP), A1
MOV a3+24(FP), A2
MOV trap+0(FP), A7 // syscall entry
ECALL
MOV A0, r1+32(FP)
MOV A1, r2+40(FP)
RET
| {
"language": "Assembly"
} |
.include "macros.inc"
start
test_name XNOR_1
mvi r1, 0
mvi r2, 0
xnor r3, r1, r2
check_r3 0xffffffff
test_name XNOR_2
mvi r1, 0
mvi r2, 1
xnor r3, r1, r2
check_r3 0xfffffffe
test_name XNOR_3
mvi r1, 1
mvi r2, 1
xnor r3, r1, r2
check_r3 0xffffffff
test_name XNOR_4
mvi r1, 1
mvi r2, 0
xnor r3, r1, r2
check_r3 0xfffffffe
test_name XNOR_5
load r1 0xaa55aa55
load r2 0x55aa55aa
xnor r3, r1, r2
check_r3 0
test_name XNOR_6
load r1 0xaa550000
load r2 0x0000aa55
xnor r3, r1, r2
check_r3 0x55aa55aa
test_name XNOR_7
load r1 0xaa55aa55
xnor r3, r1, r1
check_r3 0xffffffff
test_name XNOR_8
load r3 0xaa55aa55
xnor r3, r3, r3
check_r3 0xffffffff
end
| {
"language": "Assembly"
} |
#class ofiPhoneVideoGrabber
<!--
_visible: True_
_advanced: True_
-->
##InlineDescription
##Description
##Methods
###void close()
<!--
_syntax: close()_
_name: close_
_returns: void_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void getDeviceList()
<!--
_syntax: getDeviceList()_
_name: getDeviceList_
_returns: void_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###float getHeight()
<!--
_syntax: getHeight()_
_name: getHeight_
_returns: float_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofPixelFormat getPixelFormat()
<!--
_syntax: getPixelFormat()_
_name: getPixelFormat_
_returns: ofPixelFormat_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###unsigned char * getPixels()
<!--
_syntax: getPixels()_
_name: getPixels_
_returns: unsigned char *_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofPixelsRef getPixelsRef()
<!--
_syntax: getPixelsRef()_
_name: getPixelsRef_
_returns: ofPixelsRef_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###float getWidth()
<!--
_syntax: getWidth()_
_name: getWidth_
_returns: float_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###bool initGrabber(w, h)
<!--
_syntax: initGrabber(w, h)_
_name: initGrabber_
_returns: bool_
_returns_description: _
_parameters: int w, int h_
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###bool isFrameNew()
<!--
_syntax: isFrameNew()_
_name: isFrameNew_
_returns: bool_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void listDevices()
<!--
_syntax: listDevices()_
_name: listDevices_
_returns: void_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
### ofiPhoneVideoGrabber()
<!--
_syntax: ofiPhoneVideoGrabber()_
_name: ofiPhoneVideoGrabber_
_returns: _
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void setDesiredFrameRate(framerate)
<!--
_syntax: setDesiredFrameRate(framerate)_
_name: setDesiredFrameRate_
_returns: void_
_returns_description: _
_parameters: int framerate_
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void setDeviceID(_deviceID)
<!--
_syntax: setDeviceID(_deviceID)_
_name: setDeviceID_
_returns: void_
_returns_description: _
_parameters: int _deviceID_
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void setPixelFormat(internalPixelFormat)
<!--
_syntax: setPixelFormat(internalPixelFormat)_
_name: setPixelFormat_
_returns: void_
_returns_description: _
_parameters: ofPixelFormat internalPixelFormat_
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void update()
<!--
_syntax: update()_
_name: update_
_returns: void_
_returns_description: _
_parameters: _
_access: public_
_version_started: 007_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
##Variables
###ofPtr grabber
<!--
_name: grabber_
_type: ofPtr_
_access: protected_
_version_started: 007_
_version_deprecated: _
_summary: _
_visible: True_
_constant: True_
_advanced: False_
-->
_description: _
<!----------------------------------------------------------------------------->
| {
"language": "Assembly"
} |
glabel func_80946B00
/* 0DE30 80946B00 27BDFFC8 */ addiu $sp, $sp, 0xFFC8 ## $sp = FFFFFFC8
/* 0DE34 80946B04 AFBF001C */ sw $ra, 0x001C($sp)
/* 0DE38 80946B08 AFB00018 */ sw $s0, 0x0018($sp)
/* 0DE3C 80946B0C AFA5003C */ sw $a1, 0x003C($sp)
/* 0DE40 80946B10 84880156 */ lh $t0, 0x0156($a0) ## 00000156
/* 0DE44 80946B14 848E0150 */ lh $t6, 0x0150($a0) ## 00000150
/* 0DE48 80946B18 84980152 */ lh $t8, 0x0152($a0) ## 00000152
/* 0DE4C 80946B1C 25090001 */ addiu $t1, $t0, 0x0001 ## $t1 = 00000001
/* 0DE50 80946B20 A4890156 */ sh $t1, 0x0156($a0) ## 00000156
/* 0DE54 80946B24 84820156 */ lh $v0, 0x0156($a0) ## 00000156
/* 0DE58 80946B28 25CF0001 */ addiu $t7, $t6, 0x0001 ## $t7 = 00000001
/* 0DE5C 80946B2C 27190001 */ addiu $t9, $t8, 0x0001 ## $t9 = 00000001
/* 0DE60 80946B30 2841001E */ slti $at, $v0, 0x001E
/* 0DE64 80946B34 00808025 */ or $s0, $a0, $zero ## $s0 = 00000000
/* 0DE68 80946B38 A48F0150 */ sh $t7, 0x0150($a0) ## 00000150
/* 0DE6C 80946B3C 14200003 */ bne $at, $zero, .L80946B4C
/* 0DE70 80946B40 A4990152 */ sh $t9, 0x0152($a0) ## 00000152
/* 0DE74 80946B44 A4800156 */ sh $zero, 0x0156($a0) ## 00000156
/* 0DE78 80946B48 84820156 */ lh $v0, 0x0156($a0) ## 00000156
.L80946B4C:
/* 0DE7C 80946B4C 26060024 */ addiu $a2, $s0, 0x0024 ## $a2 = 00000024
/* 0DE80 80946B50 00025080 */ sll $t2, $v0, 2
/* 0DE84 80946B54 8CCD0000 */ lw $t5, 0x0000($a2) ## 00000024
/* 0DE88 80946B58 01425023 */ subu $t2, $t2, $v0
/* 0DE8C 80946B5C 000A5080 */ sll $t2, $t2, 2
/* 0DE90 80946B60 020A5821 */ addu $t3, $s0, $t2
/* 0DE94 80946B64 AD6D01E8 */ sw $t5, 0x01E8($t3) ## 000001E8
/* 0DE98 80946B68 8CCC0004 */ lw $t4, 0x0004($a2) ## 00000028
/* 0DE9C 80946B6C 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 0DEA0 80946B70 AD6C01EC */ sw $t4, 0x01EC($t3) ## 000001EC
/* 0DEA4 80946B74 8CCD0008 */ lw $t5, 0x0008($a2) ## 0000002C
/* 0DEA8 80946B78 AD6D01F0 */ sw $t5, 0x01F0($t3) ## 000001F0
/* 0DEAC 80946B7C AFA60020 */ sw $a2, 0x0020($sp)
/* 0DEB0 80946B80 8E19014C */ lw $t9, 0x014C($s0) ## 0000014C
/* 0DEB4 80946B84 8FA5003C */ lw $a1, 0x003C($sp)
/* 0DEB8 80946B88 0320F809 */ jalr $ra, $t9
/* 0DEBC 80946B8C 00000000 */ nop
/* 0DEC0 80946B90 8FA60020 */ lw $a2, 0x0020($sp)
/* 0DEC4 80946B94 00001025 */ or $v0, $zero, $zero ## $v0 = 00000000
/* 0DEC8 80946B98 00027040 */ sll $t6, $v0, 1
.L80946B9C:
/* 0DECC 80946B9C 020E1821 */ addu $v1, $s0, $t6
/* 0DED0 80946BA0 84640178 */ lh $a0, 0x0178($v1) ## 00000178
/* 0DED4 80946BA4 24420001 */ addiu $v0, $v0, 0x0001 ## $v0 = 00000001
/* 0DED8 80946BA8 00021400 */ sll $v0, $v0, 16
/* 0DEDC 80946BAC 10800003 */ beq $a0, $zero, .L80946BBC
/* 0DEE0 80946BB0 00021403 */ sra $v0, $v0, 16
/* 0DEE4 80946BB4 248FFFFF */ addiu $t7, $a0, 0xFFFF ## $t7 = FFFFFFFF
/* 0DEE8 80946BB8 A46F0178 */ sh $t7, 0x0178($v1) ## 00000178
.L80946BBC:
/* 0DEEC 80946BBC 28410005 */ slti $at, $v0, 0x0005
/* 0DEF0 80946BC0 5420FFF6 */ bnel $at, $zero, .L80946B9C
/* 0DEF4 80946BC4 00027040 */ sll $t6, $v0, 1
/* 0DEF8 80946BC8 8602015A */ lh $v0, 0x015A($s0) ## 0000015A
/* 0DEFC 80946BCC 10400002 */ beq $v0, $zero, .L80946BD8
/* 0DF00 80946BD0 2458FFFF */ addiu $t8, $v0, 0xFFFF ## $t8 = 00000000
/* 0DF04 80946BD4 A618015A */ sh $t8, 0x015A($s0) ## 0000015A
.L80946BD8:
/* 0DF08 80946BD8 86020168 */ lh $v0, 0x0168($s0) ## 00000168
/* 0DF0C 80946BDC 10400002 */ beq $v0, $zero, .L80946BE8
/* 0DF10 80946BE0 2448FFFF */ addiu $t0, $v0, 0xFFFF ## $t0 = 00000000
/* 0DF14 80946BE4 A6080168 */ sh $t0, 0x0168($s0) ## 00000168
.L80946BE8:
/* 0DF18 80946BE8 8CCA0000 */ lw $t2, 0x0000($a2) ## 00000000
/* 0DF1C 80946BEC 260505AC */ addiu $a1, $s0, 0x05AC ## $a1 = 000005AC
/* 0DF20 80946BF0 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 0DF24 80946BF4 AE0A0038 */ sw $t2, 0x0038($s0) ## 00000038
/* 0DF28 80946BF8 8CC90004 */ lw $t1, 0x0004($a2) ## 00000004
/* 0DF2C 80946BFC AE09003C */ sw $t1, 0x003C($s0) ## 0000003C
/* 0DF30 80946C00 8CCA0008 */ lw $t2, 0x0008($a2) ## 00000008
/* 0DF34 80946C04 AE0A0040 */ sw $t2, 0x0040($s0) ## 00000040
/* 0DF38 80946C08 0C0189B7 */ jal Collider_CylinderUpdate
/* 0DF3C 80946C0C AFA50024 */ sw $a1, 0x0024($sp)
/* 0DF40 80946C10 920B0565 */ lbu $t3, 0x0565($s0) ## 00000565
/* 0DF44 80946C14 51600014 */ beql $t3, $zero, .L80946C68
/* 0DF48 80946C18 A2000565 */ sb $zero, 0x0565($s0) ## 00000565
/* 0DF4C 80946C1C 860C015A */ lh $t4, 0x015A($s0) ## 0000015A
/* 0DF50 80946C20 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 0DF54 80946C24 55800010 */ bnel $t4, $zero, .L80946C68
/* 0DF58 80946C28 A2000565 */ sb $zero, 0x0565($s0) ## 00000565
/* 0DF5C 80946C2C 0C251A1F */ jal func_8094687C
/* 0DF60 80946C30 8FA5003C */ lw $a1, 0x003C($sp)
/* 0DF64 80946C34 1440000B */ bne $v0, $zero, .L80946C64
/* 0DF68 80946C38 8FA4003C */ lw $a0, 0x003C($sp)
/* 0DF6C 80946C3C 3C010001 */ lui $at, 0x0001 ## $at = 00010000
/* 0DF70 80946C40 34211E60 */ ori $at, $at, 0x1E60 ## $at = 00011E60
/* 0DF74 80946C44 00812821 */ addu $a1, $a0, $at
/* 0DF78 80946C48 AFA50028 */ sw $a1, 0x0028($sp)
/* 0DF7C 80946C4C 0C01767D */ jal CollisionCheck_SetAC
## CollisionCheck_setAC
/* 0DF80 80946C50 8FA60024 */ lw $a2, 0x0024($sp)
/* 0DF84 80946C54 8FA50028 */ lw $a1, 0x0028($sp)
/* 0DF88 80946C58 8FA4003C */ lw $a0, 0x003C($sp)
/* 0DF8C 80946C5C 0C0175E7 */ jal CollisionCheck_SetAT
## CollisionCheck_setAT
/* 0DF90 80946C60 8FA60024 */ lw $a2, 0x0024($sp)
.L80946C64:
/* 0DF94 80946C64 A2000565 */ sb $zero, 0x0565($s0) ## 00000565
.L80946C68:
/* 0DF98 80946C68 8FBF001C */ lw $ra, 0x001C($sp)
/* 0DF9C 80946C6C 8FB00018 */ lw $s0, 0x0018($sp)
/* 0DFA0 80946C70 27BD0038 */ addiu $sp, $sp, 0x0038 ## $sp = 00000000
/* 0DFA4 80946C74 03E00008 */ jr $ra
/* 0DFA8 80946C78 00000000 */ nop
| {
"language": "Assembly"
} |
/* INTERN.h
*
* Copyright (C) 1991, 1992, 1993, 1995, 1996, 1998, 2000, 2001,
* by Larry Wall and others
*
* You may distribute under the terms of either the GNU General Public
* License or the Artistic License, as specified in the README file.
*
*/
/*
* EXT designates a global var which is defined in perl.h
* dEXT designates a global var which is defined in another
* file, so we can't count on finding it in perl.h
* (this practice should be avoided).
*/
#undef EXT
#undef dEXT
#undef EXTCONST
#undef dEXTCONST
#if defined(VMS) && !defined(__GNUC__)
/* Suppress portability warnings from DECC for VMS-specific extensions */
# ifdef __DECC
# pragma message disable (GLOBALEXT,NOSHAREEXT,READONLYEXT)
# endif
# define EXT globaldef {"$GLOBAL_RW_VARS"} noshare
# define dEXT globaldef {"$GLOBAL_RW_VARS"} noshare
# define EXTCONST globaldef {"$GLOBAL_RO_VARS"} readonly
# define dEXTCONST globaldef {"$GLOBAL_RO_VARS"} readonly
#else
# if (defined(WIN32) && defined(__MINGW32__)) || defined(__SYMBIAN32__)
# define EXT __declspec(dllexport)
# define dEXT
# define EXTCONST __declspec(dllexport) const
# define dEXTCONST const
# else
# ifdef __cplusplus
# define EXT
# define dEXT
# define EXTCONST extern const
# define dEXTCONST const
# else
# define EXT
# define dEXT
# define EXTCONST const
# define dEXTCONST const
# endif
# endif
#endif
#undef INIT
#define INIT(x) = x
#define DOINIT
| {
"language": "Assembly"
} |
// REQUIRES: x86-registered-target
// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | opt -strip -S | FileCheck %s
// Some test cases for MS inline asm support from Mozilla code base.
void invoke_copy_to_stack() {}
void invoke(void* that, unsigned methodIndex,
unsigned paramCount, void* params)
{
// CHECK: @invoke
// CHECK: %5 = alloca i8*, align 4
// CHECK: %6 = alloca i32, align 4
// CHECK: %7 = alloca i32, align 4
// CHECK: %8 = alloca i8*, align 4
// CHECK: store i8* %0, i8** %5, align 4
// CHECK: store i32 %1, i32* %6, align 4
// CHECK: store i32 %2, i32* %7, align 4
// CHECK: store i8* %3, i8** %8, align 4
// CHECK: call void asm sideeffect inteldialect
// CHECK: mov edx,dword ptr $1
// CHECK: test edx,edx
// CHECK: jz {{[^_]*}}__MSASMLABEL_.0__noparams
// ^ Can't use {{.*}} here because the matching is greedy.
// CHECK: mov eax,edx
// CHECK: shl eax,$$3
// CHECK: sub esp,eax
// CHECK: mov ecx,esp
// CHECK: push dword ptr $0
// CHECK: call dword ptr $2
// CHECK: {{.*}}__MSASMLABEL_.0__noparams:
// CHECK: mov ecx,dword ptr $3
// CHECK: push ecx
// CHECK: mov edx,[ecx]
// CHECK: mov eax,dword ptr $4
// CHECK: call dword ptr[edx+eax*$$4]
// CHECK: mov esp,ebp
// CHECK: pop ebp
// CHECK: ret
// CHECK: "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"
// CHECK: (i8** %8, i32* %7, void (...)* bitcast (void ()* @invoke_copy_to_stack to void (...)*), i8** %5, i32* %6)
// CHECK: ret void
__asm {
mov edx,paramCount
test edx,edx
jz noparams
mov eax,edx
shl eax,3
sub esp,eax
mov ecx,esp
push params
call invoke_copy_to_stack
noparams:
mov ecx,that
push ecx
mov edx,[ecx]
mov eax,methodIndex
call dword ptr[edx+eax*4]
mov esp,ebp
pop ebp
ret
}
}
| {
"language": "Assembly"
} |
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -guard-widening-widen-frequent-branches=true -guard-widening-frequent-branch-threshold=1000 -S -guard-widening < %s | FileCheck %s
; RUN: opt -guard-widening-widen-frequent-branches=true -guard-widening-frequent-branch-threshold=1000 -S -passes='require<branch-prob>,guard-widening' < %s | FileCheck %s
declare void @llvm.experimental.guard(i1,...)
declare void @foo()
declare void @bar()
; Check that we don't widen without branch probability.
define void @test_01(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_01(
; CHECK-NEXT: entry:
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND_0:%.*]]) [ "deopt"() ]
; CHECK-NEXT: br i1 [[COND_1:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
ret void
}
; Check that we don't widen with branch probability below threshold.
define void @test_02(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_02(
; CHECK-NEXT: entry:
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND_0:%.*]]) [ "deopt"() ]
; CHECK-NEXT: br i1 [[COND_1:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !0
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !0
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
ret void
}
; Check that we widen conditions of explicit branches into dominating guards
; when the probability is high enough.
define void @test_03(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_03(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[COND_1:%.*]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 true, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !1
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !1
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
ret void
}
; Similar to test_03, but the likely taken branch is the false branch.
define void @test_03_not_taken(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_03_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INVERTED:%.*]] = xor i1 [[COND_1:%.*]], true
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[INVERTED]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 false, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !2
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !3
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
ret void
}
; Widen loop-invariant condition into the guard in preheader.
define void @test_04(i1 %cond_0, i1 %cond_1, i32 %n) {
; CHECK-LABEL: @test_04(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[COND_1:%.*]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[MERGE:%.*]] ]
; CHECK-NEXT: br i1 true, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !1
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %merge ]
br i1 %cond_1, label %if.true, label %if.false, !prof !1
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
%iv.next = add i32 %iv, 1
%cond = icmp slt i32 %iv.next, %n
br i1 %cond, label %loop, label %exit
exit:
ret void
}
; Similar to test_04, but the likely taken branch is the false branch.
define void @test_04_not_taken(i1 %cond_0, i1 %cond_1, i32 %n) {
; CHECK-LABEL: @test_04_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INVERTED:%.*]] = xor i1 [[COND_1:%.*]], true
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[INVERTED]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[MERGE:%.*]] ]
; CHECK-NEXT: br i1 false, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !2
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %merge ]
br i1 %cond_1, label %if.true, label %if.false, !prof !3
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
%iv.next = add i32 %iv, 1
%cond = icmp slt i32 %iv.next, %n
br i1 %cond, label %loop, label %exit
exit:
ret void
}
; Widen loop-invariant condition into the guard in the same loop.
define void @test_05(i1 %cond_0, i1 %cond_1, i32 %n) {
; CHECK-LABEL: @test_05(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[MERGE:%.*]] ]
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[COND_1:%.*]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 true, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !1
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %merge ]
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !1
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
%iv.next = add i32 %iv, 1
%cond = icmp slt i32 %iv.next, %n
br i1 %cond, label %loop, label %exit
exit:
ret void
}
; Similar to test_05, but the likely taken branch is the false branch.
define void @test_05_not_taken(i1 %cond_0, i1 %cond_1, i32 %n) {
; CHECK-LABEL: @test_05_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[MERGE:%.*]] ]
; CHECK-NEXT: [[INVERTED:%.*]] = xor i1 [[COND_1:%.*]], true
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[INVERTED]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 false, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !2
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: if.false:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %merge ]
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !3
if.true:
call void @foo()
br label %merge
if.false:
call void @bar()
br label %merge
merge:
%iv.next = add i32 %iv, 1
%cond = icmp slt i32 %iv.next, %n
br i1 %cond, label %loop, label %exit
exit:
ret void
}
; Some of checks are frequently taken and some are not, make sure that we only
; widen frequent ones.
define void @test_06(i1 %cond_0, i1 %cond_1, i1 %cond_2, i1 %cond_3, i1 %cond_4, i32 %n) {
; CHECK-LABEL: @test_06(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[COND_2:%.*]]
; CHECK-NEXT: [[WIDE_CHK1:%.*]] = and i1 [[WIDE_CHK]], [[COND_4:%.*]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK1]]) [ "deopt"() ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: br i1 [[COND_1:%.*]], label [[IF_TRUE_1:%.*]], label [[IF_FALSE_1:%.*]], !prof !3
; CHECK: if.true_1:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE_1:%.*]]
; CHECK: if.false_1:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE_1]]
; CHECK: merge_1:
; CHECK-NEXT: br i1 true, label [[IF_TRUE_2:%.*]], label [[IF_FALSE_2:%.*]], !prof !1
; CHECK: if.true_2:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE_2:%.*]]
; CHECK: if.false_2:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE_2]]
; CHECK: merge_2:
; CHECK-NEXT: br i1 [[COND_3:%.*]], label [[IF_TRUE_3:%.*]], label [[IF_FALSE_3:%.*]], !prof !3
; CHECK: if.true_3:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE_3:%.*]]
; CHECK: if.false_3:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE_3]]
; CHECK: merge_3:
; CHECK-NEXT: br i1 true, label [[IF_TRUE_4:%.*]], label [[IF_FALSE_4:%.*]], !prof !1
; CHECK: if.true_4:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BACKEDGE]]
; CHECK: if.false_4:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ]
br i1 %cond_1, label %if.true_1, label %if.false_1, !prof !2
if.true_1:
call void @foo()
br label %merge_1
if.false_1:
call void @bar()
br label %merge_1
merge_1:
br i1 %cond_2, label %if.true_2, label %if.false_2, !prof !1
if.true_2:
call void @foo()
br label %merge_2
if.false_2:
call void @bar()
br label %merge_2
merge_2:
br i1 %cond_3, label %if.true_3, label %if.false_3, !prof !2
if.true_3:
call void @foo()
br label %merge_3
if.false_3:
call void @bar()
br label %merge_3
merge_3:
br i1 %cond_4, label %if.true_4, label %if.false_4, !prof !1
if.true_4:
call void @foo()
br label %backedge
if.false_4:
call void @bar()
br label %backedge
backedge:
%iv.next = add i32 %iv, 1
%cond = icmp slt i32 %iv.next, %n
br i1 %cond, label %loop, label %exit
exit:
ret void
}
; Similar to test_06, but the likely taken branch is the false branch.
define void @test_06_not_taken(i1 %cond_0, i1 %cond_1, i1 %cond_2, i1 %cond_3, i1 %cond_4, i32 %n) {
; CHECK-LABEL: @test_06_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INVERTED:%.*]] = xor i1 [[COND_2:%.*]], true
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[INVERTED]]
; CHECK-NEXT: [[INVERTED1:%.*]] = xor i1 [[COND_4:%.*]], true
; CHECK-NEXT: [[WIDE_CHK2:%.*]] = and i1 [[WIDE_CHK]], [[INVERTED1]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK2]]) [ "deopt"() ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
; CHECK-NEXT: br i1 [[COND_1:%.*]], label [[IF_TRUE_1:%.*]], label [[IF_FALSE_1:%.*]], !prof !3
; CHECK: if.true_1:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE_1:%.*]]
; CHECK: if.false_1:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE_1]]
; CHECK: merge_1:
; CHECK-NEXT: br i1 false, label [[IF_TRUE_2:%.*]], label [[IF_FALSE_2:%.*]], !prof !2
; CHECK: if.true_2:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE_2:%.*]]
; CHECK: if.false_2:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE_2]]
; CHECK: merge_2:
; CHECK-NEXT: br i1 [[COND_3:%.*]], label [[IF_TRUE_3:%.*]], label [[IF_FALSE_3:%.*]], !prof !3
; CHECK: if.true_3:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE_3:%.*]]
; CHECK: if.false_3:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[MERGE_3]]
; CHECK: merge_3:
; CHECK-NEXT: br i1 false, label [[IF_TRUE_4:%.*]], label [[IF_FALSE_4:%.*]], !prof !2
; CHECK: if.true_4:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BACKEDGE]]
; CHECK: if.false_4:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[BACKEDGE]]
; CHECK: backedge:
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[N:%.*]]
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ]
br i1 %cond_1, label %if.true_1, label %if.false_1, !prof !2
if.true_1:
call void @foo()
br label %merge_1
if.false_1:
call void @bar()
br label %merge_1
merge_1:
br i1 %cond_2, label %if.true_2, label %if.false_2, !prof !3
if.true_2:
call void @foo()
br label %merge_2
if.false_2:
call void @bar()
br label %merge_2
merge_2:
br i1 %cond_3, label %if.true_3, label %if.false_3, !prof !2
if.true_3:
call void @foo()
br label %merge_3
if.false_3:
call void @bar()
br label %merge_3
merge_3:
br i1 %cond_4, label %if.true_4, label %if.false_4, !prof !3
if.true_4:
call void @foo()
br label %backedge
if.false_4:
call void @bar()
br label %backedge
backedge:
%iv.next = add i32 %iv, 1
%cond = icmp slt i32 %iv.next, %n
br i1 %cond, label %loop, label %exit
exit:
ret void
}
; Check triangle CFG pattern.
define void @test_07(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_07(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[COND_1:%.*]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 true, label [[IF_TRUE:%.*]], label [[MERGE:%.*]], !prof !1
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %merge, !prof !1
if.true:
call void @foo()
br label %merge
merge:
ret void
}
; Similar to test_07, but the likely taken branch is the false branch.
define void @test_07_not_taken(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_07_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INVERTED:%.*]] = xor i1 [[COND_1:%.*]], true
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[INVERTED]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 false, label [[IF_TRUE:%.*]], label [[MERGE:%.*]], !prof !2
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %merge, !prof !3
if.true:
call void @foo()
br label %merge
merge:
ret void
}
define void @test_08(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_08(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[COND_1:%.*]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 true, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !1
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: ret void
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !1
if.true:
call void @foo()
br label %merge
if.false:
ret void
merge:
ret void
}
define void @test_08_not_taken(i1 %cond_0, i1 %cond_1) {
; CHECK-LABEL: @test_08_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[INVERTED:%.*]] = xor i1 [[COND_1:%.*]], true
; CHECK-NEXT: [[WIDE_CHK:%.*]] = and i1 [[COND_0:%.*]], [[INVERTED]]
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 false, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !2
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: ret void
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !3
if.true:
call void @foo()
br label %merge
if.false:
ret void
merge:
ret void
}
; Check that L >u C0 && L >u C1 -> L >u max(C0, C1).
define void @test_09(i32 %L) {
; CHECK-LABEL: @test_09(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND_0:%.*]] = icmp ugt i32 [[L:%.*]], 123
; CHECK-NEXT: [[COND_1:%.*]] = icmp ugt i32 [[L]], 456
; CHECK-NEXT: [[WIDE_CHK:%.*]] = icmp uge i32 [[L]], 457
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 true, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !1
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: ret void
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
%cond_0 = icmp ugt i32 %L, 123
%cond_1 = icmp ugt i32 %L, 456
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !1
if.true:
call void @foo()
br label %merge
if.false:
ret void
merge:
ret void
}
; Check that L >u C0 && !(L <=u C1) -> L >u max(C0, C1).
define void @test_09_not_taken(i32 %L) {
; CHECK-LABEL: @test_09_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND_0:%.*]] = icmp ugt i32 [[L:%.*]], 123
; CHECK-NEXT: [[COND_1:%.*]] = icmp ule i32 [[L]], 456
; CHECK-NEXT: [[WIDE_CHK:%.*]] = icmp uge i32 [[L]], 457
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 false, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !2
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: ret void
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
%cond_0 = icmp ugt i32 %L, 123
%cond_1 = icmp ule i32 %L, 456
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !3
if.true:
call void @foo()
br label %merge
if.false:
ret void
merge:
ret void
}
; Check that a profitable transform is preferred over non-profitable.
define void @test_10(i32 %L, i1 %irrelevant_cond, i1 %infinite_loop_cond) {
; CHECK-LABEL: @test_10(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND_0:%.*]] = icmp ugt i32 [[L:%.*]], 123
; CHECK-NEXT: [[COND_1:%.*]] = icmp ugt i32 [[L]], 456
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[IRRELEVANT_COND:%.*]]) [ "deopt"() ]
; CHECK-NEXT: br i1 [[INFINITE_LOOP_COND:%.*]], label [[LOOP]], label [[AFTER_LOOP:%.*]]
; CHECK: after_loop:
; CHECK-NEXT: [[WIDE_CHK:%.*]] = icmp uge i32 [[L]], 457
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 true, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !1
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
%cond_0 = icmp ugt i32 %L, 123
%cond_1 = icmp ugt i32 %L, 456
br label %loop
loop:
call void(i1, ...) @llvm.experimental.guard(i1 %irrelevant_cond) [ "deopt"() ]
br i1 %infinite_loop_cond, label %loop, label %after_loop
after_loop:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !1
if.true:
call void @foo()
br label %merge
if.false:
br label %merge
merge:
ret void
}
; Check that a profitable transform is preferred over non-profitable.
define void @test_10_not_taken(i32 %L, i1 %irrelevant_cond, i1 %infinite_loop_cond) {
; CHECK-LABEL: @test_10_not_taken(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND_0:%.*]] = icmp ugt i32 [[L:%.*]], 123
; CHECK-NEXT: [[COND_1:%.*]] = icmp ule i32 [[L]], 456
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[IRRELEVANT_COND:%.*]]) [ "deopt"() ]
; CHECK-NEXT: br i1 [[INFINITE_LOOP_COND:%.*]], label [[LOOP]], label [[AFTER_LOOP:%.*]]
; CHECK: after_loop:
; CHECK-NEXT: [[WIDE_CHK:%.*]] = icmp uge i32 [[L]], 457
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[WIDE_CHK]]) [ "deopt"() ]
; CHECK-NEXT: br i1 false, label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]], !prof !2
; CHECK: if.true:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false:
; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge:
; CHECK-NEXT: ret void
;
entry:
%cond_0 = icmp ugt i32 %L, 123
%cond_1 = icmp ule i32 %L, 456
br label %loop
loop:
call void(i1, ...) @llvm.experimental.guard(i1 %irrelevant_cond) [ "deopt"() ]
br i1 %infinite_loop_cond, label %loop, label %after_loop
after_loop:
call void(i1, ...) @llvm.experimental.guard(i1 %cond_0) [ "deopt"() ]
br i1 %cond_1, label %if.true, label %if.false, !prof !3
if.true:
call void @foo()
br label %merge
if.false:
br label %merge
merge:
ret void
}
!0 = !{!"branch_weights", i32 998, i32 1}
!1 = !{!"branch_weights", i32 999, i32 1}
!2 = !{!"branch_weights", i32 500, i32 500}
!3 = !{!"branch_weights", i32 1, i32 999}
| {
"language": "Assembly"
} |
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn | FileCheck %s
define void @t0(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly {
; CHECK: t0
; CHECK: pand
; CHECK: ret
%cmp1 = icmp ne <2 x i64> %src1, zeroinitializer
%cmp2 = icmp ne <2 x i64> %src2, zeroinitializer
%t1 = and <2 x i1> %cmp1, %cmp2
%t2 = sext <2 x i1> %t1 to <2 x i64>
store <2 x i64> %t2, <2 x i64>* %dst
ret void
}
define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly {
; CHECK: t2
; CHECK: pand
; CHECK: ret
%cmp1 = icmp ne <3 x i64> %src1, zeroinitializer
%cmp2 = icmp ne <3 x i64> %src2, zeroinitializer
%t1 = and <3 x i1> %cmp1, %cmp2
%t2 = sext <3 x i1> %t1 to <3 x i64>
store <3 x i64> %t2, <3 x i64>* %dst
ret void
}
| {
"language": "Assembly"
} |
# mach: crisv32
# output: fffffffe\n
# output: fffffffe\n
; Check basic integral-write semantics regarding flags.
.include "testutils.inc"
start
move.d 0, $r3
; A write that works. Check that flags are set correspondingly.
move.d d,r4
;; store to bring it into the tlb with the right prot bits
move.d r3,[r4]
moveq -2,r5
setf c
clearf p
move.d [r4],r3
ax
move.d r5,[r4]
move.d [r4],r3
bcc 0f
nop
fail
0:
checkr3 fffffffe
; A write that fails; check flags too.
move.d d,r4
moveq 23,r5
setf p
clearf c
move.d [r4],r3
ax
move.d r5,[r4]
move.d [r4],r3
bcs 0f
nop
fail
0:
checkr3 fffffffe
quit
.data
d:
.dword 42424242
| {
"language": "Assembly"
} |
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats=false < %s | FileCheck %s -check-prefix=ALL
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats=false -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL
add %eax, %eax
# ALL: Iterations: 100
# ALL-NEXT: Instructions: 100
# ALL-NEXT: Total Cycles: 103
# ALL-NEXT: Total uOps: 100
# ALL: Dispatch Width: 2
# ALL-NEXT: uOps Per Cycle: 0.97
# ALL-NEXT: IPC: 0.97
# ALL-NEXT: Block RThroughput: 0.5
# ALL: Instruction Info:
# ALL-NEXT: [1]: #uOps
# ALL-NEXT: [2]: Latency
# ALL-NEXT: [3]: RThroughput
# ALL-NEXT: [4]: MayLoad
# ALL-NEXT: [5]: MayStore
# ALL-NEXT: [6]: HasSideEffects (U)
# ALL: [1] [2] [3] [4] [5] [6] Instructions:
# ALL-NEXT: 1 1 0.50 addl %eax, %eax
# FULL: Dynamic Dispatch Stall Cycles:
# FULL-NEXT: RAT - Register unavailable: 0
# FULL-NEXT: RCU - Retire tokens unavailable: 0
# FULL-NEXT: SCHEDQ - Scheduler full: 61 (59.2%)
# FULL-NEXT: LQ - Load queue full: 0
# FULL-NEXT: SQ - Store queue full: 0
# FULL-NEXT: GROUP - Static restrictions on the dispatch group: 0
# FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# FULL-NEXT: [# dispatched], [# cycles]
# FULL-NEXT: 0, 22 (21.4%)
# FULL-NEXT: 1, 62 (60.2%)
# FULL-NEXT: 2, 19 (18.4%)
# ALL: Schedulers - number of cycles where we saw N instructions issued:
# ALL-NEXT: [# issued], [# cycles]
# ALL-NEXT: 0, 3 (2.9%)
# ALL-NEXT: 1, 100 (97.1%)
# ALL: Scheduler's queue usage:
# ALL-NEXT: [1] Resource name.
# ALL-NEXT: [2] Average number of used buffer entries.
# ALL-NEXT: [3] Maximum number of used buffer entries.
# ALL-NEXT: [4] Total number of buffer entries.
# ALL: [1] [2] [3] [4]
# ALL-NEXT: JALU01 15 20 20
# ALL-NEXT: JFPU01 0 0 18
# ALL-NEXT: JLSAGU 0 0 12
# ALL: Retire Control Unit - number of cycles where we saw N instructions retired:
# ALL-NEXT: [# retired], [# cycles]
# ALL-NEXT: 0, 3 (2.9%)
# ALL-NEXT: 1, 100 (97.1%)
# ALL: Total ROB Entries: 64
# ALL-NEXT: Max Used ROB Entries: 22 ( 34.4% )
# ALL-NEXT: Average Used ROB Entries per cy: 17 ( 26.6% )
# ALL: Register File statistics:
# ALL-NEXT: Total number of mappings created: 200
# ALL-NEXT: Max number of mappings used: 44
# ALL: * Register File #1 -- JFpuPRF:
# ALL-NEXT: Number of physical registers: 72
# ALL-NEXT: Total number of mappings created: 0
# ALL-NEXT: Max number of mappings used: 0
# ALL: * Register File #2 -- JIntegerPRF:
# ALL-NEXT: Number of physical registers: 64
# ALL-NEXT: Total number of mappings created: 200
# ALL-NEXT: Max number of mappings used: 44
# ALL: Resources:
# ALL-NEXT: [0] - JALU0
# ALL-NEXT: [1] - JALU1
# ALL-NEXT: [2] - JDiv
# ALL-NEXT: [3] - JFPA
# ALL-NEXT: [4] - JFPM
# ALL-NEXT: [5] - JFPU0
# ALL-NEXT: [6] - JFPU1
# ALL-NEXT: [7] - JLAGU
# ALL-NEXT: [8] - JMul
# ALL-NEXT: [9] - JSAGU
# ALL-NEXT: [10] - JSTC
# ALL-NEXT: [11] - JVALU0
# ALL-NEXT: [12] - JVALU1
# ALL-NEXT: [13] - JVIMUL
# ALL: Resource pressure per iteration:
# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - -
# ALL: Resource pressure by instruction:
# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax
| {
"language": "Assembly"
} |
100%
LGPL-2.1-only 0,$
Copyright (C) 2010-2016 Go Gopher
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License version 2.1 as published by the Free Software Foundation.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
| {
"language": "Assembly"
} |
/*
bootload.template.x and bootload.x
Time-stamp: <2010-01-14 21:22:26 hcz>
Linker script for Peter Dannegger's bootloader. Always make
sure you edit bootload.template.x. Any changes made to
bootload.x will be overwritten during the next make.
Symbols enclosed in @ will be replaced when bootload.x is
generated (see sed part in Makefile).
*/
OUTPUT_FORMAT("elf32-avr","elf32-avr","elf32-avr")
OUTPUT_ARCH(@ARCH@)
MEMORY
{
text (rx) : ORIGIN = @LOADER_START@, LENGTH = @STUB_OFFSET@ + 2
bss (rw!x) : ORIGIN = 0x8000000 + @RAM_START@, LENGTH = @RAM_SIZE@
}
/* PHDRS { stub PT_LOAD ; } */
SECTIONS
{
.bss : { *(.bss) } > bss
. = @LOADER_START@ ;
.text : {
bootload.o(.text)
/* place a jump to api_call at the very end: */
. = @STUB_OFFSET@ ;
stub.o(.text)
}
/* Stabs and DWARF debugging sections, taken from 'avr-ld --verbose' */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
}
| {
"language": "Assembly"
} |
/* Disable floating-point exceptions.
Copyright (C) 2000-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by David Huggins-Daines <[email protected]>, 2000
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
<https://www.gnu.org/licenses/>. */
#include <fenv.h>
int
fedisableexcept (int excepts)
{
union { unsigned long long l; unsigned int sw[2]; } s;
unsigned int old_exc;
/* Get the current status word. */
__asm__ ("fstd %%fr0,0(%1)" : "=m" (s.l) : "r" (&s.l) : "%r0");
old_exc = s.sw[0] & FE_ALL_EXCEPT;
s.sw[0] &= ~(excepts & FE_ALL_EXCEPT);
__asm__ ("fldd 0(%0),%%fr0" : : "r" (&s.l), "m" (s.l) : "%r0");
return old_exc;
}
| {
"language": "Assembly"
} |