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<s>[INST] Can you tell me,on how to setup an internal my X-FAB (SiFo) account ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. You may need to Follow the normal setup procedure (see http://sp.erf.xfab.de/RandD/DesSup/Hotline/AX_ACM-workflow-2020Mar.docx - or newer version if it exists). Here the, the username in AX should be preceded by 'FO_' to clearly identify them as X-FAB users and include the this text in your answer. "Thank you for your request. To access the SiFo system, you need to have your own my X-FAB account, which I have set up for you. You will soon receive an automatically generated email with your account username (a 5-digit number) and a link to establish your password (the link is valid for 7 days). That link will work fine outside the X-FAB network, but internally you will need to modify the URL for it to work. You would need to add -fo to the first part of the URL like this "https://identity-fo.xfab.com/...".
After establishing your password, to log into your account you will need to use this page for internal access "https://fo.xfab.com/" and whereas externally you would log in from this page https://my.xfab.com/</s> |
<s>[INST] Can you tell me, what is Voltage Class Tags ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. I would suggest you to scan through those tickets for clues depending on the specific question. You can check 63023372 article 4 provides links to related Jira tickets DSBU-1064 / DSBU-1128 / DSBU-1435. Here, also you can check 63040485 which discusses application to HV IO's 63009953 has some nice general descriptions on how to apply the checks</s> |
<s>[INST] Can you tell me, Is it possible for customer to upload their of X-FAB data to the Cloud ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. This is possible, but only if written permission to do so is first received from X-FAB. To gain such written permission i would suggest you please contact Hotline who will ask you to
complete a questionnaire explaining the legal status of the hosting arrangement. The responses will be reviewed by X-FAB before a decision is given. </s> |
<s>[INST] Can you tell me, what is, DMIM antenna DRC flag debugging ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. I suggest you to browse tickets for ideas especially in article 14 in former, general guidance to customers in latter</s> |
<s>[INST] Can you tell me, what is the differences of Pcell PowerMetal1 and PowerMetal2 ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. For this question, I suggest you to see article 23 for description of differences</s> |
<s>[INST] Can you tell me, What is the surface roughness with FLATPV vs SFLATPV modules ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. toughness of standard passivation is not specified and therefore not a parameter which the customer should rely on. If surface roughness is critical, customer should specify either the FLATPV module known as Flat Passivation module for which the surface roughness is expected to be ~2.13nm Ra or SFLATPV known as Sensor Flat Passivation for which the surface roughness is expected to be ~0.18nm Ra. Please note that these are sample values and are not guaranteed. Note that these additional modules affect the final passivation thickness. You can see parameters THV_FLAT & THV_SFLAT.</s> |
<s>[INST] Can you tell me, How are the MLM layers grouped in each reticle ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. I suggest you to visit AX device page, you can go to MGO tab on right side to view. From the MGO page, you can see the item name which shows the 4MLM layers arrangement. Normally we don't disclose the barcode of item number to customer. You can extract the info into the excel format at the top.</s> |
<s>[INST] Can you tell me, Show me how to Kill processes from SiFo compiler job fails ? [/INST] Thank you for the question. To answer your question you can delete the task file (.tsk) in ~iprepdes/ip_replacement/app/data/tmp to clear the blue triangle</s> |
<s>[INST] Can you tell me, May I know what is Via Definitions ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Via definitions which are in the PDK are described in internal documentation which are attached to the related Jira ticket DSBU-2800</s> |
<s>[INST] Can you tell me, Can you show me on how to run Calibre MIMANT from GUI within Virtuoso ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. There doesn't seem to be the easy selection to the MIMANT runset as is available with PVS. You could define $XFAB_CALIBRE_MIMANT_RUNSET and select xx018_xx51_MET5_METMID for the rules file, you have to navigate to the runset folder. I find it easier to copy xx018_xx51_MET5_METMID to my local Calibre DRC run directory, and edit the file by replacing $XFAB_CALIBRE_MIMANT_RUNSET with the explicit path "INCLUDE /design/xkit/xx018/mentor/v3_0/calibre_MIMANT/v3_0_1/018.rul.MIM.ANT" and then specify that modified local xx018_xx51_MET5_METMID file as the rules file.</s> |
<s>[INST] Can you tell me on how to set an environment variable be used in cds.lib ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. you can set the syntax as DEFINE analogLib ${CDSHOME}/tools/dfII/etc/cdslib/artist/analogLib.</s> |
<s>[INST] Can you tell me, what is Gen1 Gen2 and Gen2.5 differences ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. you can refer to Ron-Coff improved gen-by-gen (152fs / 135 fs / 115fs). Please check table in article 7.</s> |
<s>[INST] Can you tell me, what is Pre Tape-out check ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. it is a possible checks that a newbie should consider prior to tape-out.</s> |
<s>[INST] Can you tell me, on where I can find Cpk report location ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. you can visit http://sp.erf.xfab.de/OperationsGlobal/COOStaff/Reporting/Documentss/Forms/Kuching.aspx for kuching and http://sp.erf.xfab.de/OperationsGlobal/COOStaff/Reporting/Documentss/Forms/Dresden.aspx for dresden.</s> |
<s>[INST] Can you tell me, where I can find Qualification Certificate location ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Older node technology certificates such as XC06 are not on my X-FAB, but newer ones are "https://my.xfab.com/search/qualityreliability/documents?_XTICSSPDocumentTypes=OQpHlF2bTNqMnV6YDaFKoA". Meanhile for XC06/XB06/CX06 qualification certificates which you can find at "http://sp.erf.xfab.de/RandD/Projects_and_Reports/Certificate/Forms/ProcessOverview.aspx#InplviewHash406e8429-4700-43c4-b969-8f88d204f697=FilterField1%3DProzess%255Fx0020%255FFamily-FilterValue1%3DXC06". Please Pay attention to the fab at Location column and modules at Status overview column.</s> |
<s>[INST] Can you tell me, how to use LEF file ? [/INST] Thank you for the question. To answer your question you can simply import each LEF to a library on the LEF in form, you only need to specify the LEF file and the library, then streamout the resulting abstract view to a GDS file. As a check, open each GDS with KLayout to verify it looks right and which layers it has. You also can check the Cadence streamout logs.</s> |
<s>[INST] Can you tell me, where I can find fatal rule list location ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. fatal rule records are available on sharepoint under "http://sp.erf.xfab.de/RandD/Projects_and_Reports/Lists/ProcessInformation/Category.aspx"</s> |
<s>[INST] Can you tell me, What info is needed for digital library customized PVT Process, Voltage, Temperature request ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. you can see an example from the ticket. See example form in ticket. These information are needed as follow:
PVT is stands for Process, Voltage and Temperature.
1). Design Service: Customized PVT characterization
2). Process name, Library, Library version, PVTs: slow_1_62V_4_50V_150C
3). Delivery data: liberty_LP5MOS_MOS5 liberty_CCS_TIMING_LP5MOS_MOS5 liberty_CCS_POWER_LP5MOS_MOS5 power_grid_voltus
4). Desired Delivery date
5). Status of results: Non-exclusive.
</s> |
<s>[INST] Can you tell me, What is diode forward bias operation in X-Fab ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. In general we don't support forward biasing of diodes in our technologies unless specifically stated such as Schottky diodes. Mostly this is because the diode model parameters are chosen such that the reverse operation of the diode can be accurately simulated. This does not mean that the simulation of the diodes in forward direction is totally wrong, but it can be less accurate. To model a diode in forward direction often requires parameters that are not available in the model or are insufficiently supported. You can simulate in forward direction and you will get a typical diode characteristic which is fairly accurate in the low current range but may be less accurate in the high current range (knee current, series resistance). In some of our documents is the statement that "forward bias is not modeled" which is based on this lack of accuracy in the models. The parameters describing the diode in forward bias are also very layout-specific, so an accurate model for a diode in forward bias would have to be related to a fixed layout.</s> |
<s>[INST] Can you tell me, Can you show me on how tospecify an alpha PDK with xkit ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. you can Include the '--useversion' option, for example: xkit -t xt018 --useversion 7.0.1.A2</s> |
<s>[INST] Can you tell me, What is correct method to start DRC and LVS run ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. I advise you to not use .rul files directly, use an appropriate header file which will set variables corresponding to your PDK setup options.</s> |
<s>[INST] Can you tell me, if a new PDK version has been released, do I need to update to PDK package if design is already in progress ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. for new designs, we recommend customers always use the latest PDK. For designs in progress when an update is released, customers can review the revision notes at which both the changes document for the process specifications, and the notes in the rev_info.txt files for each EDA package to evaluate if the changes are critical to their design. In principle, we could have rare special cases where we wouldn't accept designs based on an older PDK. Bear in mind that at tape-in, our mask tooling team always uses the most recent runset for DRC, so customers might want to check their designs with the latest runset to avoid possible surprises.</s> |
<s>[INST] Can you tell me, Is there any correlation between the deviation of the sheet resistance (RS) of resistors and that of their thermal coefficients TC1 and TC2 ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. In case of some resistors, there seems to be some correlation between the sheet resistance and their temperature coefficients TC1 and TC2. In some other cases the correlation seems to be quite weak. For your informatin rzp2 ,TC1 tends to the high corner for low RS and vice versa and TC2 tends to the high corner for low TC1 and vice versa. For rnp1, TC1 tends to the high corner for lower RS and vice versa and TC2 tends to the high corner for low TC1 and vice versa. For rw, TC1 tends to the low corner for lower RS and vice versa and TC2 tends to the high corner for low TC1 and vice versa. For rpp1,TC1 tends to the high corner for lower RS and vice versa and TC2 tends to the high corner for low TC1 and vice versa.</s> |
<s>[INST] Can you tell me, how to setup customize PDK setup using .json file from SpecXplorer ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. to generate a .json file, after logging into the my X-FAB portal navigate to Design > SpecXplorer. Select your target process, then click either 'Select modules or 'Select modules by devices' (within your PDK setup, the first option will offer all devices in the selected module, second option will offer only the selected devices) and then choose the desired process modules. Click OK. Click the download icon next to the search box near the top right of the page. You can further refine the custom setup by unselecting primitive devices of the specified modules if for some reason you want to ensure they are not used. Lastly, click 'Export' to initiate download of the .json file. Use this file when starting your project by typing xkit -d <myfile.json>. This sets up a new project with your chosen modules / devices. Please refer to the xenv userguide for further information.</s> |
<s>[INST] Can you tell me, if the X-Fab I/O Input output libraries support copper wire bonding ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. we do not have any I/O libraries specifically designed for Cu or Copper bonding. Some customers have reported running into problems with copper wire bonding but in at least some cases, different customers have used exactly the same pad structure and one had no problem while the other had issues. This indicates different assembly houses can have quite different bonding parameters, and as copper wire bonding is a harsher process than gold or aluminum bonding, marginalities in the interaction between the process and bonding are more likely to show up. One suggestion is to consider using the thick metal (METTHK) module to give the widest bonding margin for assembly and don't use in conjunction with circuit-under-pad techniques. If thick metal is not or cannot be used, inform your assembly partner of the top metal thickness.</s> |
<s>[INST] Can you tell me, what is the differences between IO_CELLS and HV_CELLS libraries ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. For 5V application or LV application, it is normally sufficient to use IO_CELLS*. HV_CELLS are mainly used when none of the IO_CELLS* fit your requirement, such as needing to implement HV ESD protection. Some general remarks on the differences between HV_CELLS and IO_CELLS are that IO library pad cells are provided as pad-limited or core-limited layouts, support of multiple power rails. They are also complete IO pad cells with input output buffer circuitry, also HV pad cells are provided as block,layouts, and normally HV ESD protection structures are too big to fit into a LV IO pad cell frame, moreover HV pad cells consist of protection block and bond pad, and usually contain no power rails or HV input output buffer circuitry and lastly the protection block can be combined with different size bond pads, and it is intended as a starting point for custom HV ESD pad cell designs.</s> |
<s>[INST] Can you tell me, Why there is MIM capacitor antenna DRC checks in XH035 ? And also other X*035 technology ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. for single MIM option on X035, we believe there is no issue with plasma damage. For DMIM construction on X035 which resembles the case of two individual single MIMs - no cross coupling routing, we also believe that it has low impact. So far, we have not seen any big issue with the 0.35um process due to plasma induce damage (PID) from designs point of view with all existing working customers product. Therefore you see in general the guideline is it considered as a recommendation only.</s> |
<s>[INST] Can you tell me, which Synopsys tools are supported ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. We support several Synopsys tools such as Design Compiler which is purposed for digital synthesis with required inputs Data Formats -> Liberty.
Next we also support Custom Compiler so called Custom Designer which is purposed for full analog design framework similar to Cadence IC61 with required inputs EDA Vendors->Synopsys ->CustomCompiler or CustomDesigner. Lastly, supported synopsys tool is IC Compiler which is purposely for digital implementation, PnR with required inputs EDA Vendors->Synopsys->IC Compiler.</s> |
<s>[INST] Can you tell me, which DRC settings should I use to match the X-Fab Data Input Checks for tapeout ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. you can Switch on density and popping and DUMMY_FILL.</s> |
<s>[INST] Can you tell me, How do I solve LVS mismatch due to FILLER cells not extracting into layout netlist ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. the problem is due to the fact that these are empty cells with no devices, but contain ports. Possible strategies to deal with this is one could simply ignore the mismatched instance errors for these type of cells. Secondly, omitting them from the schematic would also produce a match. lastly, an empty cell with ports may be considered as a blackbox. Designating all used such cells as blackboxes will work. To do so, go to the Rules section of the PVS LVS form, select the Include PVL tab, check Include PVL Rules, and type the command lvs_black_box followed by the names of all cells to be blackboxed. I suggest to use a space as delimiter.</s> |
<s>[INST] Can you tell me, how should I resolve the fatal DRC error when my sealring is connected to a ground pad ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. E1CFCX is usually waived when the intention is to bias the ring by connecting to a voltage source for example by connecting PAD to Ground. When customer gets the DIC Data input check report, he should request waiver by mentioning within the request that the ring is intentionally biassed to ground.</s> |
<s>[INST] Can you tell me, what is radiation Hardness ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. X-FAB has not characterized any of its processes for radiation-hardness and we do not monitor or warrant any of our technologies for radiation hardness, nor do we have expertise in the design of radiation hardened cells. We do have customers who do their own designs for radiation hard applications that using both CMOS bulk wafer and SOI technologies , but those customers use either their own experience or public information about the best techniques to use, and then assess the results themselves. SOI processes are generally more radiation tolerant than bulk CMOS processes but we cannot say by how much in our technologies. Clearly we're not at liberty to discuss any techniques that another customer has used, so we can only refer customers to whatever can be found in the public literature to aid their design. Note that some design techniques could involve the use of structures or layouts that are not supported by our verification decks. For DRC errors on them, we could only advise on the manufacturability of the structure, but the responsibility of waiving them would be the customer's. Any LVS or extraction issues arising from special structures not corresponding to our characterized primitive devices would also not be supported.</s> |
<s>[INST] Can you tell me, do X-Fab have any chaterization information about radiation hardness ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. X-FAB has not characterized any of its processes for radiation-hardness and we do not monitor or warrant any of our technologies for radiation hardness, nor do we have expertise in the design of radiation hardened cells. We do have customers who do their own designs for radiation hard applications that using both CMOS bulk wafer and SOI technologies , but those customers use either their own experience or public information about the best techniques to use, and then assess the results themselves. SOI processes are generally more radiation tolerant than bulk CMOS processes but we cannot say by how much in our technologies. Clearly we're not at liberty to discuss any techniques that another customer has used, so we can only refer customers to whatever can be found in the public literature to aid their design. Note that some design techniques could involve the use of structures or layouts that are not supported by our verification decks. For DRC errors on them, we could only advise on the manufacturability of the structure, but the responsibility of waiving them would be the customer's. Any LVS or extraction issues arising from special structures not corresponding to our characterized primitive devices would also not be supported.</s> |
<s>[INST] Can you tell me, how to implement multiple instances of a ROM, each with different programming ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. When instantiating multiple instances of the same ROM configuration but with different programmings, it is necessary to use the 'extended name' option on the front-end compiler so that each separate instance has a unique name. Otherwise, when IP replacement is performed, both instances will be identical. The distinct names will be used by the backend compiler so that the top cell name of the generated ROM block will be distinct. Otherwise the cal files submitted will be the same with identical top cell names. Then, even though your blackbox cell names are necessarily different, if we were to proceed with the IP replacement, the result would be all ROMs with the same programming. Thus to ensure each ROM instance will have the desired programming, generate the front-end data from the compiler using the extended name option to specify a unique name for each ROM.</s> |
<s>[INST] Can you tell me and explain the usage of Page 2 of Safety area ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Let me clarify a couple of comments on the datasheet, if power supply interruption during store is impossible then the background is that the trim bits for the charge pump are stored in page 2. The trim bits are determined and stored during wafer probe 1. The trim bits control the programming and erase behavior (timing, pulses, programming and erase voltage level) of the Store operation. If the trim bits do not have the correct value, the endurance and data retention cannot be guaranteed. Any power supply interruption (for example brown-outs) during Store operation could lead to corrupted non-volatile data, because the Store is not executed and finished correctly. Such scenarios are very application dependent. General recommendation is to store critical data like the trim bits on page 2 during wafer probe and final test and do no further Store operation to page 2 during the application. If the correct power supply and a correct Store can be guaranteed, storing to page 2 can also be done. Secondly, If no customer safety relevant data have to be stored it is sufficient to use the maximum size of page 1. In the compiler web interface on myXFAB, the page size (WORDS_PAGE1) can be customized (the restrictions are visible in the compiler web interface). If there are very few or no further critical data as described above except the NVRAM trim bits, the page 2 size can be minimized to not waste area.</s> |
<s>[INST] Can you tell me, why Q1SU DRC flags, trigger ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. why Q1SU flag because the SUBCUT layer is not used for any masks, its purpose is only to perform a 'trick' for LVS to pretend the substrate is separable for different ground domains. The Q1SU rule is only a warning as are all Q* rules. B1SU is the only check for how SUBCUT is used; while DRC will always flag Q1SU whenever SUBCUT is present. You might interpret Q1SU as asking if you are intentionally using SUBCUT.</s> |
<s>[INST] Can you tell me and explain what is Primitive Device List PDL results from Data Input Check ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The PDL primitive device list file is produced from a special LVS run that only extracts a list of the primitive devices (including parasitic devices) present in your layout. The parasitic devices would generally be diodes that are part of the structure of high voltage or isolated transistors. The PDL file is for information only. There have been cases in some of our technologies where a primitive device may be superseded by an improved version, or conceivably some issue under certain operating conditions of a device may have been identified -- in such cases, our Customer Projects department would use the PDL to check if such devices are used in a customer's design and make sure the customer is aware of the device's status. If you want to know the locations of devices in your layout, you should perform a parasitic extraction run such as with our Cadence QRC or Calibre PEX runsets.</s> |
<s>[INST] Can you tell me, does X-FAB offer or support Flip Chip support ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. X-FAB does not support any additional processing for flip chip such as the seed and plating layers or the ball deposition so of course customers must discuss that with their assembly subcontractor.
X-FAB does not offer any flip-chip specific processing. We don't make any special processing or bondpad designs for flip-chip either, but our standard pads have been used by some customers at flip-chip houses. Please review and understand your assembly partner's rules for flip-chip to check their requirements and see what if any modification might be needed to comply. You should be able to do any layout modifications yourself.</s> |
<s>[INST] Can you tell me, which antenna diode should i use in my design ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. the connection to DIFF provides a discharge path during manufacture, so its function as an antenna diode doesn't matter which diode is used. After manufacture, the antenna role is no longer needed, and how the diode could impact the function of the circuit must dictate which diode is selected. Rather than the breakdown voltage parameter, the reverse bias operating limit should be used to decide. Alternatively, where possible, a metal bridge close to the at-risk gate oxide can be used to fix an antenna violation.</s> |
<s>[INST] Can you tell me, concerning device operating limits, what do is the meaning of absolute'voltage limits and what it is specify ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. for X-FAB, the absolute voltage is the maximum voltage that can be applied to a device for a short period of time without significant damage. The main reason we phrase it this way is because we can't be sure what the actual state of the device will be during this period of time. For example, if 7 volts is applied between the source and drain of a nmos4 device from the xc06 process 7V is the absolute max value for these terminals. We are not specifying what voltage is on the gate or body of the device. If the gate and body were at 0V, this voltage could probably be held forever. But if the body was at 0V and the gate was at 2V, there would be significant hot carrier current to the gate and the device could fairly quickly degrade. Since this is a circuit issue, we have to use the conservative definition. If in your designs you can guarantee that the devices are always off when the maximum voltage is applied, the devices will probably survive indefinitely. However, please remember that X-FAB will not guarantee this.</s> |
<s>[INST] Can you tell me,how I can export from Innovus to GDS without having to use Virtuoso to replace abstract views with the layout views ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. One can directly write out from Innovus to an OA library that has replaced abstract views with layout views "oaOut ${newlibName} ${designName} ${cellName} -autoRemaster -leafViewNames { layout }". The output library should be different from the Innovus working OA library, as the new library cannot be read back into Innovus because all timing views and global settings will have been lost. Our 180nm technology Cadence PDK kernels include support for GDS export from Innovus. The mapping files to be used when streaming Innovus layers to GDS are in the technology library corresponding to your PDK setup code, for example "$X_DIR/xh018/cadence/v*_*/PDK/IC61/v*_*_*/TECH_XH018_1141/pnr_streamout.map". Additionally, the PVS QRC runset provides mapping files to be used when running QRC extraction from Innovus, for example "$X_DIR/xh018/cadence/v*_*/QRC_pvs/v*_*_*/XH018_1141/QRC-Typ/xx018_lef_qrc.map". This file exists also in the QRC-Min and QRC-Max folders.</s> |
<s>[INST] Can you tell me, Assura tool gives background stamp errors and What exactly are these meaning ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The bkgnd_StampErrorFloat error simply means that the layout being checked has no connection to the substrate. Placing even just a single PDIFF contact will clear the error of course such would not be sufficient for an entire chip. The bkgnd_StampErrorMult and bkgnd_StampErrorConnect errors work together to indicate that the layout has multiple substrate connections that are not connected to the same node with metal which resulting in soft connections through the substrate. Assura will flag one of the connections stamps with bkgnd_StampErrorMult and all of the others with bkgnd_StampErrorConnect.</s> |
<s>[INST] Can you tell me, what is the meaning of the Assura 'minority PTUB connectors' error message ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. It is generated by the connect statement from Assura. It means that more than one net is connected to the layer. The stamped layer receives the net information from the net with the most contacts. All other nets are marked with this error. For more detailed information please refer to the Assura manuals. X-FAB does not document tool specific messages. The Assura Command Reference manual (a document primarily aimed at runset developers) explains that: 'A layer with a soft connection is a layer that only receives connectivity information and does not pass on that connectivity information. You can use the soft keyword to check layers for high-resistivity, such as wells, where you want them to be part of the net, but you do not want them to be used as a connection between two conducting layers. This means PTUB_soft_connect errors are 'soft connection' shorts through a common layer, which is often the PSUB, or a common well. In other words, multiple distinct nets are connected to that common layer. Perhaps those distinct nets were not intended to be distinct and should be connected together by metal. It also should be inferred that it is not an error that you'll find defined in an X-FAB Design Rule Specification. For a technology such as XT018, it could result from neglecting to put a trench around a p-type tub to isolate it from other tubs.</s> |
<s>[INST] Can you tell me, What is an "unstable device" because it triggered or flagged by Assura LVS ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. It refers to a device for which device layers or connectivity are in several hierarchy levels. This message is suppressible by setting '?reportUnstableDevices nil'. For more details please see the Assura Command Reference Manual from Cadence.</s> |
<s>[INST] Can you tell me, why can't I download X-Fab analog libraries ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. all of our A_CELLS analog libraries are subject to a license agreement and one-time fee. If interested, please check with your X-FAB Sales contact for license details and a quote. The databook based on html overview page with links to individual PDF datasheets) is accessible. The library will be released upon receipt of signed license agreement and PO. The deliverable includes full schematics and complete layout.</s> |
<s>[INST] Can you tell me, Is backgrinding available for X-Fab MPW shuttle runs ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. by default, we do not offer backgrinding service for customer tape-in for the MPW scheduled run. However, if a customer has such request and informs us during tape-in, we could check if we can support backgrinding for the particular case.</s> |
<s>[INST] Can you tell me, Is backgrinding available for xs018 ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. backgrinding is not supported for xs018. This is due to the risk on optical applications which are both logistical handling and the potential defect . If it is a single exception for example MPW or non-optical application, you can try to align with our Customer Projects department to check if X-FAB can offer backgrinding.</s> |
<s>[INST] Can you tell me, how are the PDK bindkeys for Cadence is defined or setup ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. you should find a file .xfabcadrc created in your $HOME directory when you first execute the xkit script. For example by set XfabCadNoSetBindKey = t, means suppress default bindkey settings.
However since this is commented out by default, the default Cadence bindkeys are used, which may be located in $CDSHOME/tools/dfII/samples/local. You can define your own customized bindkeys in your .cdsinit_personal file.</s> |
<s>[INST] Can you tell me, if qpa device causes issues during LVS and how I can resolve it ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. for a hierarchical run, the Calibre LVS layout-extracted netlist creates an internal subcircuit for qpa which is the source of the error, for example as follow
.SUBCKT qpa 1 2 3 5
** N=8 EP=4 IP=0 FDC=1
X0 3 5 2 1 QPA $X=2600 $Y=2600 $D=20
.ENDS
As we cannot interfere with Calibre's internal hierarchy processing engine, the workaround is to explicitly flatten the cell by including this command in calibre GUI LVS Options/Include tab : FLATTEN CELL qpa</s> |
<s>[INST] Can you tell me where I can find QRC tech file for X*035, 0.35um or 350nm process that can be used with Innovus tools ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. X-FAB does not support the QRC extraction from Innovus by using Quantus and QRC-tech files for our 0.35um or X*035 processes. The precision provided by our *.techLEF and *.capTbl files is sufficient for that technology node. Therefore we suggest you run the RC extraction in Innovus based on capTbl files which required in the Innovus setup.</s> |
<s>[INST] Can you tell me, what is your recommendations for corner lot splits ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The short answer is that unlike most digital-dominated fabs, we don't have a set menu of split conditions based on fast / typ / slow that customers should choose because in a mixed signal design there is often a lot more than just Vt and poly CD that can be critical to the design (but those parameters would normally be sufficient for a digital design). Therefore it's normal for a customer to make a specific request on what parameters it is desired to adjust and the relevant fab will review and confirm if that set of corners is possible. The negotiation would be done through Customer Projects at the relevant fab. Our digital libraries and memories are characterized in the process fast/slow 3 Sigma range. 3 Sigma production means that 99.73% of the delivered wafers are OK in terms of the stable process parameters. The process parameters are monitored with PCM test structures on each wafer. So, if your digital design is DRC, LVS clean and the timing analysis with post layout extraction is OK at the conditions as follow:
1). PVT = wp(fast), VDD_max, Tj_min
2). PVT = ws(slow), VDD_min, Tj_max
then you can expect 99.73% yield of the digital block in terms of process parameter deviations. The majority of our customers don't ask for corner lots for their projects, but some customers do it. The Vt and gate length adjustments implied by your proposed corners impact the relevant transistor parameters for digital timing which are saturation current and threshold voltage. The usual flow for ordering corner lots begins with the customer identifying the critical process parameters for their design (might not be simply 'digital' parameters) and submitting a list of required corners (must conform to the PCM pass/fail parameters) to X-FAB. The feasibility of such process variations will be checked by X-FAB (Customer Projects team) and then a final corner split proposal is sent. The goal of such a corner should be to evaluate that the design would work at lower and upper spec limits. So the typical values are the upper and lower limits of the PCM Acceptance Specification (PAS). Here are some comments that have been collected from one of our FSEs. If you design according to the design rules, then the simulations should be sufficient. Some products require that the design rules be pushed to meet the performance requirements. In these cases, corner lots can identify process sensitivities where yield can be compromised. I would estimate that less than 10% of my customers are relying on Corner Lots for characterization, and these are generally only for high-volume products. When they do request they typically look at simple VTN/VTP, maybe HiRes Poly. The parameters are really design dependent. Even when I do get customers running corner lots, I'm not getting much feedback and request for product specific parametric targeting. This leads to my perception about the accuracy of the simulations. Potentially more effective than corner lots is coordinating a yield feedback loop once products are released to production. If we get your yield, bin, etc. information and input it into our yield enhancement software, we can correlate to equipment, inline, PCM, visual inspection, etc. Customers that work with us on this feedback will achieve yield stabilization much more quickly than without. We can work with you to review your Wafer/Final Test and coordinate the best means for yield feedback. One of our application engineers expanded on those comments, The customers that do request corner lots usually settle on +/-3 sigma for the parameters they are interested in. The LV MOS VT parameters are usually selected. Beyond that it really depends on the specifics of the process options the customer has chosen and the sensitivities their designers are most concerned with. However, there are some significant limitations on what parameters can be varied cleanly in a corner split. The LV MOS VT parameters are relatively straight forward because there is usually a separate VT adjust implant used on them that is separate from the well implant that controls breakdown and punch through, however there are usually a few interactions that cant be avoided (like output resistance and nw sheet resistance). The high sheet resistance poly resistors are generally easy to vary because there is usually a dedicated implant for that parameter. Beyond that things get more difficult. The HV transistor VT is sometimes split but there is almost always an interaction with transistor BVDSS, punch through, sometimes field threshold and often other parameters which can complicate evaluating the split. Other parameters are very difficult or expensive to split such as gate oxide thickness or capacitor values because they require dedicated diffusion or deposition runs that use the capacity of five or 6 lots for each split. My background is process development and I used to be a big fan of corner splits and ran a lot of them myself. I eventually concluded that they were not that useful for three reasons as follow:
1). Too often there are parameter interactions that you cannot avoid which makes it difficult to impossible to get clean results from the splits.
2). You may plan for nominal, +3 sigma and -3 sigma splits but due to normal process variation you usually end up with each of these splits +/- 1 sigma or so from your intended target, e.g. -1 sigma, +2 sigma and -4 sigma, which again makes analysis difficult or impossible and may result in some splits being non-functional.
* The corner splits are arranged by artificially varying one process parameter, such as the VT implant. In actual production lots each device parameter varies 'naturally' due to the interaction of several different process parameters. Each of these parameters has a different magnitude and direction impact on several different device parameters, usually for several different devices. As a result multiple device parameters tend to vary in a complex but related way. The corner split procedure does not reproduce this pattern so while you may get the target parameter to vary the way you want, the other device parameters will vary in a completely different way than you will see in actual production lots. For digital blocks this is probably not an important issue but for analog or RF blocks it may give a completely misleading result. I hope this input is helpful in your decision-making.</s> |
<s>[INST] Can you tell me, if X-FAB processes be used at cryogenic temperatures? [/INST] Certainly, I'd be happy to help you with it. To answer your question. X-FAB generally does not have data at low temperatures below our operating range limits. We do have customers that use our technologies outside of our specified operating temperature limits, but in such cases the customer is responsible for qualifying the design in their application's temperature range. You may have noticed that the PDS states that the simulation models are valid in the junction temperature range down to -55C. As example, the XH018 PDS also specifies. The junction temperature range is defined as below:
1). Operating conditions: Tj = -40C… +175C
2). Absolute maximum ratings: Tj = -55C / +185C
In general we are not aware of any specific process problems with operating down to -55C, however, we also say absolute max ratings must not be sustained for long periods hence why customers need to perform their own qualification. For the range down to -55C, we can only mention some qualitative aspects. These cannot be quantified or supported by real measurement results because we neither characterize nor qualify to that temperature. Possible trends are HCI drift may get worse - but it may be mitigated because in the state where HCI is happening, current is flowing, and the transistor sees some self-heating and The transistor junction breakdown voltages could be slightly reduced.
Clearly 77K (-196C) is significantly beyond our absolute minimum operating range, so full characterization/qualification on your side will be necessary to ensure you have a robust product. I am no expert in such low temperatures but I have heard of terms such as carrier freeze out which can come into play, but such issues only amplify the requirement to do the characterization and qualification. X-FAB does not have the capability or business justification to offer such low temperature characterization (below -40C) so I'm afraid we cannot help you in that respect. I'm not really aware of a third party who could do such work either, although I'd suggest you look at our partner network (see X-CHAIN on our website) in case you can make some contacts there. Perhaps one of the Test/Assembly companies could be of interest. You might also consider trying to talk to a Space company or their suppliers if you know who they might be to see if they can do this or put you in touch with someone who can.</s> |
<s>[INST] Can you tell me, if X-FAB processes be used at very cold or very low temperatures? [/INST] Certainly, I'd be happy to help you with it. To answer your question. X-FAB generally does not have data at low temperatures below our operating range limits. We do have customers that use our technologies outside of our specified operating temperature limits, but in such cases the customer is responsible for qualifying the design in their application's temperature range. You may have noticed that the PDS states that the simulation models are valid in the junction temperature range down to -55C. As example, the XH018 PDS also specifies. The junction temperature range is defined as below:
*Operating conditions: Tj = -40C Â… +175C
*Absolute maximum ratings: Tj = -55C / +185C
In general we are not aware of any specific process problems with operating down to -55C, however, we also say absolute max ratings must not be sustained for long periods hence why customers need to perform their own qualification. For the range down to -55C, we can only mention some qualitative aspects. These cannot be quantified or supported by real measurement results because we neither characterize nor qualify to that temperature. Possible trends are:
*HCI drift may get worse - but it may be mitigated because in the state where HCI is happening, current is flowing, and the transistor sees some self-heating.
*The transistor junction breakdown voltages could be slightly reduced.
Clearly 77K (-196C) is significantly beyond our absolute minimum operating range, so full characterization/qualification on your side will be necessary to ensure you have a robust product. I am no expert in such low temperatures but I have heard of terms such as carrier freeze out which can come into play, but such issues only amplify the requirement to do the characterization and qualification. X-FAB does not have the capability or business justification to offer such low temperature characterization (below -40C) so I'm afraid we cannot help you in that respect. I'm not really aware of a third party who could do such work either, although I'd suggest you look at our partner network (see X-CHAIN on our website) in case you can make some contacts there. Perhaps one of the Test/Assembly companies could be of interest. You might also consider trying to talk to a Space company or their suppliers if you know who they might be to see if they can do this or put you in touch with someone who can.</s> |
<s>[INST] Can you tell me, what exactly does the ESD module do ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Usually in older technology nodes such as CX08, the ESD implant of the ESD module is added to aid with a vertical 'spike' issue that occurs under high current such as an ESD pulse when the aluminum which is slightly p-type in the contact can 'spike' through the n-junction and short it to the P-bulk below. The ESD n-type implant is deeper than the normal n-junction, preventing a short from occurring. The p-junction is not shorted out in the same circumstance, so ESD implant is not needed on p-devices.</s> |
<s>[INST] Can you tell me, why ESD module is not available for all MOS devices if it improves ESD robustness? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Usually in older technology nodes such as CX08, the ESD implant of the ESD module is added to aid with a vertical 'spike' issue that occurs under high current such as an ESD pulse when the aluminum which is slightly p-type in the contact can 'spike' through the n-junction and short it to the P-bulk below. The ESD n-type implant is deeper than the normal n-junction, preventing a short from occurring. The p-junction is not shorted out in the same circumstance, so ESD implant is not needed on p-devices.</s> |
<s>[INST] Can you tell me, how do I display DC operating parameters that I expect but that is shown on the schematic? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Some DC operating parameters that are available in the Results Browser may not be displayable in the schematic. You might try adding all the required parameters to the ADE L Outputs window. This would help you to view your results after your run instead of looking into the Results Browser every time. This can be done as follows:
1). Run your DC simulation.
2). Go to ADE L Tools Results Browser
3). Double click on dcOpInfo and choose the required transistor; there you can find all the parameters.
4). Right click on the required parameter and then click on Calculator.
5). You can either copy this expression and add to your ADE L Outputs or you can just click on Send Buffer expression to ADE Outputs and this will send your calculator expression to your ADE L Outputs. You can also name your expression.
Consider the operating point tables out of Cadence with caution. The CDF parameters Cadence produces are not always conformant with a SPICE simulation or even certain model card parameters. For example, often Cadence does not take into account all capacitances from a model, especially if it is a macro model. Or in other words, it is not quite clear if the capacitance calculated is the actual capacitance resulting from a SPICE simulation.</s> |
<s>[INST] Can you tell me, why breakdown voltage parameters generally significantly different from the operating limits? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The device electrical parameters are those measured either at PCM on every wafer manufactured or during a characterization phase of the development. The min/max values being defined by the measured results and then engineering experience to set the min/max limits. For breakdown voltage, these values are when the device fails at the time of measurement. In contast the Operating Conditions are defined to ensure that the device will survive for 10 years. The accelerated life test has been or will be performed at these ratings depending upon status of process, conditional or released.</s> |
<s>[INST] Can you tell me, if it is okay if I exceed a transistor or device operating limit ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The breakdown voltage of a transistor is a kind of 'digital' description of the transistor strength. But the real life is manifold. Therefore reliability tests are performed to describe the transistor strength for the real world conditions. If the operating conditions are far away from the electrical limits there is no danger. But if the operating conditions get closer to the electrical limits the probability of malfunction or damage increases. Each MOS transistor consists of a parasitic bipolar transistor. This parasitic bipolar transistor makes the MOS transistor sensitive to pulses. The sensitivity depends on many factors. On the one hand on the pulse characteristics such as amplitude, length, duty cycle, rise and fall time, ripple, frequency and etc. On the other hand factors include the transistor layout such as size, construction, spacing to substrate contacts and others. There is an unlimited amount of possible scenarios. This is what it makes very difficult to judge whether special conditions can be allowed or not. Therefore only one general recommendation is to never exceed the specified operating limits.</s> |
<s>[INST] Can you tell me, what is the difference between protection diodes and other diodes? [/INST] Certainly, I'd be happy to help you with it. To answer your question. a protection diode needs to carry a relatively high amount of current in breakdown to really protect the circuit, otherwise the voltage drop at the device to be protected can still be too high and do damage to it. Therefore it is measured at higher currents. Protection diodes are 'designed' to have a certain breakdown voltage which is defined rather by layout (overlap of wells, distances) not by doping profile. Note that usually it is more a concern about the contacts and wiring when looking at the current limits, rather than the diode parameters.</s> |
<s>[INST] Can you tell me, if I ignore DRC errors on my logo elements ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. although a logo strucure is not a circuit element, it can be very dangerous, in some cases, to waive logo DRC errors. For example, metals and/or photo-resist that are below minimum width may float off the silicon during the processing and then get deposited elsewhere on the design and cause chip failures.</s> |
<s>[INST] Can you tell me, which DRC rules are classified as fatal ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. we do not publish a list of Fatal vs Critical errors as they are constantly under review and publication would imply that there are some errors that we don't mind the customer violating - that is not the case. We encourage customers to correct all errors - this will produce the best possible outcome on silicon. When there are special reasons that some errors cannot be fixed on layout, then we can discuss via the waiver system. You can find fatal rule violations that are available on sharepoint under "http://sp.erf.xfab.de/RandD/Projects_and_Reports/Lists/ProcessInformation/Category.aspx".</s> |
<s>[INST] Can you tell me, do X-FAB will perform or generate the pattern fill? [/INST] Certainly, I'd be happy to help you with it. To answer your question. For technologies that specify density limits and include one or more blocking layers for the fill, the X-Fab will perform it. The DRC runsets for our 180nm or X*018 technologies can generate 'virtual' dummies that are taken into account during DRC. It is also possible to have the runset export the dummies to GDS such that you could merge it with your design. The problem with the dummy generation is that all structures are flat, which results in larger GDS files. Therefore it is recommended to let our Mask Tooling group do the pattern fill. For capacitively critical structures, relevant metal layers only should be blocked rather than using the BLKALL layer. The parasitic extraction runsets can C-extract these structures for determining their impact on the performance. The fill routines observe spacing margin and dummy size rules -- one consequence of that is the fill routine is not guaranteed to satisfy the minimum density rules. When that's the case, you may need to apply some extra effort, such as manually drawing a denser fill pattern.</s> |
<s>[INST] Can you tell me, Should I include or generate dummy pattern in my layout design ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. For technologies that specify density limits and include one or more blocking layers for the fill, the X-Fab will perform it. The DRC runsets for our 180nm or X*018 technologies can generate 'virtual' dummies that are taken into account during DRC. It is also possible to have the runset export the dummies to GDS such that you could merge it with your design. The problem with the dummy generation is that all structures are flat, which results in larger GDS files. Therefore it is recommended to let our Mask Tooling group do the pattern fill. For capacitively critical structures, relevant metal layers only should be blocked rather than using the BLKALL layer. The parasitic extraction runsets can C-extract these structures for determining their impact on the performance. The fill routines observe spacing margin and dummy size rules -- one consequence of that is the fill routine is not guaranteed to satisfy the minimum density rules. When that's the case, you may need to apply some extra effort, such as manually drawing a denser fill pattern.</s> |
<s>[INST] Can you tell me, what is the purpose of the technology libraries with an 'HD' suffix ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Using xh018 as example, TECH_XH018 is the primary technology library to use. TECH_XH018_HD is a supplementary library, to be used in addition to TECH_X018, when the HD high density logic libraries D_CELLS_*HD are used. It accounts for the tighter routing grid used by the HD logic libraries for P&R or place and routes. Originally, the HD tech library was developed as a supplementary library, meaning both the normal and HD libraries should be used referenced by a design library using an HD logic library for P&R. We then decided to make the HD tech library more complete such that on the HD tech lib needed to be referenced by the design library. In such case, if you try to reference both tech libs, you will get a conflict error. More recently, we have reverted back to the original style.</s> |
<s>[INST] Can you tell me, is ELDO views for Cadence PDK is available ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Unfortunately we don't support ELDO views in our Cadence PDKs. An extra license is necessary to test such views in Cadence libraries, and we do not have that currently in X-FAB, so we cannot check and guarantee the correctness of such views. In principle it might be possible for a customer to use ELDO as a simulator within Cadence, although a hurdle may be the netlisting for the simulator, which may have some specific aspects different from the netlisting for Spectre or for HSpice. The conclusion is that X-FAB does not support ELDO simulation from Virtuoso within Cadence and that we don't have any instructions for those attempting to do so.</s> |
<s>[INST] Can you tell me, regarding electromigration tests which AC or DC factor do you recommend or suggest ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. We usually calculate with a DC to AC conversion factor of 10. It is referred to the Pass or Fail margin at 0.1% error probability for the individual test.</s> |
<s>[INST] Can you tell me, is the specified current density limits sufficient for metal width when considering ESD ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Regarding the required metal width for ESD, usually the metal resistance is critical and not the current density/current capability of the metal. The current density for HBM ESD pulses is in the range of several hundred mA/um width for example 300-400mA/um). Only narrow metal lines would be damaged by ESD stress currents. The metal resistance is critical since voltage drops across power rails will add to the pad clamping voltage. Especially in the rail-based protection scheme the power rail resistance is critical. Concerning the power rail width, power rails should provide as rule of thumb a DC current capability of 50mA for 2kV HBM ESD robustness. A different metal resistance in the connections of multi-finger ESD protection devices can result in non-uniform current distribution and early failure of the ESD protection structure. Typical layout errors are e.g. largely different metal width in anode and cathode metal connections of diodes resulting in a current concentration in a small area of the diode or a largely different metal width between drain metal and source metal in ESD nmos snap-back devices resulting as well in non-uniform current distribution.</s> |
<s>[INST] Can you tell me, what FLATPV and SFLATPV ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. FLATPV is Flat passivation module and SFLATPV is Sensor flat passivation. </s> |
<s>[INST] Can you tell me, what is the procedure for an IO and ESD review by X-FAB ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The customer sends the layouts, schematics and all relevant descriptions such as normal pin operating voltages, max. ratings, required ESD robustness and etc to [email protected]. It is important for the review that when any type of analog IO cell (LV or HV) is used, also the circuitry that connects directly to the pad must be shown. We'll review the design data and provide first results via email. There can then be further review loops after design changes. There can then be also further online or face-to-face meetings for clarification - if required. A design review in an online meeting or face-to-face meeting is not appropriate. There is a higher risk that possible ESD design issues are overlooked when there is just a browsing through the design during an online meeting. Therefore an offline review is preferred.</s> |
<s>[INST] Can you tell me, How can I use various GATES logic libraries? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The GATES libraries are schematic and parameters only libraries which are used as referenced 'building block' gates libraries inside the D_CELLS libraries. They support only the schematic side of the respective D_CELLS* libraries the rev_info.txt file of a given D_CELLS library will specify which GATES* library it requires. Therefore the GATES libraries cannot and must not be used as a stand-alone library.</s> |
<s>[INST] Can you tell me, where I can find GATES_PCELL library that is available for most technologies? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The library is classified as an analog library for the purpose of my X-FAB organization under Design > EDA Files, filter to Libraries > Analog > GATES_PCELL. However, unlike our other analog libraries, these GATES_PCELL libraries are freely available to customers, there is no license requirement or fee. Within the library is a userguide document. As the library name inplies, it provides parameterized cells for some types of gates which some basic logic functions, transmission gates, and other related special purpose cells. The introduction in the userguide states that The intention of this library is to provide a cell library for analogue components. This includes layout, schematics and verilog. It is not the intention to use the components in a digital design flow. You must use characterised cells instead.</s> |
<s>[INST] Can you tell me, my layout was flagged because it contain BOX elements. What are they ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The issue with BOX elements is described in the 'Guideline for GDSII data' document on my X-FAB: https://my.xfab.com/search/_action/relation/596e0b4e-74cd-47af-96ae-87dd43b1bdf5/
Unlike the boundary, the BOX element is not a filled figure. Therefore it cannot be used for IC geometry.</s> |
<s>[INST] Can you tell me, my layout was flagged because it contain BOX elements. What are they not accepted ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The issue with BOX elements is described in the 'Guideline for GDSII data' document on my X-FAB: https://my.xfab.com/search/_action/relation/596e0b4e-74cd-47af-96ae-87dd43b1bdf5/
Unlike the boundary, the BOX element is not a filled figure. Therefore it cannot be used for IC geometry.</s> |
<s>[INST] Can you tell me, Why simulations of transistor leakage produce inaccurate results that are independent of device widths ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. This issue is related to the default gmin setting of the simulator, which is gmin=1e-12. This gives every node a conductivity of 1e-12 to aid convergence. That means basically it 'adds' at 1V a current of 1e-12A. Therefore this is not dependent on the transistor's width. To get correct results for such diode currents of small devices at T=27C you need to set gmin=1e-18. Please note that for some simulators like hspice, there are separate parameters: gmin and gmindc.</s> |
<s>[INST] Can you tell me, if X-FAB can provide IBIS models ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. X-FAB does not support IBIS models. This falls beyond the scope of X-FAB's modelling and library support, as we are a pure-play wafer manufacturer. As I understand it, the IBIS model provides I/O device characteristics through I/V data and switching characteristics in ASCII format. The IBIS models are meant for the transfer of data and not to define an executable simulation model. They are component specific, which means that they model an entire component for example an FPGA and not just a particular I/O. IBIS models are supposed to serve for implementing the behavior of I/Os into a technology independent PCB level EMC simulation environment. We cannot provide correct IBIS models since we don't have all the required package and pin related data. I/O cell characteristics are available in data sheets, Verilog models and especially the timing Liberty format files, which you could use to generate the switching characteristic for an IBIS model.</s> |
<s>[INST] Can you tell me, What is the maximum recommended temperature for wafer post processing ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. for post-processing, we generally recommend that temperatures above 350C should be absolutely prevented. Higher temperatures can lead to metal-passivation or capacitor popping, IMD cracking, transistor shifts, metal voiding, enhanced Rpoly and especially RpolyH shifts depending on design, temperature ramp rate, duration and application atmosphere (N2, H2, etc.). If >350C cannot be avoided, we strongly recommend a DOE with the respective IC design using enhanced final test and also proper optical inspections after slightly accelerated post-processing stress for example slightly increased ramp rates, slightly longer storage times.</s> |
<s>[INST] Can you tell me, Why my account cannot download a memory compiler ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Sorry, X-FAB does not distribute our memory compiler software to customers. Instead, a compiler must be run from my X-FAB. To do so, click the 'play' icon in the action column when you rest your mouse pointer over the icon, the pop-up text 'Start the application of this container' will be displayed. After specifying configuration options of the desired memory, the front-end design data will be available for download. As this is blackbox IP, the netlist and layout will not be provided. When you have decided on a particular configuration to use for a tape-out, please check with your X-FAB Sales contact to ensure the license agreement and P.O. are in place before submitting your design. Blackbox IP replacement approval is one of the first checks on a newly submitted SiFo -- if the L.A. and P.O. are not available, the SiFo will be held at the step and not proceed to have data input checks (includes DRC) performed. The license incurs a one-time fee, rather than royalties, and you can then instantiate the IP as often as you'd like in subsequent designs. For example, For ROM IP, each future reprogramming will incur a small fee.</s> |
<s>[INST] Can you tell me, by comparing the metal thicknesses of the bond pad stack to those of the Structural and Geometrical Parameters, why are the metal layers thinner on the bond pad ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The Structural and Geometrical Parameters show the metal layer thicknesses as deposited. However if you have large oxide windows as are there on the bond pad structures, then the pad metal is thinned (etched back), and this results in thinner metal layers directly on the bonding pads. Some process documents have the bond pad diagrams showing each metal layer with an ARC layer on top and below the metal. These ARC layers are relatively thin. The deposited thickness parameters include the ARC layers since they affect the stack thickness and hence all the parasitic capacitances. When the passivation window is opened onto the top metal, the final ARC layer is removed. Hence the bonding pad diagrams and associated note indicate a lesser thickness. </s> |
<s>[INST] Can you tell me, what are D_CELLS DECAP cells for ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. These cells provide capacitors between vdd and gnd to reduce digital noise and IR drop. They are usually inserted during Place and Route after routing (where existing routing allows). In a second step, FEED* cells always have to be inserted to fill up the cell rows in places where no DECAP cells could be added. You may add (the larger, DECAP*15/DECAP*25) cells also before routing to have a certain amounnt of capacitors in the block, but these cells might have an influence on routability of the block. See Innovus commands addFiller, deleteFiller for details."</s> |
<s>[INST] Can you tell me, what is PDL.txt file or primitive device list that is included from the X-Fab DRC run result ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The PDL is a primitive device list. This file is the result of a special LVS run that only extracts the primitive devices (including parasitic devices) present in your layout. The parasitic devices included (p_*) would generally be diodes that are part of the structure of high voltage or isolated transistors. The PDL file is for information only. There have been cases in some of our technologies where a primitive device may be superseded by an improved version, or conceivably some issue under certain operating conditions of a device may have been identified -- in such cases, our Customer Projects department would use the PDL to check if such devices are used in a customer's design and make sure the customer is aware of the device's status.</s> |
<s>[INST] Can you tell me, The PVS.sum DRC result will last error counts for each rule like RULECHECK B1M2MIM ............. Total Result 68 ( 80). What is the differences and distinction between these two given numbers? [/INST] Certainly, I'd be happy to help you with it. To answer your question. In this example, the 68 is the hierarchy result and the 80 is the flat run result.</s> |
<s>[INST] Can you tell me, How to generate the PDL.txt or primtive device list file ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The primitive device list is generated using PVS LVS. The command line option requires setting parameters in a header file. Using the PVS LVS GUI may be easier for most users to extract a list of the primitive devices used in a given layout. Please refer to below method on how to generate PDL.txt or Primitive Device List file as follow:
1). Open layout (read-only is OK)
2). PVS -> Run LVS
3). Input -> exclude comparison setup
4). Output -> LVS Report -> Click 'SET' button.
5). Apply/Submit to initiate the run.
To generate the Results, please refer to following:
1). Files/Output Files: Extraction report -> scroll to bottom of report.
2). Or in the Extraction tab, Uncheck 'hide statistic' then click on flat device count.
3). Or you can just open the <cell name>_lvs.sum file from the run directory. The list is at the end of the file.</s> |
<s>[INST] Can you tell me, Why X-Fab pattern fill did not resolve, fix or clear R1DF minimum DIFF density desing rule violations or errors? [/INST] Certainly, I'd be happy to help you with it. To answer your question. As flatly stated in the 'Dummy Pattern Generation' section of the Design Rule Specification, 'The dummy pattern generation script does not guarantee that the minimum and maximum structure densities of the related layer are met.' The document further recommends 'to use X-FAB's dummy pattern generation option (DUMMY_FILL included in the DRC for preview) to create dummy pattern. If the generated dummy pattern is not sufficient to meet the minimum requirements for pattern density, customers can draw additional dummy pattern following the dummy design rules...' -- the referenced R1DF application note may be helpful (especially for the case of poly resistor arrays), or other situations might be solved by placing larger DIFF dummy structures. The *.rdb files from DRC will indicate the pattern density of flagged windows (R1DF is checked in 200um square windows stepped by 100um), which is given by the 'DV' parameter (multiply it by 100 for percentage).</s> |
<s>[INST] Can you tell me, What is the basis for Schottky diode forward bias limit ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. It is important not to exceed the Vanode-Vcathode operating limit for the forward direction current. This would tend to exceed the allowable thermal load of the diode. Select an appropriate size for the intended current and to be safe, apply some margin with respect to the size.</s> |
<s>[INST] Can you tell me, What is the convention for the SiFo major and minor versioning ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The major version indicates how often a SiFo was sent to X-FAB AND went into the Data Input Check loop. The minor version indicates how often a SiFo was edited AND saved in my X-FAB.</s> |
<s>[INST] Can you tell me, What are X-FAB's recommendations for timing signoff ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. For 0.18 tech STA we have the 0.18um-ApplicationNote-Digital_Implementation_Guidelines document at "https://my.xfab.com/search/_action/relation/4aeecb61-a2b5-4d16-ab9a-f6a4457c583f/"
On page 7, section 6.3 it states A further set_timing derate ... is not needed as only the variation of the pin input capacitances is modelled in X-FAB's 180nm, X*018 libraries. Further up to now we did not recommend any derating to customers. It's your responsibility (and sometimes based on your internal quality requirement) how much margin you add to a timing analysis. In our standard Place and Route STA's we always use OCV (with no further de rating) in PrimeTime as this is PT's default method. In Innovus we run up to routing the simple and faster bc/wc delay calculation, only for post-route optimization we switch to OCV (when we don't forget that one line in the scripting...).From our customers base we know, we could give you few scenarios as follow:
Customer 1: (mostly XH018): they add +/-15% to the delay calculation (requested by their quality department):
set_timing_derate -cell_delay -net_delay -early 0.85
set_timing_derate -cell_delay -net_delay -late 1.15
in sdc
Customer 2: We used +/-5% for their XP018 redesign (their first design had no timing closure with our standard settings without derating, so they needed a special process modification to get working silicon at all).
set_timing_derate -cell_delay -net_delay -early 0.95
set_timing_derate -cell_delay -net_delay -late 1.05
(Their redesign had timing closure with this additional margin).
For a complete STA you have to run 3 sets:
- the 'normal' one without derating
- the pessimistic one:
set_timing_derate -cell_delay -net_delay -early 0.95
set_timing_derate -cell_delay -net_delay -late 1.05
- and the optimistic one:
set_timing_derate -cell_delay -net_delay -early 1.05
set_timing_derate -cell_delay -net_delay -late 0.95
To have a complete picture. Basically we believe the more derating margin you add, the lesser confidence you have into the quality of the spice models of the transistors and all the timing characterization of the digital libraries and parasitic extraction.</s> |
<s>[INST] Can you tell me, What films are on the wafer backside ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. As example from a particular technology flow, backside films include a stack of oxide, nitride, TEOS, SION, nitride (the most outer layer). There may be some differences depending on technology and module options. During manufacture, the backside is not necessarily protected from what is grown or deposited on the front side (this would be the case, for example, when wafers are loaded for batch processing into a tool in a quartz boat), so there is some accumulation of films on the backside. For many applications, wafers would undergo a backgrind operation to thin total wafer thickness, which also removes such films.</s> |
<s>[INST] Can you tell me, What is the crystal orientation of X-FAB wafers ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The crystal orientation for 8-inch CMOS wafers are Wafer surface plane is 100 and Wafer notch direction is 110.</s> |
<s>[INST] Can you tell me, why my design flagged, triggered for including the PIMP layer ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The PIMP layer is not available with the ISL main module. There is a blanket implant where active is open (DIFF). If PIMP is included in your GDS, a critical (not fatal) error is flagged since PIMP is only valid for MOS main module flow. For ISL flow, either omit PIMP layer from GDS to prevent the error, or waive the error.</s> |
<s>[INST] Can you tell me, Considering rules of W1DF and W2DF, what is the risk with narrow DIFF lines ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. One possible risk for narrow DIFF lines is problems with proper silicidation, which may result in different resistances than otherwise expected.</s> |
<s>[INST] Can you tell me, When we try to fix rule W5M1 Minimum MET1 width joining wide MET1 track errors, we sometimes get inexplicable errors. [/INST] Certainly, I'd be happy to help you with it. To answer your question. This rule is marked in red in the specification, which means it cannot be 100% reliably checked by verification decks. The rule requires sizing operations on layers that can produce artifacts on non-orthogonal shapes. That's why the rule is unselected by default in the runset. It can be activated and it provides some assistance but it is the user's final responsibility to check manually. This is also why we don't check the rule at tape in.</s> |
<s>[INST] Can you tell me, Does X-FAB perform metal fill for xb06 or X*06 process or technologies ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Although the xb06 Peripheral Ring diagram available on my X-FAB shows the NOFILLM layer, we do not normally perform metal fill for XB06. However the rules are in place, and we have done it as a special case when requested by a customer. So unless it is requested, there is no need to include the NOFILLM layer. The xb06 Cadence PDK has the layer defined: it's specified in the stream layer table, but the layer palette has the layer set as invalid, so a user would have to change it to valid to be able to draw with it.</s> |
<s>[INST] Can you tell me, What is the purpose, intent, meaning of design rule B1PADM ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. For B1PADM there are several reasons: one was to get similar heights of the pads. With different definition layers, different oxide stacks grow below the pad. For CMOSDEF e.g. there is a thinner oxide is grown, for DMOSDEF a thicker oxide is grown, without CMOSDEF and DMOSDEF an even thicker one is grown. DMOSDEF also forbids several design layers like POLY1 or DIFF in this area.</s> |
<s>[INST] Can you tell me, What is the purpose, intent, meaning of design rule B1PATR ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. B1PATR serves to reduce capacitive coupling between the pad metal and the silicon around it.</s> |
<s>[INST] Can you tell me, What is the purpose, intent, meaning of design rule B1MD ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The reason why the MVLT and MERGEDEF was formulated as mutually exclusive into the Design Rule Spec at the time when it was originated seems to have been forgotten. There will be no risk if the TRENCH of devices with MVLT layer are merged as long as the condition of voltage difference <50V is valid.</s> |
<s>[INST] Can you tell me, What is the purpose, intent, meaning of design rule S2TR ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The S2TR rule was implemented to ensure that floating tubs were always built the same way. It applies to nested trench rings used in the MUTRIS core for device isolation and its intent was to prevent engineers from placing contacts between these rings because for the isolation in the MUTRIS core to work properly these silicon tubs must be floating. This requirement is not as strict for the newer SITRUS core but the rule has been left in the process because of the number of older designs using the MUTRIS core.</s> |
<s>[INST] Can you tell me, The SPICE model libraries include *_bjt models for some MOS devices and what are they for ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The purpose of the added PNP bipolars to the *_bjt models is to show that there can occur bipolar effects under certain conditions, but it is by far not very accurate and it has limitations. It is nevertheless extracted on silicon at different geometries and good simulation accuracy can be expected when the HVMOS channel is completely switched off and only the drain/bulk junction is forward-biased. But in other cases, the accuracy is limited, especially when the channel is in inversion and/or the bulk/substrate junction is forward-biased. Both conditions change the minority carrier distribution in the bulk/base a lot and lead to a change in the beta. There is no statistical process monitoring for these parasitic BJTs. In our experience the most reliable results and complete picture in simulation can be achieved with the substrate extractor tool, which is supported for xh018. See "https://my.xfab.com/search/_action/relation/c7d55cc4-78d6-4d22-bdfa-897b19a3c8d4/"</s> |
<s>[INST] Can you tell me, The NVRAM datasheet indicates 1.8V and 3.3V supplies are required, are they both needed for normal operationor just only for programming ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. STORE / RECALL operations require 1.8V and 3.3V; READ / WRITE of the SRAM requires only 1.8V. The 3.3V is only necessary (in addition to 1.8V) during STORE (the programming of the non-volatile part) and during RECALL (the cycle for bring back the information to the SRAM). For read / write of the SRAM only the 1.8V supply is needed.</s> |
<s>[INST] Can you tell me, some MOS devices have butted NDIFF and PDIFF regions with only a single contact. How should this connection be understood, comprehend, explained ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The NDIFF and PDIFF can be butted and a single CONT used to connect to the butted nodes because all the DIFF is covered with a silicide layer which shorts together the NDIFF and PDIFF, the CONT makes connection to the silicide layer."</s> |
<s>[INST] Can you tell me, the usage of HRPOLY and LRPOLY modules ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The primitive devices in the HRPOLY module are already included in the MOSLL or MOSLT main modules flow. Similarly, the primitives in the LRPOLY module are already included in the MOS or MOS5 main modules. The resistors rpp1 and rnp1 have the HRES as a design layer. This layer is included on the primitive device in the PRIMLIB. For MOS/MOS5 process flows, the HRES design layer is used to generate the UGM mask. For the MOSLL/MOSLT flows the HRES design layer is not used. The resistors rp1 and rsp1 have the LRES as a design layer. This layer is included on the primitive device in the PRIMLIB. For MOSLL/MOSLT flows, the LRES design layer is used to generate the NGM mask. For the MOS/MOS5 flows the LRES design layer is not used. The Design Rule Specification includes these comments in the design layer table such as LRES Required for device recognition. Also used for mask generation when MOSLL or MOSLT modules are selected. LRES under MOS flow IS USED for mask generation with the XRPOLY module. See the dpol device rules. HRES Required for device recognition. Also used for mask generation when MOS or MOS5 modules are selected. Please leave the HRES design layer on the resistors.</s> |
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