text
stringlengths 211
6.57k
|
|---|
<s>[INST] Can you tell me, What is the differences, distinction between the types of body tied transistors ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. There are two types of transistors available in the XI10 process, the H and A types. The A type transistors use the 'castellated' source/body structure; they have the advantage that they can be made whatever width the customer wants because the body contact is distributed along the source width. However, they have the disadvantage that the N+ and P+ diffusions for the source and body are touching, so there will be biasing limitations for these terminals. The xi10 S/D is not silicided, so at least there is no direct short between the source and body in these transistors, but with the N+/P+ abutment, trying to apply different voltages to the source and body will likely result in either high leakage between the two terminals or outright breakdown as this structure is effectively a surface Zener diode. The H type transistors place the body contacts of the transistors at the ends of the channel and separate the P+ and N+ diffusions by a cross connection of poly to the gate (the designation 'H' transistors comes from the resulting shape of the poly gate). The advantage of these devices is that with the diffusions separated no parasitic Zener diode is formed, so leakage and breakdown between the source and body will not be an issue. The disadvantage of these devices is that due to body resistance perpendicular to the channel, the ratio of W/L is limited for the devices to 6 for the nmos and 12 for the pmos devices.</s> |
<s>[INST] Can you tell me, how should the poly ring of diodes be biased ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Due to its lateral construction, the diode is different from pure bulk junction diodes in other processes.
You might review the Device Characteristics Documentation you can either download the package or browse online by clicking the globe icon to see how the poly ring potential influences the current.
Can check this link "https://my.xfab.com/search/_action/relation/96b7577d-f3b9-40e3-b81f-27cee2e35705/". The 'dn' model is a subckt model consisting of level1 diode models with different ideality factors. In this model the different diodes are used to model the current forward/reverse over temperature. With respect to the diode current the process variation is solely covered by changing the 'is' parameter in the model and the ideality factor is unchanged. Usually the diode current consists of an ideal and a non-ideal part and the ratio of both can change with process variation (the non-ideal part is fluctuating, while the ideal part is very stable). Changing the ideality factor in the model would lead to a large deviation of the current over temperature, which we do not observe, but we only have limited data from a statistical point of view (only lab measurements over T). It is safer to avoid using this device for high precision applications like bandgaps because the forward voltage variation is not measured by PCM test and therefore also the corner models will not be as accurate as needed for this purpose.</s> |
<s>[INST] Can you tell me, What is the handle wafer contact resistance ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. It is in the 10 kOhm range. We do not specify a value because it cannot be measured easily, e.g. from one HW contact to another the handle wafer resistance is in-between, from top to bottom is the thickness of the handle wafer and if not back-lapped the oxide on bottom also. A similar issue exists for XT06; however a contact 'resistance' is specified in the Process Specifications, but indeed much of the resistance comes from handle wafer (undoped) resistance, not the contact itself.</s> |
<s>[INST] Can you tell me, How should I connect the 'wh' handle or handle wafer pin ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The 'wh' handle wafer pin represents the connection of the back handle of the wafer situated just below the BOX and allows the connection of a substrate model to the device.
A local artificial substrate under the below devices is recognized as their 'wh' terminal with description as follow:
1). RF MOS : diffusion area enclosing source/drain regions
2). Front-End Resistors : body of the devices
3). Capacitors : bounding box of the device
4). Varactors : diffusion area
The 'wh' handle wafer terminal connection for RF MOS, Front-End Resistors (Poly1 and Diffusion type), capacitors and varactors as follow:
1). Leave it floating
2). Connect it to a noConn device (to avoid warnings after 'Check and Save")
3). Connect it to lsubmod device
The 'wh' pin for all other devices (DC MOS, inductors and metal resistors) are merged together during LVS/PEX to a single substrate node which equals the wafer back side connection
the 'wh' terminal of these devices must be tied together in the schematic a label with the name of this common node must be placed anywhere in the layout cell view. The label must be drawn using the LPP Wafer_txt:drawing.
Merging 'wh' pins in the layout view for example it is required when using of multiplier 'm' device parameter for the devices with internal vertical substrate model or when using ser/par of resistors such as series resistors The Marksub:Commonsub (33:33) has to be drawn around the concerned devices in order to represent their common wafer handle terminal. Concerning the third pin of the MIMCAP, the 'wh' pin (pin below the BOX) could be ignored. This is for simulating the lateral substrate model. There is no issue in ignoring it concerning LVS.</s> |
<s>[INST] Can you tell me, Why do I get nwell, pwell width errors, violations flag, triggered for my pe5 devices? With relevant rules that include W1W1, W1W2, W1W3, W1W4, E1MVDF. [/INST] Certainly, I'd be happy to help you with it. To answer your question. Such errors should be corrected. NWELL drawn outside MV will be NWELL1, NWELL inside MV will be NWELL2. With NWELL crossing MV, the sliver outside MV is NWELL1. All NWELL associated with the pe5 must be enclosed by MV. For the pe5 devices, the MV layer extends 0.6um beyond the NWELL. This seemingly large MV enclosure of NWELL is due to the fact that the space between MV and the nwell will be PWELL2, for which rule W1W4 dictates a 0.6um minimum width.</s> |
<s>[INST] Can you tell me and explain to me the HW handle wafer terminal on some devices ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Several transistors such as nhvta, nhvtb, nhvu, ndhvt, ndhvta, phvta, phvtb and phvu need a handle wafer connection for simulation. The fifth terminal 'HW' of these transistors is used for this. It is necessary to connect this terminal in schematic and layout. LVS checks this connection. The connection of the handle wafer can be realized by a top side or a back side connection. In case of top side connection the HWC module is to be used. If the back side application is used or in case of the transistors nhvta, nhvtb, nhvu, ndhvt, ndhvta, phvta, phvtb and phvu, an auxiliary handle wafer contact is necessary in the layout view. The Certainly, I'd be happy to help you with it. To answer your question. auxiliary handle wafer contact is only used for LVS and simulation, no mask will be created. The xt018-ApplicationNote-Layout_Techniques document explains how to create an auxiliary handle wafer contact in layout.</s> |
<s>[INST] Can you tell me, With what potential should the handle wafer or HW should be biased ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. Please see section 2.5 in the xt018 layout techniques application note. The xt018 Process & Device Specification provides operating limits for each device with respect to the HW.</s> |
<s>[INST] Can you tell me, Why XT018 or xt018 HV_CELLS library is not automatically loaded ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The module requirements can differ depending on the selected cell -- this applies mainly to the 1.8V cells as they are not compatible with the MOS5 core module. In the Cadence PDK environment, whether an X-FAB library is available for a particular PDK startup option is controlled by the pdk_code.txt file within the library. The file currently in the library only specifies options with the LP5MOS main module. However, the library can also be used with the MOS5 main module (except the 1.8V cells, as already noted). The pdk_code.txt file can be amended as below to include MOS5, which specifies the compatible options. Change the file in your installed library at (the exact path depends on the library version) $X_DIR/xt018/esdlibs/HV_CELLS/v1_2/cadence_IC61/v1_2_0/HV_CELLS/ with the content below. It's important that when selecting any cell, you ensure that its module requirements are consistent with those of your design. See guideline as follow:
# Do not edit this file!
# File keeps xkit start up information
# HV_CELLS v1_2_0
# MOS5 options added
PDK_CODE xt018_1231_LP5MOS_MET3_METMID
PDK_CODE xt018_1232_LP5MOS_MET3_METTHK
PDK_CODE xt018_1233_LP5MOS_MET3_METMID_METTHK
PDK_CODE xt018_1241_LP5MOS_MET3_MET4_METMID
PDK_CODE xt018_1242_LP5MOS_MET3_MET4_METTHK
PDK_CODE xt018_1243_LP5MOS_MET3_MET4_METMID_METTHK
PDK_CODE xt018_1251_LP5MOS_MET3_MET4_MET5_METMID
PDK_CODE xt018_1252_LP5MOS_MET3_MET4_MET5_METTHK
PDK_CODE xt018_5031_MOS5_MET3_METMID
PDK_CODE xt018_5032_MOS5_MET3_METTHK
PDK_CODE xt018_5033_MOS5_MET3_METMID_METTHK
PDK_CODE xt018_5041_MOS5_MET3_MET4_METMID
PDK_CODE xt018_5042_MOS5_MET3_MET4_METTHK
PDK_CODE xt018_5043_MOS5_MET3_MET4_METMID_METTHK
PDK_CODE xt018_5051_MOS5_MET3_MET4_MET5_METMID
PDK_CODE xt018_5052_MOS5_MET3_MET4_MET5_METTHK</s> |
<s>[INST] Can you tell me, How pe5ti device is different from the pe5 device in XT018 or xt018 ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The xt018 pe5ti is a trench-isolated pe5 without a PTUB below it. The peti and pe5ti devices were generated in response to a request for a pe or pe5 device that did not need a p-well contact as this would take up more room. We came up with the peti and pe5ti devices specifically for this reason. These devices are standard pe or pe5 transistors but with HVNWELL used below the N-well which converts the entire tub to N-type.</s> |
<s>[INST] Can you tell me, Why rm1 metal resistor breakdown is much lower than that of higher level metal resistors ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. This is related to the ILD/IMD voltage rating, for MET2 there is much thicker oxide than for MET1. There is design rule S1M1DF, but this would require a DTI between the MET1 and DIFF geometry in question. If there are no active devices below rm1, the device could be placed over floating ISOTUB(s).</s> |
<s>[INST] Can you tell me, after upgrading to version 12 PDK, why do rpp1 instances of existing design show different parameter values that flag and trigger B7P1 design rule violations ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. This is due to the underlying well options. The background here is that we found a bimodal distribution of rpp1 sheet resistance with NWELL below, depending on whether LP5MOS or MOS5 core module was used. To address this, we now offer two rpp1_3 resistor types: the rpp1_3 and a rpp1nw_3. The rpp1_3 has a new higher sheet resistance than before while the rpp1nw_3 has the same sheet resistance as the version 11 rpp1_3. This explains why, using rpp1_3, you get a different length for the same resistance in v12 PDK. You could use the new device rpp1nw_3 instead of rpp1_3 to get a better match to the old v11 and avoid the B7P1 error. Alternatively, you could leave your layout as-is and waive the B7P1 error as it is not fatal, but then if the design is re-used in a different core module later, you may see a different performance.</s> |
<s>[INST] Can you tell me, What is the relation, coorelation of FIMP mask to drawn layers ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. The xt06 FIMP mask defines where the field implant is not implanted. It is not intuitive that the NOFIMP layer is the direct design entry for the FIMP mask. Having in mind the FIMP mask is meant for blocking the global FIMP implant in the process makes it easier to understand.</s> |
<s>[INST] Can you tell me, for wafers held at Poly, at what step are the wafers actually held or stop ? [/INST] Certainly, I'd be happy to help you with it. To answer your question. For a request to hold at Poly, we will hold it at Active (ACT/DIFF) layer instead. For the 0.18um technologies, ACT and POLY1 dummies are required and both dummies are interlinked. Therefore, any POLY1 redesign may affect the ACT layer and may result in a new ACT mask. If the wafers that have been on hold at Poly had already processed with the old ACT mask, clearly the new ACT mask cannot be used for these wafers. So to avoid this from happening, we suggest to hold the wafers at the Active layer. However, if you can confirm that your future redesign will not change the ACT mask, we can support your request to hold the wafers at Poly.</s> |
<s>[INST] Can you tell me, What helps are available for resolving, clearing, fix MIM capacitor antenna errors ? [/INST] The MIM-capacitor antenna rules are defined in the 0.18um-ProcessSpecification-DR_MIM_Antenna_Rules document. Advice for preventing and resolving such errors can be found in the 0.18um-ApplicationNote-MIM_Capacitors_Check document.
You can visit this link on how to resolve this violations:
1). https://my.xfab.com/search/_action/relation/0d92400d-b4de-48f3-9bb8-38e7aaf134b9/
2). Supplemental 'MIMANT' DRC runsets for checking these antenna rules are available for PVS, Calibre, and IC Validator.
3). https://my.xfab.com/search/_action/relation/491ae11f-379c-4a5e-b2b0-8445c79c830d/
4). https://my.xfab.com/search/_action/relation/557ba3a2-ee77-4034-8518-5917dac84d4d/
5). https://my.xfab.com/search/_action/relation/de9558d0-b114-4f5f-bf3f-d8c7ab2562d3/</s> |