module_name
stringlengths 1
2.17k
| module_content
stringlengths 6
11.3k
|
|---|---|
seq_item_ams |
protected:
cv::Mat tx_img;
public:
// Input clock
sc_core::sc_in<bool> clk;
// Counters
sc_core::sc_in<unsigned int> hcount;
sc_core::sc_in<unsigned int> vcount;
// Output pixel
sc_core::sc_out<sc_uint<N> > o_red;
sc_core::sc_out<sc_uint<N> > o_green;
sc_core::sc_out<sc_uint<N> > o_blue;
SC_CTOR(seq_item_ams)
{
// Read image
const std::string img_path = IPS_IMG_PATH_TB;
cv::Mat read_img = cv::imread(img_path, cv::IMREAD_COLOR);
// CV_8UC3 Type: 8-bit unsigned, 3 channels (e.g., for a color image)
read_img.convertTo(this->tx_img, CV_8UC3);
#ifdef IPS_DEBUG_EN
std::cout << "Loading image: " << img_path << std::endl;
#endif // IPS_DEBUG_EN
// Check if the image is loaded successfully
if (this->tx_img.empty())
{
std::cerr << "Error: Could not open or find the image!" << std::endl;
exit(EXIT_FAILURE);
}
#ifdef IPS_DEBUG_EN
std::cout << "TX image info: ";
std::cout << "rows = " << this->tx_img.rows;
std::cout << " cols = " << this->tx_img.cols;
std::cout << " channels = " << this->tx_img.channels() << std::endl;
#endif // IPS_DEBUG_EN
SC_METHOD(run);
sensitive << clk.pos();
}
void run()
{
if (this->clk.read())
{
const int IMG_ROW = static_cast<int>(this->vcount.read()) - (V_SYNC_PULSE + V_BP);
const int IMG_COL = static_cast<int>(this->hcount.read()) - (H_SYNC_PULSE + H_BP);
#ifdef IPS_DEBUG_EN
std::cout << "TX image: ";
std::cout << "row = " << IMG_ROW;
std::cout << " col = " << IMG_COL;
#endif // IPS_DEBUG_EN
if ((IMG_ROW < 0) || (IMG_COL < 0) || (IMG_ROW >= static_cast<int>(V_ACTIVE)) || (IMG_COL >= static_cast<int>(H_ACTIVE)))
{
this->o_red.write(0);
this->o_green.write(0);
this->o_blue.write(0);
#ifdef IPS_DEBUG_EN
std::cout << " dpixel = (0,0,0) " << std::endl;
#endif // IPS_DEBUG_EN
}
else
{
cv::Vec3b pixel = tx_img.at<cv::Vec3b>(IMG_ROW, IMG_COL, 0);
this->o_red.write(static_cast<sc_uint<8>>(pixel[0]));
this->o_green.write(static_cast<sc_uint<8>>(pixel[1]));
this->o_blue.write(static_cast<sc_uint<8>>(pixel[2]));
#ifdef IPS_DEBUG_EN
std::cout << " ipixel = (" << static_cast<int>(pixel[0]) << ","
<< static_cast<int>(pixel[1]) << "," << static_cast<int>(pixel[2])
<< ")" << std::endl;
#endif // IPS_DEBUG_EN
}
}
}
|
waveform |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_out<DATA1024_t > source;
SC_CTOR(waveform)
{
SC_CTHREAD(waveform_thread,clk.pos());
}
void waveform_thread()
{
DATA1024_t tmp;
tmp.data = 0;
tmp.tlast = 0;
reset.write(true);
float numberGen = 0;
while(true)
{
wait();
reset.write(false);
for(int i=0;i<10;i++)
{
wait();
if(i==10-1)
{
tmp.tlast = 1;
cout << "sending TLAST signal" << endl;
}
else
{
tmp.tlast = 0;
}
if(i==0)
monitor_logger::ingressEvent();
source.write(tmp);
//while(source.num_free() != 0) {wait();}
for(int i=0;i<64;i++)
{
sc_fixed<16,8> fx = sin(numberGen)*120.1f;
//sc_signed us_tmp(fx.wl());
//us_tmp = (fx << (fx.wl()-fx.iwl()));
//tmp.data((16-1) + (16*i),16*i) = (sc_bv<16>)us_tmp;
tmp.data((16-1) + (16*i),16*i) = fixed2bv<16,8>(fx);
sc_bv<16> tmpCheckRaw = (sc_bv<16>)tmp.data((16-1) + (16*i),16*i);
sc_fixed<16,8> tmpCheck = bv2fixed<16,8>(tmpCheckRaw);
if(fx != tmpCheck)
{
sc_stop();
std::cout << "(casting error) got: " << fx << " != " << tmpCheck << std::endl ;//<< " (RAW: " << us_tmp << ")" << std::endl;
}
else
{
//std::cout << "(casting OK) got: " << fx << " != " << tmpCheck << std::endl;
}
numberGen += 0.1;
}
}
}
}
|
monitor |
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<DATA32_t > sink;
std::ofstream ofs;
SC_CTOR(monitor)
:ofs("test.txt", std::ofstream::out)
{
SC_CTHREAD(monitor_thread,clk.pos());
reset_signal_is(reset,true);
}
~monitor()
{
ofs.close();
}
void monitor_thread()
{
DATA32_t tmp;
unsigned countdown = 30;
while(true)
{
sink.read(tmp);
monitor_logger::egressEvent();
//std::string tmp_string = "PKGnr is: " + std::to_string((unsigned)count.read().to_uint()) + "TDATA: " + std::to_string((unsigned long)tmp.data.to_uint());// + " @ " + sc_time_stamp();
//ofs << "@" << sc_time_stamp() << "last: " << tmp.tlast;
//SC_REPORT_WARNING(::SC_ID_ASSERTION_FAILED_, tmp_string.c_str());
//sc_report(true);
sc_signed ss_tmp(32);
ss_tmp = tmp.data;
sc_fixed<32,16> tmpCheck = ((sc_fixed<32*2,16*2>)ss_tmp)>>16;
cout << "TDATA: " << tmpCheck << " @ " << sc_time_stamp() << endl;
if(tmp.tlast==1)
{
//clog << "test2" << sc_time_stamp() << endl;
//cerr << "test" << sc_time_stamp() << endl;
cout << "got TLAST signal @ " << sc_time_stamp() << endl;
}
countdown--;
if(countdown==0)
{
cout << "sc_stop signal" << endl;
sc_stop();
monitor_logger::measure_log();
}
}
}
|
Seuil_calc1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out <bool> detect;
// sc_fifo_out <bool> detect1;
SC_CTOR(Seuil_calc1)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
sc_uint<8> buffer[32];
sc_uint<22> seuil= 26;
#pragma HLS ARRAY_PARTITION variable=buffer complete dim=0
while( true )
{
#pragma HLS PIPELINE
for (uint8_t j = 0; j < 32-1; j += 1)
{
// #pragma HLS PIPELINE
buffer[j] = buffer[j+1];
}
buffer[32-1] = e.read();
const sc_uint<11> ps = (sc_uint<11>) buffer[ 0] + (sc_uint<11>) buffer[ 1] + (sc_uint<11>) buffer[ 4] + (sc_uint<11>) buffer[ 5] + // 2 bits à 1 en PPM
(sc_uint<11>) buffer[14] + (sc_uint<11>) buffer[15] + (sc_uint<11>) buffer[18] + (sc_uint<11>) buffer[19]; // 2 bits à 0 en PPM
sc_uint<22> sum = 0;
for (uint8_t i = 0; i < 32; i += 1)
{
// #pragma HLS PIPELINE
const sc_uint<8> temp = buffer[i];
const sc_uint<16> sqrv = (temp * temp);
sum += sqrv;
}
sum = 8 * sum;
const sc_uint<22> res_0 = (ps* ps);
const sc_uint<22> res_1 = sum >> 5;
const sc_uint<22> res_2 = (res_1 == 0)? (sc_uint<22>)31 :res_1;
const sc_uint<22> res_3 = res_0 /res_2;
const bool condition = (res_3> seuil);
detect.write(condition);
// sc_uint<22> res_0 = (ps* ps);
// sc_uint<22> res_1 = (res_0 << 5);
// sc_uint<22> res_2 = res_1 / sum;
// sc_uint<5> res_3 = res_2 & 0x1F;
// detect.write(res_3> seuil);
}
}
|
tb_cnn_2d |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
typedef sc_fixed<P_data_W, P_data_P> sc_data;
sc_data func(int a, int b, int c, int d) {
int tmp = ((d & 0xFF) << 24) | ((c & 0xFF) << 16) | ((b & 0xFF) << 8) | ((a & 0xFF) << 0);
return (sc_data)tmp;
}
void func_inv(sc_data in, int &a, int &b, int &c, int &d) {
a = (in.to_int() >> 0) & 0xFF;
b = (in.to_int() >> 8) & 0xFF;
c = (in.to_int() >> 16) & 0xFF;
d = (in.to_int() >> 24) & 0xFF;
}
struct dma_pkg : public hwcore::pipes::sc_fifo_base_dummy<dma_pkg> {
typedef sc_bv<P_input_width> sc_data_raw;
sc_data_raw *data_array;
uint64 size;
|
Counter |
//------------------------------Module Inputs------------------------------
// Input clock
sc_in_clk clk;
// Reset bar (reset when 1'b0)
sc_in<bool> rstb;
// Starts the counter
sc_in<bool> enable;
// N-bit output of the counter
sc_out<sc_uint<N > > count_out;
//-----------------------------Local Variables-----------------------------
sc_uint<4> count_int;
public:
/**
* @brief Default constructor for Counter.
*/
SC_CTOR(Counter)
{
SC_METHOD(count);
// Sensitive to the clk posedge to carry out the count
sensitive << clk.pos();
// Sensitive to any state change to go in or out of reset
sensitive << rstb;
}
//---------------------------------Methods---------------------------------
/**
* @brief Methods that counts in every posedge of the clock, unless rstb is
* equal to 0, then the output will be always 0. Enable needs to be
* asserted, otherwise it will show latest value of the counter.
*/
void count();
|
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<24> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
const sc_int<16> sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
mon_split_and_merge |
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_split_and_merge)
{
SC_THREAD(mon_thread);
}
void mon_thread()
{
for(int a=0;a<2;a++)
{
uint16_t data_gen = 0;
hwcore::pipes::sc_data_stream_t<16> tmp_in;
do
{
tmp_in = data_in.read();
std::cout << "(mon) got signal." << std::endl;
//for(int i=0;i<split_N;i++)
//{
if(tmp_in.template getKeep<16>(0)==1)
{
int tmp = tmp_in.template getData<sc_uint, 16>(0).to_uint();
std::cout << "(mon) got new data: " <<tmp << std::endl;
sc_assert(tmp == data_gen);
data_gen++;
}
//}
}while(data_gen < test_size);
}
std::cout << "Test finish no errors" << std::endl;
sc_stop();
}
|
wave_split_and_merge |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_split_and_merge)
{
SC_THREAD(wave_thread);
}
void wave_thread()
{
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++)
{
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.setKeep();
tmp.tlast = 1;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
for (int i = 0; i < test_size; i++)
{
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.setKeep();
tmp.tlast = 1;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
}
|
tb_split_and_merge |
#if __RTL_SIMULATION__
//DMA_performance_tester_rtl_wrapper u1;
#else
//DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_split_and_merge wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
hwcore::pipes::sc_stream_splitter<16,split_N,false> u1_ss;
hwcore::hf::sc_static_list<sc_fifo<hwcore::pipes::sc_data_stream_t<16> >, split_N> u1_2_u2;
//sc_fifo<hwcore::pipes::DATA_STREAM_t<16> > u1_2_u2[32];
hwcore::pipes::sc_stream_merge_raw<16,split_N> u2_sm;
sc_fifo<hwcore::pipes::sc_data_stream_t<16*split_N> > u2_2_u3;
hwcore::pipes::sc_stream_resize<16*split_N, 16> u3_sr;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > u3_2_mon;
mon_split_and_merge mon;
SC_CTOR(tb_split_and_merge)
: u1_ss("u1_ss"),u2_sm("u2_sm"), u3_sr("u3_sr"), wave("wave"), mon("mon"),
clk("clock", sc_time(10, SC_NS)),wave_2_u1(64),u2_2_u3(64), u3_2_mon(64),u1_2_u2("fifo",1)
{
wave.data_out(wave_2_u1);
u1_ss.din(wave_2_u1);
u1_ss.clk(clk);
u1_ss.reset(reset);
for(int i=0;i<split_N;i++)
{
u1_ss.dout[i](u1_2_u2.get(i));
u2_sm.din[i](u1_2_u2.get(i));
}
u2_sm.clk(clk);
u2_sm.reset(reset);
u2_sm.dout(u2_2_u3);
u3_sr.din(u2_2_u3);
u3_sr.clk(clk);
u3_sr.reset(reset);
u3_sr.dout(u3_2_mon);
mon.data_in(u3_2_mon);
}
|
MIPS |
sc_in<bool> clk;
sc_port<readwrite_if> ioController;
uint32_t breg[32];
Bitmap bg;
SC_CTOR(MIPS) {
SC_METHOD(exec);
sensitive << clk.pos();
const char fn[] = "mandrill2.bmp";
const char mode[] = "rb";
breg[4] = (uint32_t)fn; breg[5] = (uint32_t)mode;
fileOpen();
breg[4] = breg[2];
breg[5] = (uint32_t)&bg.magic_number; breg[6] = 54;
fileRead();
bg.buf = malloc(bg.width*bg.height*bg.bpp/8);
breg[5] = (uint32_t)bg.buf; breg[6] = bg.width*bg.height*bg.bpp/8;
fileRead();
fileClose();
}
~MIPS() {
free(bg.buf);
}
void exec() {
uint32_t ioWord;
static bool inited = false;
if (!inited) {
inited = true;
ioController->read(0xFF400104, 4, &ioWord);
int w = ioWord >> 16, h = ioWord & 0xFFFF;
for (int y = 0; y < h && y < int(bg.height); y++) {
for (int x = 0; x < w && x < int(bg.width); x++) {
uint32_t rgbpixel;
if (bg.bpp == 8) {
uint8_t rawpixel = ((uint8_t*)bg.buf)[(bg.height - 1 - y)*bg.width + x];
rgbpixel = rawpixel | (rawpixel << 8) | (rawpixel << 16);
}
else
rgbpixel = ((uint32_t*)bg.buf)[(bg.height - 1 - y)*bg.width + x];
ioController->write(0xFF000000 + ((y*w + x) << 2), 4, &rgbpixel);
}
}
}
ioController->read(0xFF400000 + 'w', 4, &ioWord);
if (ioWord == 1) {
printf("Insert a string: ");
fflush(stdout);
std::string tmp;
ioController->read(0xFF400114, 4, &ioWord);
while (ioWord != '\r') {
tmp += char(ioWord);
printf("%c", char(ioWord));
fflush(stdout);
ioController->read(0xFF400114, 4, &ioWord);
}
printf("\nString inserted: %s\n", tmp.c_str());
fflush(stdout);
}
ioController->read(0xFF400102, 4, &ioWord);
if (ioWord)
exit();
breg[4] = 33;
sleep();
}
// ===========================================================================
// syscalls (code in v0)
// ===========================================================================
// v0: 2
// a0: 4
// a1: 5
// a2: 6
void exit() { // v0 = 10
sc_stop();
}
void fileOpen() { // v0 = 13
breg[2] = (uint32_t)fopen((const char*)breg[4], (const char*)breg[5]);
}
void fileRead() { // v0 = 14
breg[2] = (uint32_t)fread((void*)breg[5], breg[6], 1, (FILE*)breg[4]);
}
void fileWrite() { // v0 = 15
breg[2] = (uint32_t)fwrite((const void*)breg[5], breg[6], 1, (FILE*)breg[4]);
}
void fileClose() { // v0 = 16
fclose((FILE*)breg[4]);
}
void sleep() { // v0 = 32
Thread::sleep(breg[4]);
}
|
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Seuil_calc2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out <bool> detect;
// sc_fifo_out <bool> detect1;
SC_CTOR(Seuil_calc2)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
sc_uint<8> buffer[32];
sc_uint<22> seuil= 26;
sc_uint<22> sum = 0;
sc_uint<8> x0 = buffer[0];
sc_uint<8> x31 = 0;
sc_uint<16> x02 = 0;
sc_uint<16> x312 = 0;
sc_uint<22> tmp = 0;
#pragma HLS ARRAY_PARTITION variable=buffer complete dim=0
while( true )
{
#pragma HLS PIPELINE
for (uint8_t j = 0; j < 32-1; j += 1)
{
// #pragma HLS PIPELINE
buffer[j] = buffer[j+1];
}
buffer[32-1] = e.read();
x31 = buffer[32-1];
const sc_uint<11> ps = (sc_uint<11>) buffer[ 0] + (sc_uint<11>) buffer[ 1] + (sc_uint<11>) buffer[ 4] + (sc_uint<11>) buffer[ 5] + // 2 bits à 1 en PPM
(sc_uint<11>) buffer[14] + (sc_uint<11>) buffer[15] + (sc_uint<11>) buffer[18] + (sc_uint<11>) buffer[19]; // 2 bits à 0 en PPM
x02 = x0 * x0 ;
x312 = x31 * x31;
tmp = (x312 -x02);
sum += 8*tmp;
x0 = buffer[0];
const sc_uint<22> res_0 = (ps* ps);
const sc_uint<22> res_1 = sum >> 5;
const sc_uint<22> res_2 = (res_1 == 0)? (sc_uint<22>)31 :res_1;
const sc_uint<22> res_3 = res_0 /res_2;
const bool condition = (res_3> seuil);
detect.write(condition);
}
}
|
mon_bufferstreamer |
sc_fifo_out<sc_uint<31> > ctrl_out;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_bufferstreamer) { SC_THREAD(mon_thread); }
void mon_thread() {
uint16_t data_gen = 0;
std::cout << "(mon) req. newset (start) " << std::endl;
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
std::cout << "(mon) req. newset (done) " << std::endl;
hwcore::pipes::sc_data_stream_t<16> raw_tmp;
for (int a = 0; a < 5; a++) {
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
for (int i = 0; i < test_size; i++) {
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false")
<< std::endl;
sc_assert((i == test_size - 1) == (raw_tmp.tlast == 1));
sc_assert(tmp == i);
if (tmp != i) {
sc_stop();
}
}
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false") << std::endl;
sc_assert(raw_tmp.EOP());
}
std::cout << "(mon) req. newset (start) " << std::endl;
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
std::cout << "(mon) req. newset (done) " << std::endl;
for (int a = 0; a < 5; a++) {
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
for (int i = 0; i < test_size; i++) {
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false")
<< std::endl;
sc_assert((i == test_size - 1) == (raw_tmp.tlast == 1));
sc_assert(tmp == i + 0xBF);
if (tmp != i + 0xBF) {
sc_stop();
}
}
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false") << std::endl;
sc_assert(raw_tmp.EOP());
}
std::cout << "Test finish no errors" << std::endl;
sc_stop();
}
|
wave_bufferstreamer |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_bufferstreamer) { SC_THREAD(wave_thread); }
void wave_thread() {
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++) {
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.tkeep = 0b11;
tmp.tlast = (i == test_size - 1);
std::cout << "(wave) tlast " << (tmp.tlast ? "true" : "false") << std::endl;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
for (int i = 0; i < test_size; i++) {
tmp.data = i + 0xBF;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.tkeep = 0b11;
tmp.tlast = (i == test_size - 1);
std::cout << "(wave) tlast " << (tmp.tlast ? "true" : "false") << std::endl;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
}
|
tb_bufferstreamer |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
hwcore::pipes::sc_stream_buffer_not_stream_while_write<16> bs_u1;
wave_bufferstreamer wave;
mon_bufferstreamer mon;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > bs2mon_data;
sc_fifo<sc_uint<31> > mon2bs_ctrl;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave2bs_data;
SC_CTOR(tb_bufferstreamer) : bs_u1("BS"), wave("wave"), mon("mon"), clk("clock", sc_time(10, SC_NS)) {
bs_u1.clk(clk);
bs_u1.reset(reset);
bs_u1.din(wave2bs_data);
bs_u1.dout(bs2mon_data);
bs_u1.ctrls_in(mon2bs_ctrl);
wave.data_out(wave2bs_data);
mon.ctrl_out(mon2bs_ctrl);
mon.data_in(bs2mon_data);
}
|
Detecteur2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
// sc_fifo_in < sc_uint<8> > e2;
sc_fifo_out< sc_uint<8> > s;
// sc_fifo_out< bool > detect1;
SC_CTOR(Detecteur2):
s_calc("s_calc"),
t_sep("t_sep"),
dbl("dbl"),
dbl2scalc("dbl2scalc",1024),
dbl2tsep("dbl2tsep",1024),
detect("detect", 1024)
// detect1("detect1", 4096)
{
dbl.clock(clock);
dbl.reset(reset);
dbl.e(e);
dbl.s1(dbl2scalc);
dbl.s2(dbl2tsep);
s_calc.clock(clock);
s_calc.reset(reset);
s_calc.e(dbl2scalc);
s_calc.detect(detect);
// s_calc.detect1(detect1);
t_sep.clock(clock);
t_sep.reset(reset);
t_sep.e(dbl2tsep);
t_sep.detect(detect);
t_sep.s(s);
}
private:
Seuil_calc2 s_calc;
trames_separ2 t_sep;
DOUBLEUR_U dbl;
sc_fifo< sc_uint<8> > dbl2scalc;
sc_fifo< sc_uint<8> > dbl2tsep;
sc_fifo <bool> detect;
|
memory |
protected:
int *mem;
public:
sc_core::sc_in<bool> clk;
sc_core::sc_in<bool> we;
sc_core::sc_in<unsigned long long int> address;
sc_core::sc_in<sc_uint<24>> wdata;
sc_core::sc_out<sc_uint<24>> rdata;
// Constructor for memory
SC_CTOR(memory)
{
this->mem = new int[SIZE];
SC_METHOD(run);
sensitive << clk.pos();
}
void run()
{
if (clk.read())
{
const unsigned long long int ADDR = static_cast<unsigned long long int>(this->address.read());
if (we.read())
{
this->mem[ADDR] = this->wdata.read();
}
this->rdata.write(this->mem[ADDR]);
}
}
|
hl5 |
public:
// Declaration of clock and reset signals
sc_in_clk clk;
sc_in < bool > rst;
//End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
// TODO: removeme
// sc_out < bool > main_start;
// sc_out < bool > main_end;
// Instruction counters
sc_out < long int > icount;
sc_out < long int > j_icount;
sc_out < long int > b_icount;
sc_out < long int > m_icount;
sc_out < long int > o_icount;
// Inter-stage Flex Channels.
put_get_channel< de_out_t > de2exe_ch;
put_get_channel< mem_out_t > wb2de_ch; // Writeback loop
put_get_channel< exe_out_t > exe2mem_ch;
// Forwarding
sc_signal< reg_forward_t > fwd_exe_ch;
SC_HAS_PROCESS(hl5);
hl5(sc_module_name name,
sc_uint<XLEN> imem[ICACHE_SIZE],
sc_uint<XLEN> dmem[DCACHE_SIZE])
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
// , main_start("main_start")
// , main_end("main_end")
, entry_point("entry_point")
, de2exe_ch("de2exe_ch")
, exe2mem_ch("exe2mem_ch")
, wb2de_ch("wb2de_ch")
, fwd_exe_ch("fwd_exe_ch")
, fede("Fedec", imem)
, exe("Execute")
, mewb("Memory", dmem)
{
// FEDEC
fede.clk(clk);
fede.rst(rst);
fede.dout(de2exe_ch);
fede.feed_from_wb(wb2de_ch);
fede.program_end(program_end);
fede.fetch_en(fetch_en);
fede.entry_point(entry_point);
// fede.main_start(main_start);
// fede.main_end(main_end);
fede.fwd_exe(fwd_exe_ch);
fede.icount(icount);
fede.j_icount(j_icount);
fede.b_icount(b_icount);
fede.m_icount(m_icount);
fede.o_icount(o_icount);
// EXE
exe.clk(clk);
exe.rst(rst);
exe.din(de2exe_ch);
exe.dout(exe2mem_ch);
exe.fwd_exe(fwd_exe_ch);
// MEM
mewb.clk(clk);
mewb.rst(rst);
mewb.din(exe2mem_ch);
mewb.dout(wb2de_ch);
mewb.fetch_en(fetch_en);
}
// Instantiate the modules
fedec_wrapper fede;
execute_wrapper exe;
memwb_wrapper mewb;
|
BMPWriter |
public:
sc_fifo_in< sc_uint<32> > addr;
sc_fifo_in< sc_uint<24> > rgbv;
SC_CTOR(BMPWriter)
{
SC_THREAD(do_gen);
}
~BMPWriter( )
{
string fn;
fn = "received_image";
string filename = fn + ".bmp";
if (fopen(filename.c_str(), "rb")== NULL )
bmp->write( filename.c_str() );
else
{
uint32_t k = 1;
filename = fn+std::to_string(k)+".bmp";
while (fopen(filename.c_str(), "rb")!= NULL )
{
filename = fn+std::to_string(k)+".bmp";
k++;
}
// const char* filename = ("received_image"+std::to_string(k)+".bmp").c_str();
bmp->write(filename.c_str());
}
delete bmp;
}
private:
BMP* bmp;
void do_gen( )
{
bmp = new BMP(640, 480);
uint8_t* ptr = bmp->data.data();
//
// On initilise l'image de sortie dans la couleur rouge pour mieux voir
// les defauts
//
for (uint32_t i = 0; i < (3 * 640 * 480); i += 3)
{
ptr[i + 0] = 0xFF;
ptr[i + 0] = 0x00;
ptr[i + 0] = 0x00;
}
while( true )
{
uint32_t adr = addr.read();
sc_uint<24> rgb = rgbv.read();
uint32_t r = rgb.range(23, 16);
uint32_t g = rgb.range(15, 8);
uint32_t b = rgb.range( 7, 0);
if( (3 * adr) >= (3 * 640 *480) )
{
std::cout << "(WW) Address value is out of image bounds !" << std::endl;
continue;
}
ptr[3 * adr + 0 ] = r;
ptr[3 * adr + 1 ] = g;
ptr[3 * adr + 2 ] = b;
}
}
|
Filter |
//-----------------------------Local Variables-----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
/**
* @brief Default constructor for Filter
*/
SC_CTOR(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
SC_METHOD(init_kernel);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT& result);
void init_kernel();
|
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
trames_separ |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_in <bool> detect;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(trames_separ)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
// uint64_t counter = 0;
// #endif
// float buffer[32];
// #pragma HLS ARRAY_PARTITION variable=buffer complete dim=0
while( true )
{
const uint8_t data = e.read();
const bool valid = detect.read();
if( valid)
{
const int factor = 2 * 2; // PPM modulation + UpSampling(2)
for(uint16_t i = 0; i < factor * _BITS_HEADER_; i += 1)
{
s.write( e.read() );
detect.read();
}
for(uint16_t i = 0; i < factor * _BITS_PAYLOAD_; i += 1)
{
s.write( e.read() );
detect.read();
}
for(uint16_t i = 0; i < factor * _BITS_CRC_; i += 1)
{
s.write( e.read() );
detect.read();
}
}
}
}
|
cpu_sim |
sc_fifo_out<pipes::sc_data_stream_t<16*32> > dma_out;
sc_fifo_in<pipes::sc_data_stream_t<16*32> > dma_in;
//sc_out<uint32_t>
|
tb_cnn_top |
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > cpu_sim_2_u1_dma;
cnn::top_cnn<> cnn_u1;
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > u1_2_cpu_sim_dma;
|
RAWReader |
public:
sc_fifo_out< sc_int<8> > s;
SC_CTOR(RAWReader)
{
SC_THREAD(do_gen);
}
private:
void do_gen( )
{
cout << "(II) RAWReader :: START" << endl;
FILE* f = fopen("/tmp/file.raw", "rb");
if( f == NULL )
{
cout << "(EE) Error opening the input file (/tmp/file.raw)" << endl;
exit( EXIT_FAILURE );
}
while( feof(f) == 0 )
{
int8_t buffer[1024];
uint32_t n = fread(buffer, sizeof(int8_t), 1024, f);
// cout << "(DD) RAWReader (" << n << ") values were read in the file." << endl;
for(uint32_t i = 0; i < n; i += 1)
{
s.write( buffer[i] );
wait(10, SC_NS);
}
}
wait(100, SC_US);
cout << "(II) RAWReader :: STOP" << endl;
sc_stop();
}
|
fedec |
public:
// FlexChannel initiators
put_initiator< de_out_t > dout;
get_initiator< mem_out_t > feed_from_wb;
// Forward
sc_in< reg_forward_t > fwd_exe;
// End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
// Clock and reset signals
sc_in_clk clk;
sc_in< bool > rst;
// TODO: removeme
// sc_out < bool > main_start;
// sc_out < bool > main_end;
// Instruction counters
sc_out < long int > icount;
sc_out < long int > j_icount;
sc_out < long int > b_icount;
sc_out < long int > m_icount;
sc_out < long int > o_icount;
// Trap signals. TODO: not used. Left for future implementations.
sc_signal< bool > trap; //sc_out
sc_signal< sc_uint<LOG2_NUM_CAUSES> > trap_cause; //sc_out
// Instruction cache pointer to external memory
sc_uint<XLEN> *imem;
// Thread prototype
void fedec_th(void);
// Function prototypes.
sc_bv<PC_LEN> sign_extend_jump(sc_bv<21> imm);
sc_bv<PC_LEN> sign_extend_branch(sc_bv<13> imm);
SC_HAS_PROCESS(fedec);
fedec(sc_module_name name, sc_uint<XLEN> _imem[ICACHE_SIZE])
: dout("dout")
, feed_from_wb("feed_from_wb")
, fwd_exe("fwd_exe")
, program_end("program_end")
, fetch_en("fetch_en")
, entry_point("entry_point")
// , main_start("main_start")
// , main_end("main_end")
, j_icount("j_icount")
, b_icount("b_icount")
, m_icount("m_icount")
, o_icount("o_icount")
, clk("clk")
, rst("rst")
, trap("trap")
, trap_cause("trap_cause")
, imem(_imem)
{
SC_CTHREAD(fedec_th, clk.pos());
reset_signal_is(rst, false);
dout.clk_rst(clk, rst);
feed_from_wb.clk_rst(clk, rst);
FLAT_REGFILE;
FLAT_SENTINEL;
MAP_ICACHE;
}
sc_uint<PC_LEN> pc; // Init. to -4, then before first insn fetch it will be updated to 0.
sc_bv<INSN_LEN> insn; // Contains full instruction fetched from IMEM. Used in decoding.
fe_in_t self_feed; // Contains branch and jump data.
// Member variables (DECODE)
mem_out_t feedinput;
de_out_t output;
// NB. x0 is included in this regfile so it is not a real hardcoded 0
// constant. The writeback section of fedec has a guard fro writes on
// x0. For double protection, some instructions that want to write into
// x0 will have their regwrite signal forced to false.
sc_bv<XLEN> regfile[REG_NUM];
// Keeps track of in-flight instructions that are going to overwrite a
// register. Implements a primitive stall mechanism for RAW hazards.
sc_uint<TAG_WIDTH> sentinel[REG_NUM];
// TODO: Used for synchronizing with the wb stage and avoid
// 'hiccuping'. It magically works.
sc_uint<2> position;
bool freeze;
sc_uint<TAG_WIDTH> tag;
sc_uint<PC_LEN> return_address;
|
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
Detecteur1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
// sc_fifo_in < sc_uint<8> > e2;
sc_fifo_out< sc_uint<8> > s;
// sc_fifo_out< bool > detect1;
SC_CTOR(Detecteur1):
s_calc("s_calc"),
t_sep("t_sep"),
dbl("dbl"),
dbl2scalc("dbl2scalc",1024),
dbl2tsep("dbl2tsep",1024),
detect("detect", 1024)
// detect1("detect1", 4096)
{
dbl.clock(clock);
dbl.reset(reset);
dbl.e(e);
dbl.s1(dbl2scalc);
dbl.s2(dbl2tsep);
s_calc.clock(clock);
s_calc.reset(reset);
s_calc.e(dbl2scalc);
s_calc.detect(detect);
// s_calc.detect1(detect1);
t_sep.clock(clock);
t_sep.reset(reset);
t_sep.e(dbl2tsep);
t_sep.detect(detect);
t_sep.s(s);
}
private:
Seuil_calc1 s_calc;
trames_separ1 t_sep;
DOUBLEUR_U dbl;
sc_fifo< sc_uint<8> > dbl2scalc;
sc_fifo< sc_uint<8> > dbl2tsep;
sc_fifo <bool> detect;
|
DOUBLEUR |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int<8> > e;
sc_fifo_out< sc_int<8> > s1;
sc_fifo_out< sc_int<8> > s2;
SC_CTOR(DOUBLEUR)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
while ( true )
{
const uint8_t data = e.read();
s1.write( data );
s2.write( data );
}
}
|
first_counter |
// Clock input of the design
sc_in_clk clock;
// Active high, synchronous Reset input
sc_in<bool> reset;
// Active high enable signal for counter
sc_in<bool> enable;
// 4 bit vector output of the counter
sc_out<sc_uint<4> > counter_out;
//------------Local Variables Here---------------------
sc_uint<4> count;
//------------Code Starts Here-------------------------
// Constructor for the counter
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock and also when ever reset changes state
SC_CTOR(first_counter);
// Below function implements actual counter logic
void incr_count();
|
scheduler_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_dma_weight;
sc_fifo_in<float> from_dma_input;
sc_fifo_in< sc_uint<64> > from_dma_instructions;
sc_fifo_out<float> to_dma;
// PROCESSING ENGINES
sc_fifo_out< sc_uint<34> > npu_instructions[CORE];
sc_fifo_out<float> npu_weight[CORE];
sc_fifo_out<float> npu_input[CORE];
sc_fifo_in<float> npu_output[CORE];
// STATES
sc_uint<64> state_instruction_counter;
sc_uint<64> state_instruction_buffer[INSTRUCTION_BUFFER];
float state_input_buffer[INPUT_BUFFER];
float state_output_buffer[INPUT_BUFFER];
// PROCESS
void process(void);
SC_CTOR(scheduler_module)
{
// Init STATES
state_instruction_counter = 0;
SC_CTHREAD(process, clk.pos());
reset_signal_is(reset, true);
}
|
trames_separ2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_in <bool> detect;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(trames_separ2)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
// uint64_t counter = 0;
// #endif
// sc_uint<8> buffer[32];
//#pragma HLS ARRAY_PARTITION variable=buffer complete dim=0
while( true )
{
const uint8_t data = e.read();
const bool valid = detect.read();
if( valid)
{
const int factor = 2 * 2; // PPM modulation + UpSampling(2)
for(uint16_t i = 0; i < factor * _BITS_HEADER_; i += 1)
{
s.write( e.read() );
detect.read();
}
for(uint16_t i = 0; i < factor * _BITS_PAYLOAD_; i += 1)
{
s.write( e.read() );
detect.read();
}
for(uint16_t i = 0; i < factor * _BITS_CRC_; i += 1)
{
s.write( e.read() );
detect.read();
}
}
}
}
|
BMPWriter_fixed_acc |
public:
sc_fifo_in< sc_uint<32> > addr;
sc_fifo_in< sc_uint<24> > rgbv;
SC_CTOR(BMPWriter_fixed_acc)
{
SC_THREAD(do_gen);
}
~BMPWriter_fixed_acc( )
{
string fn;
fn = "received_image_fixed_acc";
string filename = fn + ".bmp";
if (fopen(filename.c_str(), "rb")== NULL )
bmp->write( filename.c_str() );
else
{
uint32_t k = 1;
filename = fn+std::to_string(k)+".bmp";
while (fopen(filename.c_str(), "rb")!= NULL )
{
filename = fn+std::to_string(k)+".bmp";
k++;
}
// const char* filename = ("received_image"+std::to_string(k)+".bmp").c_str();
bmp->write(filename.c_str());
}
delete bmp;
}
private:
BMP* bmp;
void do_gen( )
{
bmp = new BMP(640, 480);
uint8_t* ptr = bmp->data.data();
//
// On initilise l'image de sortie dans la couleur rouge pour mieux voir
// les defauts
//
for (uint32_t i = 0; i < (3 * 640 * 480); i += 3)
{
ptr[i + 0] = 0xFF;
ptr[i + 0] = 0x00;
ptr[i + 0] = 0x00;
}
while( true )
{
uint32_t adr = addr.read();
sc_uint<24> rgb = rgbv.read();
uint32_t r = rgb.range(23, 16);
uint32_t g = rgb.range(15, 8);
uint32_t b = rgb.range( 7, 0);
if( (3 * adr) >= (3 * 640 *480) )
{
std::cout << "(WW) Address value is out of image bounds !" << std::endl;
continue;
}
ptr[3 * adr + 0 ] = r;
ptr[3 * adr + 1 ] = g;
ptr[3 * adr + 2 ] = b;
}
}
|
LED |
sc_in<bool> in;
sc_in<bool> in2;
SC_CTOR(LED)
{
SC_METHOD(blink);
sensitive << in;
}
void blink()
{
if (in.read())
cout << log_time() << "LED "<< name() << ": ON\n";
else
cout << log_time() << "LED "<< name() << ": OFF\n";
}
|
Gate |
sc_in<Person> card;
// Turnstile interface:
sc_in<bool> passed;
sc_out<bool> unlock;
// Two lights for green and red:
sc_out<bool> green;
sc_out<bool> red;
public:
// Better: make it private, include values as constructor args.
Building org;
Building dest;
private:
Person dap= NO_PERSON; // Person currently passing
public:
SC_CTOR(Gate)
{
dap= NO_PERSON;
SC_THREAD(operate);
}
void accept()
{
cout << log_time() << "Person " << dap << " accepted.\n";
green.write(true);
unlock.write(true);
}
void pass_thru()
{
cout << log_time() << "Person " << dap << " has gone to " << dest << "\n";
Users::set_sit(dap, dest);
green.write(false);
unlock.write(false);
dap= NO_PERSON;
}
void off_grn()
{
green.write(false);
unlock.write(false);
dap= NO_PERSON;
}
void refuse()
{
cout << log_time() << "Person " << dap << " refused.\n";
red.write(true);
dap= NO_PERSON;
}
void off_red()
{
red.write(false);
dap= NO_PERSON;
}
void operate()
{
while (true) {
wait(card.value_changed_event());
dap= card.read();
if (Users::admitted(dap, dest))
{
accept();
wait(sc_time(TIMEOUT_GREEN, TIME_UNIT),
passed.posedge_event());
if (passed.read())
pass_thru();
else
off_grn();
}
else
{
refuse();
wait(TIMEOUT_RED, TIME_UNIT);
off_red();
}
}
}
|
turnstile |
sc_in<bool> unlock;
sc_out<bool> passed;
SC_CTOR(turnstile)
{
SC_THREAD(operate);
// sensitive << unlock;
}
void operate()
{
int t;
bool b;
while (true)
{
wait (unlock.posedge_event());
cout << log_time() << "Turnstile " << name() << " unlocked.\n";
/* Wait random amount of time... */
wait(rand() % (TIMEOUT_GREEN/2)+ TIMEOUT_GREEN/2, TIME_UNIT);
b= pick_bool();
cout << log_time() << "Turnstile " << name () << (b ? ": somebody " : ": nobody ") << "passed.\n";
passed.write(b);
}
}
|
Door |
sc_out<Person> card;
private:
sc_signal<bool> green_sig;
sc_signal<bool> red_sig;
sc_signal<bool> unlock_sig;
sc_signal<bool> pass_sig;
sc_signal<Person> card_sig;
LED grn;
LED red;
turnstile ts;
Gate gc;
public:
SC_CTOR(Door) : grn("Green"), red("Red"), ts("TS"), gc("GC")
{
gc.red(red_sig);
red.in(red_sig);
gc.green(green_sig);
grn.in(green_sig);
gc.card(card_sig);
card(card_sig);
gc.unlock(unlock_sig);
ts.unlock(unlock_sig);
gc.passed(pass_sig);
ts.passed(pass_sig);
// SC_METHOD(operate);
// sensitive >> card;
}
void setOrgDest(int org, int dest)
{
gc.org= org;
gc.dest= dest;
}
void operate()
{
approach(card.read());
}
void approach(Person p)
{
cout << log_time() << "Person "<< p << " approaching door " << name() << "\n";
card.write(p);
}
|
testGen |
Door *doors[NUM_DOORS];
int num_steps;
SC_CTOR(testGen)
{
doors[0] = new Door("DoorA");
doors[1] = new Door("DoorB");
doors[2] = new Door("DoorC");
doors[3] = new Door("DoorD");
doors[4] = new Door("DoorE");
doors[5] = new Door("DoorF");
/* Connect doors */
doors[0]->setOrgDest(1, 2);
doors[1]->setOrgDest(2, 1);
doors[2]->setOrgDest(2, 3);
doors[3]->setOrgDest(3, 4);
doors[4]->setOrgDest(4, 3);
doors[5]->setOrgDest(4, 1);
SC_THREAD(driver);
}
void driver()
{
Person p;
Building b;
int c;
for (int i= 0; i< num_steps; i++)
{
cout << log_time() << "#### New simulation step ################\n";
p= rand() % NUM_PERSONS;
c= rand() % NUM_DOORS;
// cout << "Person "<< p<< " approaching door "<< c << "\n";
doors[c]->approach(p);
wait(20, SC_SEC);
cout << log_time() << "Person "<< p<< " now in building "<< Users::get_sit(p) << "\n";
}
}
|
SYSTEM |
//Module Declarations
tb *tb0;
full_adder *full_adder0;
//Local signal declarations
sc_signal<bool> sig_inp_a, sig_inp_b,
sig_inp_cin, sig_sum, sig_co;
SC_HAS_PROCESS(SYSTEM);
SYSTEM( sc_module_name nm) : sc_module (nm) {
//Module instance signal connections
tb0 = new tb("tb0");
tb0->inp_a( sig_inp_a );
tb0->inp_b( sig_inp_b );
tb0->inp_cin( sig_inp_cin );
tb0->sum( sig_sum );
tb0->co( sig_co );
full_adder0 = new full_adder("full_adder0");
full_adder0->inp_a( sig_inp_a );
full_adder0->inp_b( sig_inp_b );
full_adder0->inp_cin( sig_inp_cin );
full_adder0->sum( sig_sum );
full_adder0->co( sig_co );
}
//Destructor
~SYSTEM(){
delete tb0;
delete full_adder0;
}
|
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{
}
|
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{
}
|
M |
sc_in<bool> ckp;
sc_out<int> s1p;
sc_signal<int> s2;
sc_event e1, e2;
void P1_meth(void);
void P3_thrd(void);
void P2_thrd(void);
SC_CTOR(M):count(0),temp(9)
,prev_time(99),prev_ck(true),prev_s1(99),prev_s2(99),prev_temp(99)
{
cout << "T-5:---- Elaborating (CTOR Registering P3_thrd)" << std::endl;
SC_THREAD(P3_thrd);
cout << "T-4:---- Elaborating (CTOR Registering P2_thrd)" << std::endl;
SC_THREAD(P2_thrd);
sensitive << ckp.pos();
cout << "T-3:---- Elaborating (CTOR Registering P1_meth)" << std::endl;
SC_METHOD(P1_meth);
dont_initialize();
sensitive << s2;
SC_METHOD(mon);
sensitive << ckp;
dont_initialize();
}//end SC_CTOR
void mon(void){Eval("ck",1);}// Monitor the clock
unsigned int count;
private:
int temp;
// Special variables and routines to monitor execution follow
Did_update me;
double prev_time;
int prev_temp, prev_s1, prev_s2;
bool prev_ck;
void Eval(const char* message,int type=0){ // Used to trace simulation
if (me.updated) {
Changes();
me.clear();
}//endif
me.watch(&count);
count++;
cout << "T" << std::setfill('_') << std::setw(2) << count;
cout << std::setfill(' ');
if (prev_time == sc_time_stamp()/sc_time(1,SC_NS)) {
cout << ": ";
} else {
cout << ":" << std::setw(2) << int(sc_time_stamp()/sc_time(1,SC_NS)) << "ns";
}//endif
switch (type) {
case 1: cout << " MNTR "; break;
default: cout << " EVAL "; break;
}//endswitch
if (ckp->read() == prev_ck) cout << " ";
else cout << " ck=" << ckp->read();
if (s1p->read() == prev_s1) cout << " ";
else cout << " s1=" << s1p->read();
if (s2.read() == prev_s2) cout << " ";
else cout << " s2=" << s2.read();
if (temp == prev_temp) cout << " ";
else cout << " temp=" << temp;
cout << ": " << message
<< std::endl;
prev_time = sc_time_stamp()/sc_time(1,SC_NS);
prev_ck = ckp->read();
prev_s1 = s1p->read();
prev_s2 = s2.read();
prev_temp = temp;
}//end Eval()
void Changes(void) { // Display variable changes if any
if (ckp->read() != prev_ck || s1p->read() != prev_s1 || s2.read() != prev_s2 || temp != prev_temp) {
cout << " [ ] ";
if (ckp->read() == prev_ck) cout << " ";
else cout << " ck=" << ckp->read();
if (s1p->read() == prev_s1) cout << " ";
else cout << " s1=" << s1p->read();
if (s2.read() == prev_s2) cout << " ";
else cout << " s2=" << s2.read();
if (temp == prev_temp) cout << " ";
else cout << " temp=" << temp;
cout << std::endl;
prev_ck = ckp->read();
prev_s1 = s1p->read();
prev_s2 = s2.read();
prev_temp = temp;
}//endif
}//end Changes()
|
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
IDE |
// Declare inputs and outputs if needed
|
PCIx |
// Declare inputs and outputs if needed
|
ESATA |
public:
sc_in<bool> clk;
sc_out<std::string> path;
void write(const std::string& path) {
// Write logic goes here
}
void read_permissions() {
// Read permissions logic goes here
}
void thread_process() {
wait();
write(/* Your path */);
read_permissions();
}
|
ETH |
public:
sc_in<bool> clk;
sc_in<unsigned char*> ethData;
sc_out<std::string> encryptionKey;
void thread_process() {
wait();
// Replace this line with your actual Ethernet signal transmission logic
sendEthernetSignal(ethData, encryptionKey);
}
|
bootmsgs) : sc_module("bootmsgs" |
QUIETELSECLASS(bootmsgs, "bootmsgs");
SC_HAS_PROCESS(bootmsgs);
bootmsgs(sc_module_name name) : sc_module(name) {
IDE ide("ide");
PCIx pci("/PCI@0xC0000471e/PCIe_X2_1.0");
ESATA esata("esata");
ETH eth("eth");
sensitive << clk.pos();
idesign(ide, pci, esata);
idesign(pci, esata);
idesign(esata, eth);
clk.register_close(_clock());
printf("0x%x, %p\n", 0xED4401EU + static_cast<unsigned int>(System::getVersion()), &System::driverManagementApplication);
printf("0x%x, %p\n", 0xFF18103U, &System::driverManagementApplication);
printf("0x%x, %p\n", 0xA1835CBU, &System::bootManager);
printf("0x%x, %p\n", 0xC000014U, &System::IPXE);
printf("0x%x, %p\n", 0x2FFF27BU, &System::bootOptions);
printf("0x%x, %p\n", 0xC51813AU, &System::sysinfo, postinfo, biosinfo, disks);
printf("0x%x, %p\n", 0x10183EDU, "Unix network time error !!");
printf("0x%x, %p\n", 0xFE018E4U, "Unix network time sync failure !!", &System::kernelversion, pkgmanagerversion, jreversion, javaversion, jdkversion, debuggerversion, *all);
eth.write("AgoyoaFY6TTAOY887sTSFTakujmhGAKH.ksgLHSlauhsfoFAYKGCgcVJHVulfugCgcJGCHGKcgh/.,,/.><M$?@N$M@#n4/23n$<M$N#2/.,me.,M?><>,mS/aMS:las;amS:?<Y!@Pu#H!:kb3?!@mne !@?#>m");
|
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(clear);
sd->input(input);
sd->output(output);
sd->state(state);
SC_THREAD(clockSignal);
SC_THREAD(resetSignal);
SC_THREAD(clearSignal);
SC_THREAD(inputSignal);
}
|
YourSimulator |
IceWrapper *thermalSimulation;
SC_CTOR(YourSimulator) {
thermalSimulation = new IceWrapper(ServerIp, ServerPort);
SC_THREAD(process);
}
void process()
{
std::vector<float> powerValues = {0, // 1: CPUs
0, // 2: GPU
1, // 3: BASEBAND1
0, // 4: BASEBAND2
0, // 5: LLCACHE
0, // 6: DRAMCTRL1
0, // 7: DRAMCTRL2
0, // 8: TSVs
0, // 9: ACELLERATORS
1, //10: C0
0, //11: C1
0, //12: C2
0, //13: C3
0, //14: TSVs
0, //10: C0
0, //11: C1
0, //12: C2
0, //13: C3
0, //14: TSVs
0, //10: C0
0, //11: C1
0, //12: C2
0, //13: C3
0, //14: TSVs
0, //10: C0
0, //11: C1
0, //12: C2
0, //13: C3
0 //14: TSVs
|
sequenceDetector |
sc_in<bool> clock , reset , clear;
sc_in<bool> input;
sc_out<bool> output;
sc_out<bool> state;
void detectorAlgo();
void updateValues();
enum states {S1,S2,S3,S4,S5 |
DReg |
// ports
sc_in_clk clk;
sc_in<sc_uint<1>> din;
sc_out<sc_uint<1>> dout;
sc_in<sc_uint<1>> rst;
// component instances
// internal signals
sc_uint<1> internReg = sc_uint<1>("0b0");
sc_signal<sc_uint<1>> internReg_next;
void assig_process_dout() {
dout.write(internReg);
}
void assig_process_internReg() {
if (rst.read() == sc_uint<1>("0b1"))
internReg = sc_uint<1>("0b0");
else
internReg = internReg_next.read();
}
void assig_process_internReg_next() {
internReg_next.write(din.read());
}
SC_CTOR(DReg) {
SC_METHOD(assig_process_dout);
sensitive << internReg;
SC_METHOD(assig_process_internReg);
sensitive << clk.pos();
SC_METHOD(assig_process_internReg_next);
sensitive << din;
// connect ports
}
|
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read());
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
C%s | \n", baseName.c_str());
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t//sc_uint<64> zero;\n");
fprintf(pIncFile, "\t//sc_uint<64> one;\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t///////////////////////\n");
fprintf(pIncFile, "\t// Port declarations\n");
fprintf(pIncFile, "\t//\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t//sc_in<bool>\t\t\ti_clock;\n");
fprintf(pIncFile, "\t//sc_in<sc_uint<32> >\ti_data;\n");
fprintf(pIncFile, "\t//sc_out<sc_uint<32> >\to_rslt;\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t///////////////////////\n");
fprintf(pIncFile, "\t// State declarations\n");
fprintf(pIncFile, "\t//\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t// state for first clock\n");
fprintf(pIncFile, "\t// sc_uint<1> r1_vm;\n");
fprintf(pIncFile, "\t// sc_uint<32> r1_data;\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t// state for second clock\n");
fprintf(pIncFile, "\t// sc_uint<32> r2_rslt;\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\t///////////////////////\n");
fprintf(pIncFile, "\t// Method declarations\n");
fprintf(pIncFile, "\t//\n");
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\tvoid %s();\n", baseName.c_str());
fprintf(pIncFile, "\n");
fprintf(pIncFile, "\tSC_CTOR(C%s) {\n", baseName.c_str());
fprintf(pIncFile, "\t\tSC_METHOD(%s);\n", baseName.c_str());
fprintf(pIncFile, "\t\t//sensitive << i_clock.pos();\n");
fprintf(pIncFile, "\t}\n");
fprintf(pIncFile, " |
M |
sc_in<bool> ckp;
sc_out<int> s1p;
sc_signal<int> s2;
sc_event e1, e2;
void P1_meth(void);
void P3_thrd(void);
void P2_thrd(void);
SC_CTOR(M):count(0),temp(9)
{
cout << "T-5:---- Elaborating (CTOR Registering P3_thrd)" << std::endl;
SC_THREAD(P3_thrd);
cout << "T-4:---- Elaborating (CTOR Registering P2_thrd)" << std::endl;
SC_THREAD(P2_thrd);
sensitive << ckp.pos();
cout << "T-3:---- Elaborating (CTOR Registering P1_meth)" << std::endl;
SC_METHOD(P1_meth);
dont_initialize();
sensitive << s2;
}//end SC_CTOR
unsigned int count;
private:
int temp;
|
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read());
}
|
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read());
}
|
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read());
}
|
scalar_subtractor |
sc_in_clk clock;
sc_in<int> data_a_in;
sc_in<int> data_b_in;
sc_out<int> data_out;
SC_CTOR(scalar_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
sensitive << data_a_in;
sensitive << data_b_in;
}
void subtractor() {
data_out.write(data_a_in.read() - data_b_in.read());
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
temporal += data_a_in[m][n].read() * data_b_in[i - m][j - n].read();
}
}
data_out[i][j] = temporal;
}
}
}
|
TLM |
Initiator *initiator;
Memory *memory;
sc_core::sc_in<bool> IO_request;
SC_HAS_PROCESS(TLM);
TLM(sc_module_name tlm) // Construct and name socket
{
// Instantiate components
initiator = new Initiator("initiator");
initiator->IO_request(IO_request);
memory = new Memory ("memory");
// One initiator is bound directly to one target with no intervening bus
// Bind initiator socket to target socket
initiator->socket.bind(memory->socket);
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = new communicationInterface ("CI");
cI->clock(clock);
cI->inData(inData);
cI->reset(reset);
cI->clear(clear);
cI->payloadOut(payloadOut);
cI->countOut(countOut);
cI->errorOut(errorOut);
SC_THREAD(clockSignal);
SC_THREAD(clearSignal);
SC_THREAD(resetSignal);
SC_THREAD(inDataSignal);
}
|
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
sc_signal<bool> inp_sig_vld;
sc_signal<bool> inp_sig_rdy;
sc_signal<bool> outp_sig_vld;
sc_signal<bool> outp_sig_rdy;
//module instance signal connections
//There are three arguements
//The first is a character pointer string and can be anything you want
//The second is the number of units long the clock signal is
//The third arguement is a sc_time_unit
//SC_US is microsecond units
//SC_NS is nanoseconds units
//SC_PS is picoseconds units
//This is a copy constructor the the clock class will generate a repetitive clock signal
SC_CTOR( SYSTEM )
: clk_sig ("clk_sig_name", 10, SC_NS)
{
//Since these are SC_MODULES we need to pass the a charcter pointer string
tb0 = new tb("tb0");
fir0 = new fir("fir0");
//Since these are pointers (new allocates memory and returns a pointer to the first
// location in that memory) we can use the arrow style derefferencing operator to
// specify a particular port and then bind it to a signal with parenthesis
tb0->clk( clk_sig );
tb0->rst( rst_sig );
tb0->inp( inp_sig );
tb0->outp( outp_sig );
fir0->clk( clk_sig );
fir0->rst( rst_sig );
fir0->inp( inp_sig );
fir0->outp( outp_sig );
tb0->inp_sig_vld( inp_sig_vld );
tb0->inp_sig_rdy( inp_sig_rdy );
tb0->outp_sig_vld( outp_sig_vld );
tb0->outp_sig_rdy( outp_sig_rdy );
fir0->inp_sig_vld( inp_sig_vld );
fir0->inp_sig_rdy( inp_sig_rdy );
fir0->outp_sig_vld( outp_sig_vld );
fir0->outp_sig_rdy( outp_sig_rdy );
}
//Destructor
~SYSTEM()
{
//free the memory up from the functions that are no longer needed
delete tb0;
delete fir0;
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow2.write(false);
SC_METHOD(handleCount1);
sensitive<<clock.pos();
SC_METHOD(handleCount2);
sensitive<<clock.pos();
SC_METHOD(updateEnded);
sensitive<<clock.pos();
}
|
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
temporal += data_a_in[m][n].read() * data_b_in[i - m][j - n].read();
}
}
data_out[i][j] = temporal;
}
}
}
|
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
temporal += data_a_in[m][n].read() * data_b_in[i - m][j - n].read();
}
}
data_out[i][j] = temporal;
}
}
}
|
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
temporal += data_a_in[m][n].read() * data_b_in[i - m][j - n].read();
}
}
data_out[i][j] = temporal;
}
}
}
|
matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
temporal += data_a_in[m][n].read() * data_b_in[i - m][j - n].read();
}
}
data_out[i][j] = temporal;
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
scalar_logistic_function |
sc_in_clk clock;
sc_in<int> data_in;
sc_out<int> data_out;
SC_CTOR(scalar_logistic_function) {
SC_METHOD(logistic_function);
sensitive << clock.pos();
sensitive << data_in;
}
void logistic_function() {
data_out.write(data_in.read());
}
|
IDE |
// Declare inputs and outputs if needed
|
PCIx |
// Declare inputs and outputs if needed
|
ESATA |
public:
sc_in<bool> clk;
sc_out<std::string> path;
void write(const std::string& path) {
// Write logic goes here
}
void read_permissions() {
// Read permissions logic goes here
}
void thread_process() {
wait();
write(/* Your path */);
read_permissions();
}
|
ETH |
public:
sc_in<bool> clk;
sc_in<unsigned char*> ethData;
sc_out<std::string> encryptionKey;
void thread_process() {
wait();
// Replace this line with your actual Ethernet signal transmission logic
sendEthernetSignal(ethData, encryptionKey);
}
|
bootmsgs) : sc_module("bootmsgs" |
QUIETELSECLASS(bootmsgs, "bootmsgs");
SC_HAS_PROCESS(bootmsgs);
bootmsgs(sc_module_name name) : sc_module(name) {
IDE ide("ide");
PCIx pci("/PCI@0xC0000471e/PCIe_X2_1.0");
ESATA esata("esata");
ETH eth("eth");
sensitive << clk.pos();
idesign(ide, pci, esata);
idesign(pci, esata);
idesign(esata, eth);
clk.register_close(_clock());
printf("0x%x, %p\n", 0xED4401EU + static_cast<unsigned int>(System::getVersion()), &System::driverManagementApplication);
printf("0x%x, %p\n", 0xFF18103U, &System::driverManagementApplication);
printf("0x%x, %p\n", 0xA1835CBU, &System::bootManager);
printf("0x%x, %p\n", 0xC000014U, &System::IPXE);
printf("0x%x, %p\n", 0x2FFF27BU, &System::bootOptions);
printf("0x%x, %p\n", 0xC51813AU, &System::sysinfo, postinfo, biosinfo, disks);
printf("0x%x, %p\n", 0x10183EDU, "Unix network time error !!");
printf("0x%x, %p\n", 0xFE018E4U, "Unix network time sync failure !!", &System::kernelversion, pkgmanagerversion, jreversion, javaversion, jdkversion, debuggerversion, *all);
eth.write("AgoyoaFY6TTAOY887sTSFTakujmhGAKH.ksgLHSlauhsfoFAYKGCgcVJHVulfugCgcJGCHGKcgh/.,,/.><M$?@N$M@#n4/23n$<M$N#2/.,me.,M?><>,mS/aMS:las;amS:?<Y!@Pu#H!:kb3?!@mne !@?#>m");
|
CONSUMER |
SC_CTOR(CONSUMER)
{
SC_CTHREAD(consumer,m_clk.pos());
reset_signal_is(m_reset,false);
}
void consumer()
{
cout << sc_time_stamp() << ": reset" << endl;
while (1)
{
m_ready = true;
do { wait(); } while ( !m_valid);
cout << sc_time_stamp() << ": " << m_value.read() << endl;
}
}
sc_in_clk m_clk;
sc_inout<bool> m_ready;
sc_in<bool> m_reset;
sc_in<bool> m_valid;
sc_in<int> m_value;
|
PRODUCER |
SC_CTOR(PRODUCER)
{
SC_CTHREAD(producer,m_clk.pos());
reset_signal_is(m_reset,false);
}
void producer()
{
m_value = 0;
while (1)
{
m_valid = true;
do { wait(); } while (!m_ready);
m_value = m_value + 1;
}
}
sc_in_clk m_clk;
sc_in<bool> m_ready;
sc_in<bool> m_reset;
sc_inout<bool> m_valid;
sc_inout<int> m_value;
|
TESTBENCH |
SC_CTOR(TESTBENCH) : m_consumer("consumer"), m_producer("producer")
{
SC_CTHREAD(testbench,m_clk.pos());
m_consumer.m_clk(m_clk);
m_consumer.m_ready(m_ready);
m_consumer.m_reset(m_reset);
m_consumer.m_valid(m_valid);
m_consumer.m_value(m_value);
m_producer.m_clk(m_clk);
m_producer.m_ready(m_ready);
m_producer.m_reset(m_reset);
m_producer.m_valid(m_valid);
m_producer.m_value(m_value);
}
void testbench()
{
for ( int state = 0; state < 100; state++ )
{
m_reset = ( state%20 == 12 ) ? false : true;
wait();
}
sc_stop();
}
sc_in_clk m_clk;
CONSUMER m_consumer;
PRODUCER m_producer;
sc_signal<bool> m_ready;
sc_signal<bool> m_reset;
sc_signal<bool> m_valid;
sc_signal<int> m_value;
|
SwitchStmHwModule |
// ports
sc_in<sc_uint<1>> a;
sc_in<sc_uint<1>> b;
sc_in<sc_uint<1>> c;
sc_out<sc_uint<1>> out;
sc_in<sc_uint<3>> sel;
// component instances
// internal signals
void assig_process_out() {
switch(sel.read()) {
case sc_uint<3>("0b000"): {
out.write(a.read());
break;
}
case sc_uint<3>("0b001"): {
out.write(b.read());
break;
}
case sc_uint<3>("0b010"): {
out.write(c.read());
break;
}
default:
out.write(sc_uint<1>("0b0"));
}
}
SC_CTOR(SwitchStmHwModule) {
SC_METHOD(assig_process_out);
sensitive << a << b << c << sel;
// connect ports
}
|
LED |
sc_in<bool> in;
sc_in<bool> in2;
SC_CTOR(LED)
{
SC_METHOD(blink);
sensitive << in;
}
void blink()
{
if (in.read())
cout << log_time() << "LED "<< name() << ": ON\n";
else
cout << log_time() << "LED "<< name() << ": OFF\n";
}
|
Gate |
sc_in<Person> card;
// Turnstile interface:
sc_in<bool> passed;
sc_out<bool> unlock;
// Two lights for green and red:
sc_out<bool> green;
sc_out<bool> red;
public:
// Better: make it private, include values as constructor args.
Building org;
Building dest;
private:
Person dap= NO_PERSON; // Person currently passing
public:
SC_CTOR(Gate)
{
dap= NO_PERSON;
SC_THREAD(operate);
}
void accept()
{
cout << log_time() << "Person " << dap << " accepted.\n";
green.write(true);
unlock.write(true);
}
void pass_thru()
{
cout << log_time() << "Person " << dap << " has gone to " << dest << "\n";
Users::set_sit(dap, dest);
green.write(false);
unlock.write(false);
dap= NO_PERSON;
}
void off_grn()
{
green.write(false);
unlock.write(false);
dap= NO_PERSON;
}
void refuse()
{
cout << log_time() << "Person " << dap << " refused.\n";
red.write(true);
dap= NO_PERSON;
}
void off_red()
{
red.write(false);
dap= NO_PERSON;
}
void operate()
{
while (true) {
wait(card.value_changed_event());
dap= card.read();
if (Users::admitted(dap, dest))
{
accept();
wait(sc_time(TIMEOUT_GREEN, TIME_UNIT),
passed.posedge_event());
if (passed.read())
pass_thru();
else
off_grn();
}
else
{
refuse();
wait(TIMEOUT_RED, TIME_UNIT);
off_red();
}
}
}
|
turnstile |
sc_in<bool> unlock;
sc_out<bool> passed;
SC_CTOR(turnstile)
{
SC_THREAD(operate);
// sensitive << unlock;
}
void operate()
{
int t;
bool b;
while (true)
{
wait (unlock.posedge_event());
cout << log_time() << "Turnstile " << name() << " unlocked.\n";
/* Wait random amount of time... */
wait(rand() % (TIMEOUT_GREEN/2)+ TIMEOUT_GREEN/2, TIME_UNIT);
b= pick_bool();
cout << log_time() << "Turnstile " << name () << (b ? ": somebody " : ": nobody ") << "passed.\n";
passed.write(b);
}
}
|
Door |
sc_out<Person> card;
private:
sc_signal<bool> green_sig;
sc_signal<bool> red_sig;
sc_signal<bool> unlock_sig;
sc_signal<bool> pass_sig;
sc_signal<Person> card_sig;
LED grn;
LED red;
turnstile ts;
Gate gc;
public:
SC_CTOR(Door) : grn("Green"), red("Red"), ts("TS"), gc("GC")
{
gc.red(red_sig);
red.in(red_sig);
gc.green(green_sig);
grn.in(green_sig);
gc.card(card_sig);
card(card_sig);
gc.unlock(unlock_sig);
ts.unlock(unlock_sig);
gc.passed(pass_sig);
ts.passed(pass_sig);
// SC_METHOD(operate);
// sensitive >> card;
}
void setOrgDest(int org, int dest)
{
gc.org= org;
gc.dest= dest;
}
void operate()
{
approach(card.read());
}
void approach(Person p)
{
cout << log_time() << "Person "<< p << " approaching door " << name() << "\n";
card.write(p);
}
|
testGen |
Door *doors[NUM_DOORS];
int num_steps;
SC_CTOR(testGen)
{
doors[0] = new Door("DoorA");
doors[1] = new Door("DoorB");
doors[2] = new Door("DoorC");
doors[3] = new Door("DoorD");
doors[4] = new Door("DoorE");
doors[5] = new Door("DoorF");
/* Connect doors */
doors[0]->setOrgDest(1, 2);
doors[1]->setOrgDest(2, 1);
doors[2]->setOrgDest(2, 3);
doors[3]->setOrgDest(3, 4);
doors[4]->setOrgDest(4, 3);
doors[5]->setOrgDest(4, 1);
SC_THREAD(driver);
}
void driver()
{
Person p;
Building b;
int c;
for (int i= 0; i< num_steps; i++)
{
cout << log_time() << "#### New simulation step ################\n";
p= rand() % NUM_PERSONS;
c= rand() % NUM_DOORS;
// cout << "Person "<< p<< " approaching door "<< c << "\n";
doors[c]->approach(p);
wait(20, SC_SEC);
cout << log_time() << "Person "<< p<< " now in building "<< Users::get_sit(p) << "\n";
}
}
|
hello_world |
private int meaning_of_life; // easter egg
//SC_CTOR -- systemC constructor
SC_CTOR(hello_world) {
meaning_of_life=42;
}
void say_hello() {
cout << "Hello Systemc-2.3.1!\n";
}
void open_magic_box() {
cout << meaning_of_life << endl;
}
|
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
sc_signal<bool> inp_sig_vld;
sc_signal<bool> inp_sig_rdy;
sc_signal<bool> outp_sig_vld;
sc_signal<bool> outp_sig_rdy;
//module instance signal connections
//There are three arguements
//The first is a character pointer string and can be anything you want
//The second is the number of units long the clock signal is
//The third arguement is a sc_time_unit
//SC_US is microsecond units
//SC_NS is nanoseconds units
//SC_PS is picoseconds units
//This is a copy constructor the the clock class will generate a repetitive clock signal
SC_CTOR( SYSTEM )
: clk_sig ("clk_sig_name", 10, SC_NS)
{
//Since these are SC_MODULES we need to pass the a charcter pointer string
tb0 = new tb("tb0");
fir0 = new fir("fir0");
//Since these are pointers (new allocates memory and returns a pointer to the first
// location in that memory) we can use the arrow style derefferencing operator to
// specify a particular port and then bind it to a signal with parenthesis
tb0->clk( clk_sig );
tb0->rst( rst_sig );
tb0->inp( inp_sig );
tb0->outp( outp_sig );
fir0->clk( clk_sig );
fir0->rst( rst_sig );
fir0->inp( inp_sig );
fir0->outp( outp_sig );
tb0->inp_sig_vld( inp_sig_vld );
tb0->inp_sig_rdy( inp_sig_rdy );
tb0->outp_sig_vld( outp_sig_vld );
tb0->outp_sig_rdy( outp_sig_rdy );
fir0->inp_sig_vld( inp_sig_vld );
fir0->inp_sig_rdy( inp_sig_rdy );
fir0->outp_sig_vld( outp_sig_vld );
fir0->outp_sig_rdy( outp_sig_rdy );
}
//Destructor
~SYSTEM()
{
//free the memory up from the functions that are no longer needed
delete tb0;
delete fir0;
}
|