module_name
stringlengths 1
2.17k
| module_content
stringlengths 6
11.3k
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|---|---|
gate |
// inputs
sc_in<bool> inA, inB;
// outputs
sc_out<bool> out;
// C function
void do_something()
{
out.write(inA.read() || inB.read());
}
// constructor
SC_CTOR(gate)
{
// register method
SC_METHOD(do_something);
}
|
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow2.write(false);
SC_METHOD(handleCount1);
sensitive<<clock.pos();
SC_METHOD(handleCount2);
sensitive<<clock.pos();
SC_METHOD(updateEnded);
sensitive<<clock.pos();
}
|
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = new communicationInterface ("CI");
cI->clock(clock);
cI->inData(inData);
cI->reset(reset);
cI->clear(clear);
cI->payloadOut(payloadOut);
cI->countOut(countOut);
cI->errorOut(errorOut);
SC_THREAD(clockSignal);
SC_THREAD(clearSignal);
SC_THREAD(resetSignal);
SC_THREAD(inDataSignal);
}
|
TLM |
Initiator *initiator;
Memory *memory;
sc_core::sc_in<bool> IO_request;
SC_HAS_PROCESS(TLM);
TLM(sc_module_name tlm) // Construct and name socket
{
// Instantiate components
initiator = new Initiator("initiator");
initiator->IO_request(IO_request);
memory = new Memory ("memory");
// One initiator is bound directly to one target with no intervening bus
// Bind initiator socket to target socket
initiator->socket.bind(memory->socket);
}
|
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(clear);
sd->input(input);
sd->output(output);
sd->state(state);
SC_THREAD(clockSignal);
SC_THREAD(resetSignal);
SC_THREAD(clearSignal);
SC_THREAD(inputSignal);
}
|
SYSTEM |
//Module Declarations
tb *tb0;
full_adder *full_adder0;
//Local signal declarations
sc_signal<bool> sig_inp_a, sig_inp_b,
sig_inp_cin, sig_sum, sig_co;
SC_HAS_PROCESS(SYSTEM);
SYSTEM( sc_module_name nm) : sc_module (nm) {
//Module instance signal connections
tb0 = new tb("tb0");
tb0->inp_a( sig_inp_a );
tb0->inp_b( sig_inp_b );
tb0->inp_cin( sig_inp_cin );
tb0->sum( sig_sum );
tb0->co( sig_co );
full_adder0 = new full_adder("full_adder0");
full_adder0->inp_a( sig_inp_a );
full_adder0->inp_b( sig_inp_b );
full_adder0->inp_cin( sig_inp_cin );
full_adder0->sum( sig_sum );
full_adder0->co( sig_co );
}
//Destructor
~SYSTEM(){
delete tb0;
delete full_adder0;
}
|
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contOut;
sc_in<sc_uint<32>> d;
sc_in<sc_uint<1>> e;
sc_out<sc_uint<1>> f;
sc_out<sc_uint<16>> fitted;
sc_out<sc_uint<8>> g;
sc_out<sc_uint<8>> h;
sc_in<sc_uint<2>> i;
sc_out<sc_uint<8>> j;
sc_out<sc_uint<32>> k;
sc_out<sc_uint<1>> out;
sc_out<sc_uint<1>> output;
sc_in<sc_uint<1>> rst_n;
sc_out<sc_uint<8>> sc_signal_0;
// component instances
// internal signals
sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
sc_int<8> fallingEdgeRam[4];
sc_uint<1> r = sc_uint<1>("0b0");
sc_uint<2> r_0 = sc_uint<2>("0b00");
sc_uint<2> r_1 = sc_uint<2>("0b00");
sc_signal<sc_uint<1>> r_next;
sc_signal<sc_uint<2>> r_next_0;
sc_signal<sc_uint<2>> r_next_1;
sc_uint<8> rom[4] = {sc_uint<8>("0x00"),
sc_uint<8>("0x01"),
sc_uint<8>("0x02"),
sc_uint<8>("0x03"),
|
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contOut;
sc_in<sc_uint<32>> d;
sc_in<sc_uint<1>> e;
sc_out<sc_uint<1>> f;
sc_out<sc_uint<16>> fitted;
sc_out<sc_uint<8>> g;
sc_out<sc_uint<8>> h;
sc_in<sc_uint<2>> i;
sc_out<sc_uint<8>> j;
sc_out<sc_uint<32>> k;
sc_out<sc_uint<1>> out;
sc_out<sc_uint<1>> output;
sc_in<sc_uint<1>> rst_n;
sc_out<sc_uint<8>> sc_signal_0;
// component instances
// internal signals
sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
sc_int<8> fallingEdgeRam[4];
sc_uint<1> r = sc_uint<1>("0b0");
sc_uint<2> r_0 = sc_uint<2>("0b00");
sc_uint<2> r_1 = sc_uint<2>("0b00");
sc_signal<sc_uint<1>> r_next;
sc_signal<sc_uint<2>> r_next_0;
sc_signal<sc_uint<2>> r_next_1;
sc_uint<8> rom[4] = {sc_uint<8>("0x00"),
sc_uint<8>("0x01"),
sc_uint<8>("0x02"),
sc_uint<8>("0x03"),
|
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{
}
|
nand_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void nand_process(void)
{
and_process(); // c = a and b
c = !c.read(); // c = not c
}
void and_process ( void )
{
c = a.read() && b.read();
}
void test_process(void)
{
assert( c.read() == ( a.read() && b.read() ) );
}
SC_CTOR(nand_gate)
{
}
|
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(clear);
sd->input(input);
sd->output(output);
sd->state(state);
SC_THREAD(clockSignal);
SC_THREAD(resetSignal);
SC_THREAD(clearSignal);
SC_THREAD(inputSignal);
}
|
hello_world |
private int meaning_of_life; // easter egg
//SC_CTOR -- systemC constructor
SC_CTOR(hello_world) {
meaning_of_life=42;
}
void say_hello() {
cout << "Hello Systemc-2.3.1!\n";
}
void open_magic_box() {
cout << meaning_of_life << endl;
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
sc_signal<bool> inp_sig_vld;
sc_signal<bool> inp_sig_rdy;
sc_signal<bool> outp_sig_vld;
sc_signal<bool> outp_sig_rdy;
//module instance signal connections
//There are three arguements
//The first is a character pointer string and can be anything you want
//The second is the number of units long the clock signal is
//The third arguement is a sc_time_unit
//SC_US is microsecond units
//SC_NS is nanoseconds units
//SC_PS is picoseconds units
//This is a copy constructor the the clock class will generate a repetitive clock signal
SC_CTOR( SYSTEM )
: clk_sig ("clk_sig_name", 10, SC_NS)
{
//Since these are SC_MODULES we need to pass the a charcter pointer string
tb0 = new tb("tb0");
fir0 = new fir("fir0");
//Since these are pointers (new allocates memory and returns a pointer to the first
// location in that memory) we can use the arrow style derefferencing operator to
// specify a particular port and then bind it to a signal with parenthesis
tb0->clk( clk_sig );
tb0->rst( rst_sig );
tb0->inp( inp_sig );
tb0->outp( outp_sig );
fir0->clk( clk_sig );
fir0->rst( rst_sig );
fir0->inp( inp_sig );
fir0->outp( outp_sig );
tb0->inp_sig_vld( inp_sig_vld );
tb0->inp_sig_rdy( inp_sig_rdy );
tb0->outp_sig_vld( outp_sig_vld );
tb0->outp_sig_rdy( outp_sig_rdy );
fir0->inp_sig_vld( inp_sig_vld );
fir0->inp_sig_rdy( inp_sig_rdy );
fir0->outp_sig_vld( outp_sig_vld );
fir0->outp_sig_rdy( outp_sig_rdy );
}
//Destructor
~SYSTEM()
{
//free the memory up from the functions that are no longer needed
delete tb0;
delete fir0;
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
tensor_matrix_convolution |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(tensor_matrix_convolution) {
SC_METHOD(convolution);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
}
sensitive << data_b_in[i][j];
}
}
}
void convolution() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
int temporal = 0;
for (int m = 0; m < i; m++) {
for (int n = 0; n < j; n++) {
for (int p = 0; p < k; p++) {
temporal += data_a_in[m][n][p].read() * data_b_in[i - m][j - n].read();
}
}
}
data_out[i][j] = temporal;
}
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow2.write(false);
SC_METHOD(handleCount1);
sensitive<<clock.pos();
SC_METHOD(handleCount2);
sensitive<<clock.pos();
SC_METHOD(updateEnded);
sensitive<<clock.pos();
}
|
DUT |
SC_CTOR(DUT)
{
SC_THREAD(exec)
sensitive << m_clk.pos();
// CONNECT PORTS TO THEIR BACKING SIGNALS:
m_in_bigint4(m_back_in_bigint4);
m_inout_bigint4(m_back_inout_bigint4);
m_in_biguint4(m_back_in_biguint4);
m_inout_biguint4(m_back_inout_biguint4);
m_in_int4(m_back_in_int4);
m_inout_int4(m_back_inout_int4);
m_in_uint4(m_back_in_uint4);
m_inout_uint4(m_back_inout_uint4);
}
void exec()
{
// TEST RIGHT HAND CONCATENATION:
m_back_in_bigint4 = 1;
m_back_inout_bigint4 = 2;
m_back_in_biguint4 = 3;
m_back_inout_biguint4 = 4;
m_back_in_int4 = 5;
m_back_inout_int4 = 6;
m_back_in_uint4 = 7;
m_back_inout_uint4 = 8;
wait();
DISPLAY((
m_in_bigint4,
m_inout_bigint4,
m_in_biguint4,
m_inout_biguint4,
m_in_int4,
m_inout_int4,
m_in_uint4,
m_inout_uint4
),hex);
m_signal_bigint8 = ( m_in_bigint4,m_inout_uint4);
m_signal_biguint8 = ( m_inout_bigint4,m_in_uint4);
m_signal_int8 = ( m_in_biguint4,m_inout_int4);
m_signal_uint8 = ( m_inout_biguint4,m_in_int4);
wait();
DISPLAY(m_signal_bigint8,hex);
DISPLAY(m_signal_biguint8,hex);
DISPLAY(m_signal_int8,hex);
DISPLAY(m_signal_uint8,hex);
// TEST LEFT HAND CONCATENATION:
(m_inout_uint4,m_signal_biguint8) = 0x123;
wait();
(m_signal_bigint8,m_inout_bigint4) = (m_inout_uint4,m_signal_biguint8);
(m_signal_biguint8,m_inout_biguint4) = 0x456;
(m_inout_int4,m_signal_int8) = 0x978;
(m_inout_uint4,m_signal_uint8) = 0xcab;
wait();
DISPLAY(m_signal_bigint8,hex);
DISPLAY(m_inout_bigint4,hex);
DISPLAY(m_signal_biguint8,hex);
DISPLAY(m_inout_biguint4,hex);
DISPLAY(m_signal_int8,hex);
DISPLAY(m_inout_int4,hex);
DISPLAY(m_signal_uint8,hex);
DISPLAY(m_inout_uint4,hex);
// TEST MATH OPERATIONS:
//
// Note there is not need to call .read() methods!
m_nb_signal_bigint8 = -1;
m_nb_signal_biguint8 = 255;
m_nb_signal_int8 = -2;
m_nb_signal_uint8 = 128;
m_signal_bigint8 = -1;
m_signal_biguint8 = 255;
m_signal_int8 = -2;
m_signal_uint8 = 128;
wait();
TEST(m_signal_bigint8*m_signal_biguint8,
m_nb_signal_bigint8*m_nb_signal_biguint8,dec);
TEST(m_signal_bigint8*m_signal_uint8,
m_nb_signal_bigint8*m_nb_signal_uint8,dec);
TEST(m_signal_int8*m_signal_biguint8,
m_nb_signal_int8*m_nb_signal_biguint8,dec);
TEST(m_signal_int8*m_signal_uint8,
m_nb_signal_int8*m_nb_signal_uint8,dec);
TEST(m_signal_bigint8+m_signal_biguint8,
m_nb_signal_bigint8+m_nb_signal_biguint8,dec);
TEST(m_signal_bigint8+m_signal_uint8,
m_nb_signal_bigint8+m_nb_signal_uint8,dec);
TEST(m_signal_int8+m_signal_biguint8,
m_nb_signal_int8+m_nb_signal_biguint8,dec);
TEST(m_signal_int8+m_signal_uint8,
m_nb_signal_int8+m_nb_signal_uint8,dec);
TEST(m_signal_bigint8-m_signal_biguint8,
m_nb_signal_bigint8-m_nb_signal_biguint8,dec);
TEST(m_signal_bigint8-m_signal_uint8,
m_nb_signal_bigint8-m_nb_signal_uint8,dec);
TEST(m_signal_int8-m_signal_biguint8,
m_nb_signal_int8-m_nb_signal_biguint8,dec);
TEST(m_signal_int8-m_signal_uint8,
m_nb_signal_int8-m_nb_signal_uint8,dec);
TEST(m_signal_int8+m_signal_uint8*m_signal_bigint8-m_signal_biguint8,
m_nb_signal_int8+m_nb_signal_uint8*m_nb_signal_bigint8-m_nb_signal_biguint8,dec);
m_nb_in_bigint4 = -1;
m_nb_in_biguint4 = 15;
m_nb_in_int4 = -2;
m_nb_in_uint4 = 8;
m_back_in_bigint4 = -1;
m_back_in_biguint4 = 15;
m_back_in_int4 = -2;
m_back_in_uint4 = 8;
wait();
TEST(m_in_bigint4*m_in_biguint4,
m_nb_in_bigint4*m_nb_in_biguint4,dec);
TEST(m_in_bigint4*m_in_uint4,
m_nb_in_bigint4*m_nb_in_uint4,dec);
TEST(m_in_int4*m_in_biguint4,
m_nb_in_int4*m_nb_in_biguint4,dec);
TEST(m_in_int4*m_in_uint4,
m_nb_in_int4*m_nb_in_uint4,dec);
TEST(m_in_bigint4+m_in_biguint4,
m_nb_in_bigint4+m_nb_in_biguint4,dec);
TEST(m_in_bigint4+m_in_uint4,
m_nb_in_bigint4+m_nb_in_uint4,dec);
TEST(m_in_int4+m_in_biguint4,
m_nb_in_int4+m_nb_in_biguint4,dec);
TEST(m_in_int4+m_in_uint4,
m_nb_in_int4+m_nb_in_uint4,dec);
TEST(m_in_bigint4-m_in_biguint4,
m_nb_in_bigint4-m_nb_in_biguint4,dec);
TEST(m_in_bigint4-m_in_uint4,
m_nb_in_bigint4-m_nb_in_uint4,dec);
TEST(m_in_int4-m_in_biguint4,
m_nb_in_int4-m_nb_in_biguint4,dec);
TEST(m_in_int4-m_in_uint4,
m_nb_in_int4-m_nb_in_uint4,dec);
TEST(m_in_int4+m_in_uint4*m_in_bigint4-m_in_biguint4,
m_nb_in_int4+m_nb_in_uint4*m_nb_in_bigint4-m_nb_in_biguint4,dec);
sc_stop();
}
sc_in<bool> m_clk;
sc_signal<sc_bigint<4> > m_back_in_bigint4;
sc_signal<sc_bigint<4> > m_back_inout_bigint4;
sc_signal<sc_biguint<4> > m_back_in_biguint4;
sc_signal<sc_biguint<4> > m_back_inout_biguint4;
sc_signal<sc_int<4> > m_back_in_int4;
sc_signal<sc_int<4> > m_back_inout_int4;
sc_signal<sc_uint<4> > m_back_in_uint4;
sc_signal<sc_uint<4> > m_back_inout_uint4;
sc_in<sc_bigint<4> > m_in_bigint4;
sc_inout<sc_bigint<4> > m_inout_bigint4;
sc_signal<sc_bigint<8> > m_signal_bigint8;
sc_in<sc_biguint<4> > m_in_biguint4;
sc_inout<sc_biguint<4> > m_inout_biguint4;
sc_signal<sc_biguint<8> > m_signal_biguint8;
sc_in<sc_int<4> > m_in_int4;
sc_inout<sc_int<4> > m_inout_int4;
sc_signal<sc_int<8> > m_signal_int8;
sc_in<sc_uint<4> > m_in_uint4;
sc_inout<sc_uint<4> > m_inout_uint4;
sc_signal<sc_uint<8> > m_signal_uint8;
sc_bigint<4> m_nb_in_bigint4;
sc_bigint<4> m_nb_inout_bigint4;
sc_bigint<8> m_nb_signal_bigint8;
sc_biguint<4> m_nb_in_biguint4;
sc_biguint<4> m_nb_inout_biguint4;
sc_biguint<8> m_nb_signal_biguint8;
sc_int<4> m_nb_in_int4;
sc_int<4> m_nb_inout_int4;
sc_int<8> m_nb_signal_int8;
sc_uint<4> m_nb_in_uint4;
sc_uint<4> m_nb_inout_uint4;
sc_uint<8> m_nb_signal_uint8;
|
SYSTEM |
//module declarations
//Done by doing module_name Pointer_to_instance i.e. name *iname;
tb *tb0;
fir *fir0;
//signal declarations
sc_signal<bool> rst_sig;
sc_signal< sc_int<16> > inp_sig;
sc_signal< sc_int<16> > outp_sig;
sc_clock clk_sig;
sc_signal<bool> inp_sig_vld;
sc_signal<bool> inp_sig_rdy;
sc_signal<bool> outp_sig_vld;
sc_signal<bool> outp_sig_rdy;
//module instance signal connections
//There are three arguements
//The first is a character pointer string and can be anything you want
//The second is the number of units long the clock signal is
//The third arguement is a sc_time_unit
//SC_US is microsecond units
//SC_NS is nanoseconds units
//SC_PS is picoseconds units
//This is a copy constructor the the clock class will generate a repetitive clock signal
SC_CTOR( SYSTEM )
: clk_sig ("clk_sig_name", 10, SC_NS)
{
//Since these are SC_MODULES we need to pass the a charcter pointer string
tb0 = new tb("tb0");
fir0 = new fir("fir0");
//Since these are pointers (new allocates memory and returns a pointer to the first
// location in that memory) we can use the arrow style derefferencing operator to
// specify a particular port and then bind it to a signal with parenthesis
tb0->clk( clk_sig );
tb0->rst( rst_sig );
tb0->inp( inp_sig );
tb0->outp( outp_sig );
fir0->clk( clk_sig );
fir0->rst( rst_sig );
fir0->inp( inp_sig );
fir0->outp( outp_sig );
tb0->inp_sig_vld( inp_sig_vld );
tb0->inp_sig_rdy( inp_sig_rdy );
tb0->outp_sig_vld( outp_sig_vld );
tb0->outp_sig_rdy( outp_sig_rdy );
fir0->inp_sig_vld( inp_sig_vld );
fir0->inp_sig_rdy( inp_sig_rdy );
fir0->outp_sig_vld( outp_sig_vld );
fir0->outp_sig_rdy( outp_sig_rdy );
}
//Destructor
~SYSTEM()
{
//free the memory up from the functions that are no longer needed
delete tb0;
delete fir0;
}
|
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = new communicationInterface ("CI");
cI->clock(clock);
cI->inData(inData);
cI->reset(reset);
cI->clear(clear);
cI->payloadOut(payloadOut);
cI->countOut(countOut);
cI->errorOut(errorOut);
SC_THREAD(clockSignal);
SC_THREAD(clearSignal);
SC_THREAD(resetSignal);
SC_THREAD(inDataSignal);
}
|
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
sensitive << data_b_in[i][j][k];
}
}
}
}
void subtractor() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
data_out[i][j][k].write(data_a_in[i][j][k].read() - data_b_in[i][j][k].read());
}
}
}
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation()
{
m_thread=std::thread( [this] { this->process(); } );
}
void process()
{
std::this_thread::sleep_for(std::chrono::seconds(1));
// asynchronous notification from a separate thread
when.notify(sc_time(10,SC_NS));
}
#else
void start_of_simulation()
{
// no threading support, notifiy directly
when.notify(sc_time(10,SC_NS));
}
#endif // C++11 threading support
private:
void call_stop()
{
cout << "Asked to stop at time " << sc_time_stamp() << endl;
barked=true;
sc_stop();
}
void end_of_simulation()
{
sc_assert(barked==true);
cout << "The dog barks before the end of simulation" << endl;
}
|
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
matrix_multiplier |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN];
SC_CTOR(matrix_multiplier) {
SC_METHOD(multiplier);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
sensitive << data_a_in[i][j];
sensitive << data_b_in[i][j];
}
}
}
void multiplier() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
data_out[i][j].write(data_a_in[i][j].read() * data_b_in[i][j].read());
}
}
}
|
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
sensitive << data_b_in[i][j][k];
}
}
}
}
void subtractor() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
data_out[i][j][k].write(data_a_in[i][j][k].read() - data_b_in[i][j][k].read());
}
}
}
}
|
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
sensitive << data_b_in[i][j][k];
}
}
}
}
void subtractor() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
data_out[i][j][k].write(data_a_in[i][j][k].read() - data_b_in[i][j][k].read());
}
}
}
}
|
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
sensitive << data_b_in[i][j][k];
}
}
}
}
void subtractor() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
data_out[i][j][k].write(data_a_in[i][j][k].read() - data_b_in[i][j][k].read());
}
}
}
}
|
tensor_subtractor |
sc_in_clk clock;
sc_in<sc_int<64>> data_a_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_in<sc_int<64>> data_b_in[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
sc_out<sc_int<64>> data_out[SIZE_I_IN][SIZE_J_IN][SIZE_K_IN];
SC_CTOR(tensor_subtractor) {
SC_METHOD(subtractor);
sensitive << clock.pos();
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
sensitive << data_a_in[i][j][k];
sensitive << data_b_in[i][j][k];
}
}
}
}
void subtractor() {
for (int i = 0; i < SIZE_I_IN; i++) {
for (int j = 0; j < SIZE_J_IN; j++) {
for (int k = 0; k < SIZE_K_IN; k++) {
data_out[i][j][k].write(data_a_in[i][j][k].read() - data_b_in[i][j][k].read());
}
}
}
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation()
{
m_thread=std::thread( [this] { this->process(); } );
}
void process()
{
std::this_thread::sleep_for(std::chrono::seconds(1));
// asynchronous notification from a separate thread
when.notify(sc_time(10,SC_NS));
}
#else
void start_of_simulation()
{
// no threading support, notifiy directly
when.notify(sc_time(10,SC_NS));
}
#endif // C++11 threading support
private:
void call_stop()
{
cout << "Asked to stop at time " << sc_time_stamp() << endl;
barked=true;
sc_stop();
}
void end_of_simulation()
{
sc_assert(barked==true);
cout << "The dog barks before the end of simulation" << endl;
}
|
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation()
{
m_thread=std::thread( [this] { this->process(); } );
}
void process()
{
std::this_thread::sleep_for(std::chrono::seconds(1));
// asynchronous notification from a separate thread
when.notify(sc_time(10,SC_NS));
}
#else
void start_of_simulation()
{
// no threading support, notifiy directly
when.notify(sc_time(10,SC_NS));
}
#endif // C++11 threading support
private:
void call_stop()
{
cout << "Asked to stop at time " << sc_time_stamp() << endl;
barked=true;
sc_stop();
}
void end_of_simulation()
{
sc_assert(barked==true);
cout << "The dog barks before the end of simulation" << endl;
}
|
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation()
{
m_thread=std::thread( [this] { this->process(); } );
}
void process()
{
std::this_thread::sleep_for(std::chrono::seconds(1));
// asynchronous notification from a separate thread
when.notify(sc_time(10,SC_NS));
}
#else
void start_of_simulation()
{
// no threading support, notifiy directly
when.notify(sc_time(10,SC_NS));
}
#endif // C++11 threading support
private:
void call_stop()
{
cout << "Asked to stop at time " << sc_time_stamp() << endl;
barked=true;
sc_stop();
}
void end_of_simulation()
{
sc_assert(barked==true);
cout << "The dog barks before the end of simulation" << endl;
}
|
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
watchDog |
async_event when;
bool barked;
public:
SC_CTOR(watchDog) : barked(false)
{
SC_METHOD(call_stop);
sensitive << when;
dont_initialize();
}
#if SC_CPLUSPLUS >= 201103L // C++11 threading support
~watchDog()
{
m_thread.join();
}
private:
std::thread m_thread;
void start_of_simulation()
{
m_thread=std::thread( [this] { this->process(); } );
}
void process()
{
std::this_thread::sleep_for(std::chrono::seconds(1));
// asynchronous notification from a separate thread
when.notify(sc_time(10,SC_NS));
}
#else
void start_of_simulation()
{
// no threading support, notifiy directly
when.notify(sc_time(10,SC_NS));
}
#endif // C++11 threading support
private:
void call_stop()
{
cout << "Asked to stop at time " << sc_time_stamp() << endl;
barked=true;
sc_stop();
}
void end_of_simulation()
{
sc_assert(barked==true);
cout << "The dog barks before the end of simulation" << endl;
}
|
activity |
SC_CTOR(activity)
{
SC_THREAD(busy);
}
void busy()
{
cout << "I'm busy!"<<endl;
}
|
SwitchStmHwModule |
// ports
sc_in<sc_uint<1>> a;
sc_in<sc_uint<1>> b;
sc_in<sc_uint<1>> c;
sc_out<sc_uint<1>> out;
sc_in<sc_uint<3>> sel;
// component instances
// internal signals
void assig_process_out() {
switch(sel.read()) {
case sc_uint<3>("0b000"): {
out.write(a.read());
break;
}
case sc_uint<3>("0b001"): {
out.write(b.read());
break;
}
case sc_uint<3>("0b010"): {
out.write(c.read());
break;
}
default:
out.write(sc_uint<1>("0b0"));
}
}
SC_CTOR(SwitchStmHwModule) {
SC_METHOD(assig_process_out);
sensitive << a << b << c << sel;
// connect ports
}
|
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contOut;
sc_in<sc_uint<32>> d;
sc_in<sc_uint<1>> e;
sc_out<sc_uint<1>> f;
sc_out<sc_uint<16>> fitted;
sc_out<sc_uint<8>> g;
sc_out<sc_uint<8>> h;
sc_in<sc_uint<2>> i;
sc_out<sc_uint<8>> j;
sc_out<sc_uint<32>> k;
sc_out<sc_uint<1>> out;
sc_out<sc_uint<1>> output;
sc_in<sc_uint<1>> rst_n;
sc_out<sc_uint<8>> sc_signal_0;
// component instances
// internal signals
sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
sc_int<8> fallingEdgeRam[4];
sc_uint<1> r = sc_uint<1>("0b0");
sc_uint<2> r_0 = sc_uint<2>("0b00");
sc_uint<2> r_1 = sc_uint<2>("0b00");
sc_signal<sc_uint<1>> r_next;
sc_signal<sc_uint<2>> r_next_0;
sc_signal<sc_uint<2>> r_next_1;
sc_uint<8> rom[4] = {sc_uint<8>("0x00"),
sc_uint<8>("0x01"),
sc_uint<8>("0x02"),
sc_uint<8>("0x03"),
|
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
E_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
#define N_TX 3
#define N_RX 2
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket[N_RX];
while(true)
{
// Positive edge Clock
wait(clk.posedge_event());
txPacket[0] = (uint8_t)Cin.read(); // Cin
txPacket[1] = (uint8_t)(Yin.read())<<4 | (uint8_t)(Xin.read()); // Yin | Xin
txPacket[2] = (uint8_t)Rdy.read();
// Send to Emulator
for (int i=0; i<N_TX; i++)
{
x = txPacket[i];
while(write(fd, &x, 1)<=0) usleep(1);
}
// Receive from Emulator
for (int i=0; i<N_RX; i++)
{
while(read(fd, &y, 1)<=0) usleep(1);
rxPacket[i] = y;
}
Yout.write((sc_uint<4>)(rxPacket[0]>>4));
Xout.write((sc_uint<4>)(rxPacket[0] & 0x0F));
Vld.write(rxPacket[1]? true:false);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
SC_CTOR(E_fir_pe):
clk("clk"),
Cin("Cin"), Xin("Xin"), Xout("Xout"),
Yin("Yin"), Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
return;
}
// Set up serial port
options.c_cflag = B115200 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
}
~E_fir_pe(void)
{
}
|
Consumer |
sc_in<int> data;
int readNumber;
SC_CTOR(Consumer){
SC_METHOD(consume);
sensitive << data;
}
void consume()
{
readNumber = data.read();
//readNumber = data; //geht bei SC_SIGNAL auch
cout << "[" << sc_time_stamp() << " / " << sc_delta_count() << "](" << name() << "): read " << readNumber << endl;
}
|
gpio_matrix |
sc_inout<gn_mixed> d0_a11 {"d0_a11" |
HelloServertest |
/* Signals */
sc_signal<bool> led {"led" |
pcntmod |
sc_signal<uint32_t> conf0[8];
sc_signal<uint32_t> conf1[8];
sc_signal<uint32_t> conf2[8];
sc_signal<uint16_t> cnt_unit[8];
sc_signal<uint32_t> int_raw[8];
sc_signal<uint32_t> int_st {"int_st" |
SmallScreentest |
/* Signals */
sc_signal<bool> led {"led" |
System |
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
// LAB EXERCISE: Add a second parameter to select TLM I/O
// OLD
cynw_p2p < input_t, CYN::TLM > chan1; // For data going into the design
cynw_p2p < output_t, CYN::TLM > chan2; // For data coming out of the design
// NEW
//cynw_p2p < input_t, ioConfig > chan1; // For data going into the design
//cynw_p2p < output_t, ioConfig > chan2; // For data coming out of the design
// The testbench and DUT modules.
dut_wrapper *m_dut; // use the generated wrapper for all hls_modules
tb *m_tb;
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, chan1( "chan1" )
, chan2( "chan2" )
{
m_dut = new dut_wrapper( "dut_wrapper" );
// Connect the design module
m_dut->clk( clk_sig );
m_dut->rst( rst_sig );
m_dut->din( chan1 );
m_dut->dout( chan2 );
// Connect the testbench
m_tb = new tb( "tb" );
m_tb->clk( clk_sig );
m_tb->rst_out( rst_sig );
m_tb->dout( chan1 );
m_tb->din( chan2 );
}
~System()
{
delete m_tb;
delete m_dut;
}
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
System |
sc_clock clk_sig;
sc_signal<bool> rst_sig;
sc_signal<bool> finish;
sc_int<32> A[10];
sc_int<32> B[10];
sc_int<32> D[10];
dut_wrapper *m_dut;
tb *m_tb;
SC_CTOR(System)
: clk_sig("clk_sig", CLOCK_PERIOD, SC_NS)
, rst_sig("rst_sig")
, finish("finish")
{
m_dut = new dut_wrapper("dut_wrapper", A, B, D);
m_dut->clk(clk_sig);
m_dut->rst(rst_sig);
m_dut->finish(finish);
m_tb = new tb("tb", A, B, D);
m_tb->clk(clk_sig);
m_tb->rst(rst_sig);
m_tb->finish(finish);
}
~System()
{
delete m_tb;
delete m_dut;
}
|
s3 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s3_box();
SC_CTOR(s3)
{
SC_METHOD(s3_box);
sensitive << stage1_input;
}
|
s4 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s4_box();
SC_CTOR(s4)
{
SC_METHOD(s4_box);
sensitive << stage1_input;
}
|
des |
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<bool > load_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<64> > data_i;
sc_in<sc_uint<64> > key_i;
sc_out<sc_uint<64> > data_o;
sc_out<bool > ready_o;
//Registers for iteration counters
sc_signal<sc_uint<4> > stage1_iter, next_stage1_iter;
sc_signal<bool > next_ready_o;
sc_signal<sc_uint<64> > next_data_o;
sc_signal<bool > data_ready, next_data_ready;
//Conections to desround stage1
sc_signal<sc_uint<32> > stage1_L_i;
sc_signal<sc_uint<32> > stage1_R_i;
sc_signal<sc_uint<56> > stage1_round_key_i;
sc_signal<sc_uint<4> > stage1_iteration_i;
sc_signal<sc_uint<32> > stage1_R_o;
sc_signal<sc_uint<32> > stage1_L_o;
sc_signal<sc_uint<56> > stage1_round_key_o;
sc_signal<sc_uint<6> > s1_stag1_i, s2_stag1_i, s3_stag1_i, s4_stag1_i, s5_stag1_i, s6_stag1_i, s7_stag1_i, s8_stag1_i;
sc_signal<sc_uint<4> > s1_stag1_o, s2_stag1_o, s3_stag1_o, s4_stag1_o, s5_stag1_o, s6_stag1_o, s7_stag1_o, s8_stag1_o;
void des_proc();
void reg_signal();
desround *rd1;
s1 *sbox1;
s2 *sbox2;
s3 *sbox3;
s4 *sbox4;
s5 *sbox5;
s6 *sbox6;
s7 *sbox7;
s8 *sbox8;
SC_CTOR(des)
{
SC_METHOD(reg_signal);
sensitive << clk.pos();
sensitive << reset.neg();
SC_METHOD(des_proc);
sensitive << data_i << key_i << load_i << stage1_iter << data_ready;
sensitive << stage1_L_o << stage1_R_o << stage1_round_key_o;
rd1 = new desround("round1");
sbox1 = new s1("s1");
sbox2 = new s2("s2");
sbox3 = new s3("s3");
sbox4 = new s4("s4");
sbox5 = new s5("s5");
sbox6 = new s6("s6");
sbox7 = new s7("s7");
sbox8 = new s8("s8");
//For each stage in the pipe one instance
//First stage always present
rd1->clk(clk);
rd1->reset(reset);
rd1->iteration_i(stage1_iteration_i);
rd1->decrypt_i(decrypt_i);
rd1->R_i(stage1_R_i);
rd1->L_i(stage1_L_i);
rd1->Key_i(stage1_round_key_i);
rd1->R_o(stage1_R_o);
rd1->L_o(stage1_L_o);
rd1->Key_o(stage1_round_key_o);
rd1->s1_o(s1_stag1_i);
rd1->s2_o(s2_stag1_i);
rd1->s3_o(s3_stag1_i);
rd1->s4_o(s4_stag1_i);
rd1->s5_o(s5_stag1_i);
rd1->s6_o(s6_stag1_i);
rd1->s7_o(s7_stag1_i);
rd1->s8_o(s8_stag1_i);
rd1->s1_i(s1_stag1_o);
rd1->s2_i(s2_stag1_o);
rd1->s3_i(s3_stag1_o);
rd1->s4_i(s4_stag1_o);
rd1->s5_i(s5_stag1_o);
rd1->s6_i(s6_stag1_o);
rd1->s7_i(s7_stag1_o);
rd1->s8_i(s8_stag1_o);
sbox1->stage1_input(s1_stag1_i);
sbox1->stage1_output(s1_stag1_o);
sbox2->stage1_input(s2_stag1_i);
sbox2->stage1_output(s2_stag1_o);
sbox3->stage1_input(s3_stag1_i);
sbox3->stage1_output(s3_stag1_o);
sbox4->stage1_input(s4_stag1_i);
sbox4->stage1_output(s4_stag1_o);
sbox5->stage1_input(s5_stag1_i);
sbox5->stage1_output(s5_stag1_o);
sbox6->stage1_input(s6_stag1_i);
sbox6->stage1_output(s6_stag1_o);
sbox7->stage1_input(s7_stag1_i);
sbox7->stage1_output(s7_stag1_o);
sbox8->stage1_input(s8_stag1_i);
sbox8->stage1_output(s8_stag1_o);
}
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
reg |
// Reading Port :
sc_in<sc_uint<6>> RADR1_SD;
sc_in<sc_uint<6>> RADR2_SD;
sc_out<sc_uint<32>> RDATA1_SR;
sc_out<sc_uint<32>> RDATA2_SR;
// Writing Port :
sc_in<sc_uint<6>> WADR_SW;
sc_in<bool> WENABLE_SW;
sc_in<sc_uint<32>> WDATA_SW;
sc_in<sc_uint<32>> WRITE_PC_SD;
sc_in<bool> WRITE_PC_ENABLE_SD;
// PC Gestion :
sc_out<sc_uint<32>> READ_PC_SR;
// Global Interface :
sc_in_clk CLK;
sc_in<bool> RESET;
// Registres :
sc_signal<sc_uint<32>> REG_RR[32];
sc_signal<sc_uint<32>> PC_RR;
void read();
void write();
void trace(sc_trace_file * tf);
SC_CTOR(reg) {
SC_METHOD(read);
sensitive << RADR1_SD << RADR2_SD << RESET << PC_RR;
for (int i = 0; i < 32; i++)
sensitive << REG_RR[i];
SC_CTHREAD(write, reg::CLK.pos());
reset_signal_is(RESET, false);
}
|
wb_arbiter |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<sc_uint<32>> ADR_I;
//interface master0
sc_in<bool> CYC_0_I;
sc_out<bool> GRANT_0_O;
//interface master1
sc_in<bool> CYC_1_I;
sc_out<bool> GRANT_1_O;
//interface slave0
sc_out<bool> CYC_O;
sc_out<bool> SEL_0_O;
//signals
sc_signal<sc_uint<1>> master_priority;
// slave memory const registers
sc_signal<sc_uint<32>> slave_deb_adr[nb_slaves];
sc_signal<sc_uint<32>> slave_end_adr[nb_slaves];
void master_selector();
void slave_selector();
void init_memory();
void trace(sc_trace_file*);
SC_CTOR(wb_arbiter)
{
SC_METHOD(master_selector);
sensitive << RESET_N << CYC_0_I << CYC_1_I;
SC_METHOD(slave_selector);
sensitive << ADR_I;
SC_METHOD(init_memory);
sensitive << RESET_N;
|
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
sc_fir8* u_sc_fir8;
#ifdef VERILATED_CO_SIM
sc_signal<uint32_t> V_Xin;
sc_signal<uint32_t> V_Xout;
sc_signal<uint32_t> V_Yin;
sc_signal<uint32_t> V_Yout;
Vfir8* u_Vfir8;
VerilatedVcdSc* tfp; // Verilator VCD
#endif
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb): clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
#ifdef VERILATED_CO_SIM
u_Vfir8 = new Vfir8("u_Vfir8");
u_Vfir8->clk(clk);
u_Vfir8->Xin(V_Xin);
u_Vfir8->Xout(V_Xout);
u_Vfir8->Yin(V_Yin);
u_Vfir8->Yout(V_Yout);
Verilated::traceEverOn(true);
tfp = new VerilatedVcdSc;
sc_start(SC_ZERO_TIME);
u_Vfir8->trace(tfp, 3); // Trace levels of hierarchy
tfp->open("Vfir8.vcd");
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
#endif
}
~sc_fir8_tb(void)
{
}
|
rocket_wrapper |
//== Ports
sc_in<bool> clock;
sc_in<bool> reset;
sc_out<sc_lv<44>> periph_aw_msg;
sc_out<bool> periph_aw_valid;
sc_in<bool> periph_aw_ready;
sc_out<sc_lv<37>> periph_w_msg;
sc_out<bool> periph_w_valid;
sc_in<bool> periph_w_ready;
sc_in<sc_lv<6>> periph_b_msg;
sc_in<bool> periph_b_valid;
sc_out<bool> periph_b_ready;
sc_out<sc_lv<44>> periph_ar_msg;
sc_out<bool> periph_ar_valid;
sc_in<bool> periph_ar_ready;
sc_in<sc_lv<39>> periph_r_msg;
sc_in<bool> periph_r_valid;
sc_out<bool> periph_r_ready;
//== Signals
sc_signal<sc_logic> my_sc_clock;
sc_signal<sc_logic> my_sc_reset;
sc_signal<sc_lv<44>> sc_periph_aw_msg;
sc_signal<sc_logic> sc_periph_aw_valid;
sc_signal<sc_logic> sc_periph_aw_ready;
sc_signal<sc_lv<37>> sc_periph_w_msg;
sc_signal<sc_logic> sc_periph_w_valid;
sc_signal<sc_logic> sc_periph_w_ready;
sc_signal<sc_lv<6>> sc_periph_b_msg;
sc_signal<sc_logic> sc_periph_b_valid;
sc_signal<sc_logic> sc_periph_b_ready;
sc_signal<sc_lv<44>> sc_periph_ar_msg;
sc_signal<sc_logic> sc_periph_ar_valid;
sc_signal<sc_logic> sc_periph_ar_ready;
sc_signal<sc_lv<39>> sc_periph_r_msg;
sc_signal<sc_logic> sc_periph_r_valid;
sc_signal<sc_logic> sc_periph_r_ready;
//sc_logic sc_periph_r_ready;
//== Instances
sc_module_name rocket_sc_module_name{"rocket" |
Blinktest |
/* Signals */
sc_signal<bool> led {"led" |
s5 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s5_box();
SC_CTOR(s5)
{
SC_METHOD(s5_box);
sensitive << stage1_input;
}
|
wb_river_mc |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> ACK_I; // when asserted indicates the normal termination of a bus cycle
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<32>> ADR_O;
sc_out<sc_uint<2>> SEL_O; // select which words on DAT_O are valid
sc_out<bool> WE_O;
sc_out<bool> STB_O; // Master is talking on the bus
//interface with ICACHE
sc_in<sc_uint<32>> A_IC;
sc_in<bool> DTA_VALID_IC;
sc_out<sc_uint<32>> DT_IC;
sc_out<bool> ACK_IC;
//interface with DCACHE
sc_in<bool> DTA_VALID_DC;
sc_in<bool> READ_DC;
sc_in<bool> WRITE_DC;
sc_in<sc_uint<2>> SIZE_SEL_DC;
sc_in<sc_uint<32>> DT_DC;
sc_in<sc_uint<32>> A_DC;
sc_out<sc_uint<32>> DT_RM;
sc_out<bool> ACK_DC;
sc_out<bool> STALL_SW;
//interface with BCU
sc_in<bool> GRANT_I;
sc_out<bool> CYC_O;
//signals
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> future_state;
void new_state();
void state_transition();
void mae_output();
void trace(sc_trace_file*);
SC_CTOR(wb_river_mc)
{
SC_METHOD(new_state);
sensitive << CLK.pos() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.pos() << DTA_VALID_DC << DTA_VALID_IC
<< GRANT_I << WRITE_DC << READ_DC << ACK_I;
SC_METHOD(mae_output);
sensitive << current_state << DAT_I << ACK_I;
}
|
sc_fir8_tb |
sc_in<bool> clk;
sc_in<sc_uint<4> > eXout;
sc_in<sc_uint<4> > eYout;
sc_in<bool> eVld;
sc_out<sc_uint<4> > eXin;
sc_out<sc_uint<4> > eYin;
sc_out<bool> eRdy;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Yin;
sc_signal<bool> Rdy;
sc_fir8* u_sc_fir8;
bool sc_Stopped;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
sc_trace_file* fp; // VCD file
SC_CTOR(sc_fir8_tb): clk("clk"), sc_Stopped(false)
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Rdy(Rdy);
u_sc_fir8->Xout(eXin);
u_sc_fir8->Yout(eYin);
u_sc_fir8->Vld(eRdy);
// VCD Trace
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, eXin, "eXin");
sc_trace(fp, eYin, "eYin");
sc_trace(fp, eRdy, "eRdy");
sc_trace(fp, eXout, "eXout");
sc_trace(fp, eYout, "eYout");
sc_trace(fp, eVld, "eVld");
}
~sc_fir8_tb(void)
{
}
|
sc_shifter_TB |
sc_clock clk;
sc_signal<bool> rst,
sc_signal<sc_bv<7> > rst, din, qout;
Vshifter* u_Vshifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vshifter = new Vshifter("u_Vshifter");
// Binding
u_Vshifter->clk(clk);
u_Vshifter->rst(rst);
u_Vshifter->din(din);
u_Vshifter->qout(qout);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_shifter_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, rst, "rst");
sc_trace(fp, din, "din");
sc_trace(fp, qout, "qout");
}
void test_generator()
{
int test_count =0;
din.write(0);
rst.write(0);
wait(clk.posedge_event());
wait(clk.posedge_event());
rst.write(1);
wait(clk.posedge_event());
while(true)
{
din.write(1);
wait(clk.posedge_event());
if (test_count>6)
{
sc_close_vcd_trace_file(fp);
sc_stop();
}
else
test_count++;
}
}
|
dcache |
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SC;
sc_out<bool> STALL_SC; // if stall donc miss else hit
// interface MP
sc_out<bool> DTA_VALID_SC;
sc_out<bool> READ_SC, WRITE_SC;
sc_out<sc_uint<2>> SIZE_SC;
sc_out<sc_uint<32>> DT_SC;
sc_out<sc_uint<32>> A_SC;
sc_in<sc_uint<32>> DT_SP;
sc_in<sc_uint<32>> A_SP;
sc_in<bool> SLAVE_ACK_SP; // slave answer (slave dt valid)
//signals
//parse address from CPU
sc_signal<sc_uint<21>> address_tag;
sc_signal<sc_uint<7>> address_index;
sc_signal<sc_uint<4>> address_offset;
//parse address from MP
sc_signal<sc_uint<21>> mp_address_tag;
sc_signal<sc_uint<7>> mp_address_index;
sc_signal<sc_uint<4>> mp_address_offset;
sc_signal<sc_uint<4>> mp_last_addr_offset;
sc_signal<bool> way0_hit;
sc_signal<bool> way1_hit;
sc_signal<bool> miss;
sc_signal<sc_uint<32>> selected_data;
sc_signal<bool> current_LRU; // false: 0, true: 1
// WAYS 128 lines
sc_signal<bool> LRU_bit_check[128]; // bit to compare least recently used
// WAY 0
sc_signal<sc_uint<32>> w0_word[128][4];
sc_signal<sc_uint<21>> w0_TAG[128];
sc_signal<bool> w0_LINE_VALIDATE[128];
//WAY 1
sc_signal<sc_uint<32>> w1_word[128][4];
sc_signal<sc_uint<21>> w1_TAG[128];
sc_signal<bool> w1_LINE_VALIDATE[128];
//buffer
sc_signal<bool> write_buff, read_buff;
sc_signal<bool> full, empty;
sc_signal<sc_uint<32>> adr_sc;
sc_signal<sc_uint<32>> dt_sc;
int burst_cpt;
sc_signal<sc_uint<32>> data_mask_sc;
//FMS signal debug
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> future_state;
void adresse_parcer();
void miss_detection();
void new_state();
void state_transition();
void mae_output();
void buffer_manager();
void trace(sc_trace_file*);
buffercache buffcache_inst;
SC_CTOR(dcache) :
buffcache_inst("buffercache")
{
SC_METHOD(adresse_parcer);
sensitive << DATA_ADR_SM << A_SP;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< LOAD_SM
<< STORE_SM
<< way0_hit
<< way1_hit
<< CLK.neg();
SC_METHOD(new_state);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(mae_output);
sensitive << CLK.neg() << RESET_N << mp_address_tag
<< mp_address_index << mp_address_offset;
reset_signal_is(RESET_N, false);
buffcache_inst.RESET_N(RESET_N);
buffcache_inst.CLK(CLK);
buffcache_inst.WRITE_OBUFF(write_buff);
buffcache_inst.READ_OBUFF(read_buff);
buffcache_inst.DATA_C(DATA_SM);
buffcache_inst.ADR_C(DATA_ADR_SM);
buffcache_inst.STORE_C(STORE_SM);
buffcache_inst.LOAD_C(LOAD_SM);
buffcache_inst.SIZE_C(MEM_SIZE_SM);
buffcache_inst.FULL(full);
buffcache_inst.EMPTY(empty);
buffcache_inst.DATA_MP(DT_SC);
buffcache_inst.ADR_MP(A_SC);
buffcache_inst.STORE_MP(WRITE_SC);
buffcache_inst.LOAD_MP(READ_SC);
buffcache_inst.SIZE_MP(SIZE_SC);
}
|
reg |
// Reading Port :
sc_in<sc_uint<6>> RADR1_SD;
sc_in<sc_uint<6>> RADR2_SD;
sc_out<sc_uint<32>> RDATA1_SR;
sc_out<sc_uint<32>> RDATA2_SR;
// Writing Port :
sc_in<sc_uint<6>> WADR_SW;
sc_in<bool> WENABLE_SW;
sc_in<sc_uint<32>> WDATA_SW;
sc_in<sc_uint<32>> WRITE_PC_SD;
sc_in<bool> WRITE_PC_ENABLE_SD;
// PC Gestion :
sc_out<sc_uint<32>> READ_PC_SR;
// Global Interface :
sc_in_clk CLK;
sc_in<bool> RESET;
// Registres :
sc_signal<sc_uint<32>> REG_RR[32];
sc_signal<sc_uint<32>> PC_RR;
void read();
void write();
void trace(sc_trace_file * tf);
SC_CTOR(reg) {
SC_METHOD(read);
sensitive << RADR1_SD << RADR2_SD << RESET << PC_RR;
for (int i = 0; i < 32; i++)
sensitive << REG_RR[i];
SC_CTHREAD(write, reg::CLK.pos());
reset_signal_is(RESET, false);
}
|
fir_top |
sc_in<bool> CLK;
sc_in<bool> RESET;
sc_in<bool> IN_VALID;
sc_in<int> SAMPLE;
sc_out<bool> OUTPUT_DATA_READY;
sc_out<int> RESULT;
sc_signal<unsigned> state_out;
fir_fsm *fir_fsm1;
fir_data *fir_data1;
SC_CTOR(fir_top) {
fir_fsm1 = new fir_fsm("FirFSM");
fir_fsm1->clock(CLK);
fir_fsm1->reset(RESET);
fir_fsm1->in_valid(IN_VALID);
fir_fsm1->state_out(state_out);
fir_data1 = new fir_data("FirData");
fir_data1 -> reset(RESET);
fir_data1 -> state_out(state_out);
fir_data1 -> sample(SAMPLE);
fir_data1 -> result(RESULT);
fir_data1 -> output_data_ready(OUTPUT_DATA_READY);
}
|
dut |
sc_in_clk clk;
sc_in< bool > rst;
cynw_p2p< input_data, ioConfig >::in in;
cynw_p2p< output_data, ioConfig >::out out;
stream_16X8::in<ioConfig> streamin;
stream_16X8::out<ioConfig> streamout;
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, out( "out" )
, streamin( "streamin" )
, streamout( "streamout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
in.clk_rst( clk, rst );
out.clk_rst( clk, rst );
streamin.clk_rst( clk, rst );
streamout.clk_rst( clk, rst );
}
sc_uint<8> x[8];
sc_uint<8> y[4];
sc_uint<8> data[16];
void thread1();
|
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
|
ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> write1;
sc_signal<bool> arrange1;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
ACC_DTYPE<32> g1 [256];
ACC_DTYPE<8> r1 [256];
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[4096];
ACC_DTYPE<32> lhsdata2a[4096];
ACC_DTYPE<32> lhsdata3a[4096];
ACC_DTYPE<32> lhsdata4a[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
// //new sums bram
// ACC_DTYPE<32> lhs_sum1[512];
// ACC_DTYPE<32> lhs_sum2[512];
// ACC_DTYPE<32> lhs_sum3[512];
// ACC_DTYPE<32> lhs_sum4[512];
//
// ACC_DTYPE<32> rhs_sum1[512];
// ACC_DTYPE<32> rhs_sum2[512];
// ACC_DTYPE<32> rhs_sum3[512];
// ACC_DTYPE<32> rhs_sum4[512];
//
// //crf & crx
// ACC_DTYPE<32> crf1[512];
// ACC_DTYPE<32> crf2[512];
// ACC_DTYPE<32> crf3[512];
// ACC_DTYPE<32> crf4[512];
// ACC_DTYPE<32> crx[512];
//new sums bram
ACC_DTYPE<32> lhs_sum1[1024];
ACC_DTYPE<32> lhs_sum2[1024];
ACC_DTYPE<32> lhs_sum3[1024];
ACC_DTYPE<32> lhs_sum4[1024];
ACC_DTYPE<32> rhs_sum1[1024];
ACC_DTYPE<32> rhs_sum2[1024];
ACC_DTYPE<32> rhs_sum3[1024];
ACC_DTYPE<32> rhs_sum4[1024];
//crf & crx
ACC_DTYPE<32> crf1[1024];
ACC_DTYPE<32> crf2[1024];
ACC_DTYPE<32> crf3[1024];
ACC_DTYPE<32> crf4[1024];
ACC_DTYPE<32> crx[1024];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<char> sIs1;
sc_fifo<char> sIs2;
sc_fifo<char> sIs3;
sc_fifo<char> sIs4;
sc_fifo<char> sIs5;
sc_fifo<char> sIs6;
sc_fifo<char> sIs7;
sc_fifo<char> sIs8;
sc_fifo<char> sIs9;
sc_fifo<char> sIs10;
sc_fifo<char> sIs11;
sc_fifo<char> sIs12;
sc_fifo<char> sIs13;
sc_fifo<char> sIs14;
sc_fifo<char> sIs15;
sc_fifo<char> sIs16;
sc_fifo<char> sWs1;
sc_fifo<char> sWs2;
sc_fifo<char> sWs3;
sc_fifo<char> sWs4;
sc_fifo<char> sWs5;
sc_fifo<char> sWs6;
sc_fifo<char> sWs7;
sc_fifo<char> sWs8;
sc_fifo<char> sWs9;
sc_fifo<char> sWs10;
sc_fifo<char> sWs11;
sc_fifo<char> sWs12;
sc_fifo<char> sWs13;
sc_fifo<char> sWs14;
sc_fifo<char> sWs15;
sc_fifo<char> sWs16;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void schedule_gemm_unit(int, int, int, int, int,int,int);
int SHR(int,int);
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512),sIs1(2048),sIs2(2048),sIs3(2048),sIs4(2048),sIs5(2048),sIs6(2048),sIs7(2048),sIs8(2048),
sIs9(2048),sIs10(2048),sIs11(2048),sIs12(2048),sIs13(2048),sIs14(2048),sIs15(2048),sIs16(2048),
WRQ2(512),sWs1(2048),sWs2(2048),sWs3(2048),sWs4(2048),sWs5(2048),sWs6(2048),sWs7(2048),sWs8(2048),
sWs9(2048),sWs10(2048),sWs11(2048),sWs12(2048),sWs13(2048),sWs14(2048),sWs15(2048),sWs16(2048),WRQ3(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS array_partition variable=g1 complete dim=0
#pragma HLS RESET variable=reset
}
|
TLM |
Initiator *initiator;
Memory *memory;
sc_core::sc_in<bool> IO_request;
SC_HAS_PROCESS(TLM);
TLM(sc_module_name tlm) // Construct and name socket
{
// Instantiate components
initiator = new Initiator("initiator");
initiator->IO_request(IO_request);
memory = new Memory ("memory");
// One initiator is bound directly to one target with no intervening bus
// Bind initiator socket to target socket
initiator->socket.bind(memory->socket);
}
|
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_CTOR( tb ){
SC_CTHREAD( source, clk.pos() );
SC_CTHREAD( sink, clk.pos() );
}
|
s6 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s6_box();
SC_CTOR(s6)
{
SC_METHOD(s6_box);
sensitive << stage1_input;
}
|
display |
// Port for input by channel
sc_port< sc_csp_channel_in_if< sc_uint<8> > > result_channel_port;
SC_CTOR(display)
{
SC_THREAD(output);
}
// Main method
void output();
|
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top" |
i2c_controller_tb |
sc_clock *clk;
sc_signal<bool> rst;
sc_signal<sc_uint<7>> addr;
sc_signal<sc_uint<8>> data_in;
sc_signal<bool> enable;
sc_signal<bool> rw;
sc_signal<sc_lv<8>> data_out;
sc_signal<bool> ready;
sc_signal<sc_logic, SC_MANY_WRITERS> i2c_sda;
sc_signal<sc_logic> i2c_scl;
i2c_controller *master;
i2c_slave_controller *slave;
SC_CTOR(i2c_controller_tb)
{
clk = new sc_clock("clk",2,SC_NS);
master = new i2c_controller("i2c_controller");
master->clk(*clk);
master->rst(rst);
master->addr(addr);
master->data_in(data_in);
master->enable(enable);
master->rw(rw);
master->data_out(data_out);
master->ready(ready);
master->i2c_sda(i2c_sda);
master->i2c_scl(i2c_scl);
slave = new i2c_slave_controller("i2c_slave_controller");
slave->sda(i2c_sda);
slave->scl(i2c_scl);
SC_THREAD(stimuli);
sensitive << *clk << rst;
}
~i2c_controller_tb()
{
delete master;
delete slave;
}
void stimuli();
|
fir |
sc_in<bool> clk;
sc_in<bool> rst;
sc_in<sc_int<16>> inp;
sc_out<sc_int<16>> out;
// Handshake signals
sc_in<bool> inp_vld;
sc_out<bool> inp_rdy;
sc_out<bool> out_vld;
sc_in<bool> out_rdy;
void fir_main();
SC_CTOR( fir ) {
SC_CTHREAD(fir_main, clk.pos());
reset_signal_is(rst, true);
}
|
CounterModule |
// Inputs
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> up_down_ctrl;
sc_in<bool> count_enable;
//Outputs
sc_out<sc_uint<N> > count_out;
sc_out<bool> overflow_intr;
sc_out<bool> underflow_intr;
// Variables
sc_uint<N> count;
// Main function of the module
void do_count();
SC_CTOR(CounterModule){
SC_METHOD(do_count);
sensitive << clk.pos();
}
|
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
#ifdef EMULATED
sc_signal<sc_uint<8> > E_Xout;
sc_signal<sc_uint<16> > E_Yout;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
#endif
}
~sc_fir8_tb(void)
{
}
|
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<8> > X[FILTER_TAP_NUM]; // Shift Register X
void fir8_thread(void)
{
uint8_t x;
uint8_t yL, yH;
uint16_t y;
while(true)
{
wait(clk.posedge_event());
x = (uint8_t)Xin.read();
while(write(fd, &x, 1)<=0) // Send Byte
usleep(100);
for (int i=0; i<FILTER_TAP_NUM; i++)
{
while(read(fd, &x, 1)<=0) // Receive Byte: Shift Register of X
usleep(100);
X[i].write(sc_uint<8>(x));
}
while(read(fd, &yL, 1)<=0) // Receive Byte:LSB of y
usleep(100);
while(read(fd, &yH, 1)<=0) // Receive Byte:MSB of y
usleep(100);
y = (uint16_t)(yH<<8) | (uint16_t)(yL);
Yout.write(y);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(fir8_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
//return -1;
}
// Set up serial port
options.c_cflag = B9600 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
char szTrace[8];
for (int i=0; i<FILTER_TAP_NUM; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
close(fd);
}
|
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_fir_pe* u_fir_pe[N_PE_ARRAY];
sc_signal<sc_uint<8> > X[N_PE_ARRAY-1]; // X-input
sc_signal<sc_uint<16> > Y[N_PE_ARRAY-1]; // Accumulated
sc_signal<sc_uint<8> > C[N_PE_ARRAY]; // Filter-Tabs Coeff
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
// Instaltiate PE array -----------------------------
char szPeName[16];
for (int i=0; i<N_PE_ARRAY; i++)
{
sprintf(szPeName, "u_PE_%d", i);
u_fir_pe[i] = new sc_fir_pe(szPeName);
C[i].write(sc_uint<8>(filter_taps[i]));
u_fir_pe[i]->Cin(C[i]);
u_fir_pe[i]->clk(clk);
}
// Configure Array -----------------------------------
// 0-th PE
u_fir_pe[0]->Xin(Xin);
u_fir_pe[0]->Xout(X[0]);
u_fir_pe[0]->Yin(Yin);
u_fir_pe[0]->Yout(Y[0]);
// Systolic Array
for (int i=1; i<N_PE_ARRAY-1; i++)
{
u_fir_pe[i]->Xin(X[i-1]);
u_fir_pe[i]->Xout(X[i]);
u_fir_pe[i]->Yin(Y[i-1]);
u_fir_pe[i]->Yout(Y[i]);
}
// Last PE
u_fir_pe[N_PE_ARRAY-1]->Xin(X[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Xout(Xout);
u_fir_pe[N_PE_ARRAY-1]->Yin(Y[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Yout(Yout);
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
char szTrace[8];
for (int i=0; i<N_PE_ARRAY-1; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
sprintf(szTrace, "Y_%d", i);
sc_trace(fp, Y[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
}
|
sc_DUT_TB |
sc_clock CLK;
sc_signal<bool> nCLR;
sc_signal<bool> nLOAD;
sc_signal<bool> ENP;
sc_signal<bool> ENT;
sc_signal<bool> RCO;
// Verilator treats all Verilog's vector as <uint32_t>
sc_signal<uint32_t> Digit;
sc_signal<uint32_t> Din;
sc_signal<uint32_t> Dout;
// Exact DUT ports' vector width
sc_signal<sc_uint<2> > Digit_n2;
sc_signal<sc_uint<4> > Din_n4;
sc_signal<sc_uint<16> > Dout_n16;
// Verilated DUT or Foreign Verilog
VDUT* u_VDUT;
#ifdef CO_EMULATION
// Emulator DUT
DUT* u_DUT;
sc_signal<sc_uint<16> > Dout_emu;
sc_signal<bool> RCO_emu;
#endif
// Convert Verilator's ports to DUT's ports
void conv_method()
{
Digit_n2.write((sc_uint<2>)Digit);
Din_n4.write((sc_uint<4>)Din);
Dout_n16.write((sc_uint<16>)Dout);
}
void test_generator();
void monitor();
sc_trace_file* fp; // VCD file
SC_CTOR(sc_DUT_TB) : // Constructor
CLK("CLK", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
SC_THREAD(test_generator);
sensitive << CLK;
SC_THREAD(monitor);
sensitive << CLK;
SC_METHOD(conv_method);
sensitive << Din << Dout << Digit;
// DUT Instantiation
u_VDUT = new VDUT("u_VDUT");
// Binding
u_VDUT->CLK(CLK);
u_VDUT->nCLR(nCLR);
u_VDUT->nLOAD(nLOAD);
u_VDUT->Digit(Digit);
u_VDUT->ENP(ENP);
u_VDUT->ENT(ENT);
u_VDUT->Din(Din);
u_VDUT->Dout(Dout);
u_VDUT->RCO(RCO);
#ifdef CO_EMULATION
u_DUT = new DUT("u_DUT");
// Binding
u_DUT->CLK(CLK);
u_DUT->nCLR(nCLR);
u_DUT->nLOAD(nLOAD);
u_DUT->Digit(Digit_n2);
u_DUT->Din(Din_n4);
u_DUT->Dout(Dout_emu);
u_DUT->RCO(RCO_emu);
#endif
// VCD Trace
fp = sc_create_vcd_trace_file("sc_DUT_TB");
fp->set_time_unit(100, SC_PS);
sc_trace(fp, CLK, "CLK");
sc_trace(fp, nCLR, "nCLR");
sc_trace(fp, nLOAD, "nLOAD");
sc_trace(fp, Digit_n2, "Digit");
sc_trace(fp, ENP, "ENP");
sc_trace(fp, ENT, "ENT");
sc_trace(fp, Din_n4, "Din");
sc_trace(fp, Dout_n16, "Dout");
sc_trace(fp, RCO, "RCO");
#ifdef CO_EMULATION
sc_trace(fp, Dout_emu, "Dout_emu");
sc_trace(fp, RCO_emu, "RCO_emu");
#endif
}
// Destructor
~sc_DUT_TB()
{}
|
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > E_Yout;
sc_signal<bool> E_Vld;
#endif
sc_fir8* u_sc_fir8;
VerilatedVcdSc* tfp; // Verilator VCD
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Vld("Vld"),
Rdy("Rdy"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
u_sc_fir8->Rdy(Rdy);
u_sc_fir8->Vld(Vld);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
u_sc_fir8->E_Vld(E_Vld);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
#endif
// Trace Verilated Verilog internals
Verilated::traceEverOn(true);
tfp = new VerilatedVcdSc;
sc_start(SC_ZERO_TIME);
u_sc_fir8->
u_fir_pe[N_PE_ARRAY-1]->
u_Vfir_pe->trace(tfp, 99); // Trace levels of hierarchy
tfp->open("Vfir_pe.vcd");
}
~sc_fir8_tb(void)
{
}
|
simple_bus_test |
// channels
sc_clock C1;
// module instances
simple_bus_master_blocking *master_b;
simple_bus_master_non_blocking *master_nb;
simple_bus_master_direct *master_d;
simple_bus_slow_mem *mem_slow;
simple_bus *bus;
simple_bus_fast_mem *mem_fast;
simple_bus_arbiter *arbiter;
// constructor
SC_CTOR(simple_bus_test)
: C1("C1")
{
// create instances
master_b = new simple_bus_master_blocking("master_b", 4, 0x4c, false, 300);
master_nb = new simple_bus_master_non_blocking("master_nb", 3, 0x38, false, 20);
master_d = new simple_bus_master_direct("master_d", 0x78, 100);
mem_fast = new simple_bus_fast_mem("mem_fast", 0x00, 0x7f);
mem_slow = new simple_bus_slow_mem("mem_slow", 0x80, 0xff, 1);
// bus = new simple_bus("bus",true); // verbose output
bus = new simple_bus("bus");
// arbiter = new simple_bus_arbiter("arbiter",true); // verbose output
arbiter = new simple_bus_arbiter("arbiter");
// connect instances
master_d->clock(C1);
bus->clock(C1);
master_b->clock(C1);
master_nb->clock(C1);
mem_slow->clock(C1);
master_d->bus_port(*bus);
master_b->bus_port(*bus);
master_nb->bus_port(*bus);
bus->arbiter_port(*arbiter);
bus->slave_port(*mem_slow);
bus->slave_port(*mem_fast);
}
// destructor
~simple_bus_test()
{
if (master_b) {delete master_b; master_b = 0;}
if (master_nb) {delete master_nb; master_nb = 0;}
if (master_d) {delete master_d; master_d = 0;}
if (mem_slow) {delete mem_slow; mem_slow = 0;}
if (bus) {delete bus; bus = 0;}
if (mem_fast) {delete mem_fast; mem_fast = 0;}
if (arbiter) {delete arbiter; arbiter = 0;}
}
|
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
|
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top" |
quant |
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
|
quant |
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
|
quant |
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
|
transmitter)
//class transmitter : public sc_module
{
/// Input port for datas from the switch
sc_in<Packet> datain;
/// reset port
sc_in<bool> rst_n;
/// clk port
sc_in<bool> clk;
/// full port. If it's set it indicates that the fifo of the transmitter is to small to contain all datas
sc_out<sc_bit> full;
/// strobe output port.It changes with datac
sc_out<sc_bit> strobe;
/// data to the receiver sub-block of the wrapper
sc_out<Packet> datac;
/// main process of the transmitter module
void evaluate();
//Packet FIFO[FIFO_TX_DIM];
/// fifo used to manage case of fast transmitter
Packet* FIFO;
int i,last_pos,c;
ofstream tx_file;
//SC_CTOR(transmitter)
/// constructor of the transmitter
SC_HAS_PROCESS(transmitter);
transmitter(sc_module_name name_ , int N_R , int N_T, int fifo_tx_dim) : sc_module(name_), m_N_R(N_R), m_N_T(N_T),m_fifo_tx_dim(fifo_tx_dim |
SC_METHOD(evaluate);
sensitive<<clk.pos()<<rst_n.neg();
FIFO= new Packet[m_fifo_tx_dim];
for (i=0;i<m_fifo_tx_dim;i++)
FIFO[i]=empty_NL_PDU;
last_pos=0;
if(m_N_R > m_N_T)
c=m_N_R;
tx_file.open ("tx_file.txt",ios::trunc);
tx_file << "SIMULATION STARTS NOW: "<<endl<<endl;
tx_file.close();
}
private:
int m_N_R,m_N_T,m_fifo_tx_dim;
|
fila |
sc_in<bool > clock;
sc_in<bool > reset_n;
sc_in<regflit > data_in;
sc_in<bool > rx;
sc_out<bool > credit_o;
//sc_out<bool > ack_rx;
sc_out<bool > h;
sc_in<bool > ack_h;
sc_out<bool > data_av;
sc_out<regflit > data;
sc_in<bool > data_ack;
sc_out<bool > sender;
enum fila_out{S_INIT, S_PAYLOAD, S_SENDHEADER, S_HEADER, S_END, S_END2 |