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ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
// int rows=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_2_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_3_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_4_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> write2;
sc_signal<bool,SC_MANY_WRITERS> write3;
sc_signal<bool,SC_MANY_WRITERS> write4;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
sc_signal<bool,SC_MANY_WRITERS> arrange2;
sc_signal<bool,SC_MANY_WRITERS> arrange3;
sc_signal<bool,SC_MANY_WRITERS> arrange4;
sc_signal<bool,SC_MANY_WRITERS> write1_1;
sc_signal<bool,SC_MANY_WRITERS> write1_2;
sc_signal<bool,SC_MANY_WRITERS> write1_3;
sc_signal<bool,SC_MANY_WRITERS> write1_4;
sc_signal<bool,SC_MANY_WRITERS> write2_1;
sc_signal<bool,SC_MANY_WRITERS> write2_2;
sc_signal<bool,SC_MANY_WRITERS> write2_3;
sc_signal<bool,SC_MANY_WRITERS> write2_4;
sc_signal<bool,SC_MANY_WRITERS> write3_1;
sc_signal<bool,SC_MANY_WRITERS> write3_2;
sc_signal<bool,SC_MANY_WRITERS> write3_3;
sc_signal<bool,SC_MANY_WRITERS> write3_4;
sc_signal<bool,SC_MANY_WRITERS> write4_1;
sc_signal<bool,SC_MANY_WRITERS> write4_2;
sc_signal<bool,SC_MANY_WRITERS> write4_3;
sc_signal<bool,SC_MANY_WRITERS> write4_4;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> gemm_unit_2_ready;
sc_signal<bool> gemm_unit_3_ready;
sc_signal<bool> gemm_unit_4_ready;
sc_signal<bool> write1;
sc_signal<bool> write2;
sc_signal<bool> write3;
sc_signal<bool> write4;
sc_signal<bool> arrange1;
sc_signal<bool> arrange2;
sc_signal<bool> arrange3;
sc_signal<bool> arrange4;
sc_signal<bool> write1_1;
sc_signal<bool> write1_2;
sc_signal<bool> write1_3;
sc_signal<bool> write1_4;
sc_signal<bool> write2_1;
sc_signal<bool> write2_2;
sc_signal<bool> write2_3;
sc_signal<bool> write2_4;
sc_signal<bool> write3_1;
sc_signal<bool> write3_2;
sc_signal<bool> write3_3;
sc_signal<bool> write3_4;
sc_signal<bool> write4_1;
sc_signal<bool> write4_2;
sc_signal<bool> write4_3;
sc_signal<bool> write4_4;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<int> gemm_unit_2_l_pointer;
sc_signal<int> gemm_unit_3_l_pointer;
sc_signal<int> gemm_unit_4_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
sc_signal<bool> gemm_unit_2_iwuse;
sc_signal<bool> gemm_unit_3_iwuse;
sc_signal<bool> gemm_unit_4_iwuse;
ADATA g1;
ADATA g2;
ADATA g3;
ADATA g4;
ADATA r1;
ADATA r2;
ADATA r3;
ADATA r4;
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[2048];
ACC_DTYPE<32> lhsdata2a[2048];
ACC_DTYPE<32> lhsdata3a[2048];
ACC_DTYPE<32> lhsdata4a[2048];
//GEMM 2 Inputs
ACC_DTYPE<32> lhsdata1b[2048];
ACC_DTYPE<32> lhsdata2b[2048];
ACC_DTYPE<32> lhsdata3b[2048];
ACC_DTYPE<32> lhsdata4b[2048];
//GEMM 3 Inputs
ACC_DTYPE<32> lhsdata1c[2048];
ACC_DTYPE<32> lhsdata2c[2048];
ACC_DTYPE<32> lhsdata3c[2048];
ACC_DTYPE<32> lhsdata4c[2048];
//GEMM 4 Inputs
ACC_DTYPE<32> lhsdata1d[2048];
ACC_DTYPE<32> lhsdata2d[2048];
ACC_DTYPE<32> lhsdata3d[2048];
ACC_DTYPE<32> lhsdata4d[2048];
// //GEMM 1 Inputs
// ACC_DTYPE<32> lhsdata1a[4096];
// ACC_DTYPE<32> lhsdata2a[4096];
// ACC_DTYPE<32> lhsdata3a[4096];
// ACC_DTYPE<32> lhsdata4a[4096];
//
// //GEMM 2 Inputs
// ACC_DTYPE<32> lhsdata1b[4096];
// ACC_DTYPE<32> lhsdata2b[4096];
// ACC_DTYPE<32> lhsdata3b[4096];
// ACC_DTYPE<32> lhsdata4b[4096];
//
// //GEMM 3 Inputs
// ACC_DTYPE<32> lhsdata1c[4096];
// ACC_DTYPE<32> lhsdata2c[4096];
// ACC_DTYPE<32> lhsdata3c[4096];
// ACC_DTYPE<32> lhsdata4c[4096];
//
// //GEMM 4 Inputs
// ACC_DTYPE<32> lhsdata1d[4096];
// ACC_DTYPE<32> lhsdata2d[4096];
// ACC_DTYPE<32> lhsdata3d[4096];
// ACC_DTYPE<32> lhsdata4d[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
//First Set (A)
ACC_DTYPE<32> rhs1a_1[2048];
ACC_DTYPE<32> rhs1b_1[2048];
ACC_DTYPE<32> rhs1c_1[2048];
ACC_DTYPE<32> rhs1d_1[2048];
ACC_DTYPE<32> rhs2a_1[2048];
ACC_DTYPE<32> rhs2b_1[2048];
ACC_DTYPE<32> rhs2c_1[2048];
ACC_DTYPE<32> rhs2d_1[2048];
ACC_DTYPE<32> rhs3a_1[2048];
ACC_DTYPE<32> rhs3b_1[2048];
ACC_DTYPE<32> rhs3c_1[2048];
ACC_DTYPE<32> rhs3d_1[2048];
ACC_DTYPE<32> rhs4a_1[2048];
ACC_DTYPE<32> rhs4b_1[2048];
ACC_DTYPE<32> rhs4c_1[2048];
ACC_DTYPE<32> rhs4d_1[2048];
// //First Set (A)
// ACC_DTYPE<32> rhs1a_1[1024];
// ACC_DTYPE<32> rhs1b_1[1024];
// ACC_DTYPE<32> rhs1c_1[1024];
// ACC_DTYPE<32> rhs1d_1[1024];
//
// ACC_DTYPE<32> rhs2a_1[1024];
// ACC_DTYPE<32> rhs2b_1[1024];
// ACC_DTYPE<32> rhs2c_1[1024];
// ACC_DTYPE<32> rhs2d_1[1024];
//
// ACC_DTYPE<32> rhs3a_1[1024];
// ACC_DTYPE<32> rhs3b_1[1024];
// ACC_DTYPE<32> rhs3c_1[1024];
// ACC_DTYPE<32> rhs3d_1[1024];
//
// ACC_DTYPE<32> rhs4a_1[1024];
// ACC_DTYPE<32> rhs4b_1[1024];
// ACC_DTYPE<32> rhs4c_1[1024];
// ACC_DTYPE<32> rhs4d_1[1024];
//new sums bram
ACC_DTYPE<32> lhs_sum1[512];
ACC_DTYPE<32> lhs_sum2[512];
ACC_DTYPE<32> lhs_sum3[512];
ACC_DTYPE<32> lhs_sum4[512];
ACC_DTYPE<32> rhs_sum1[512];
ACC_DTYPE<32> rhs_sum2[512];
ACC_DTYPE<32> rhs_sum3[512];
ACC_DTYPE<32> rhs_sum4[512];
//crf & crx
ACC_DTYPE<32> crf1[512];
ACC_DTYPE<32> crf2[512];
ACC_DTYPE<32> crf3[512];
ACC_DTYPE<32> crf4[512];
ACC_DTYPE<32> crx[512];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<int> WRQ4;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Worker2();
void Worker3();
void Worker4();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void Post2();
void Post3();
void Post4();
void Arranger1();
void Arranger2();
void Arranger3();
void Arranger4();
void WSync1();
void WSync2();
void WSync3();
void WSync4();
void load_weights(int,int);
void schedule_gemm_unit(int, int, int, int);
int SHR(int,int);
void overwrite_weights_check();
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512), WRQ2(512), WRQ3(512), WRQ4(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS RESET variable=reset
}
|
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_HAS_PROCESS( tb );
tb( sc_module_name nm );
|
x1_multiplier |
// input :
sc_in<sc_bv<320>> IN_RX0;
sc_in<bool> SELECT_HIGHER_BITS_RX0;
sc_in<bool> SIGNED_RES_RX0;
sc_in<bool> X02X1_EMPTY_SX0;
sc_in<bool> X12X2_POP_SX2;
// output :
sc_out<sc_bv<128>> RES_RX1;
sc_out<bool> SELECT_HIGHER_BITS_RX1;
sc_out<bool> SIGNED_RES_RX1;
sc_out<bool> X12X2_EMPTY_SX1;
sc_out<bool> X02X1_POP_SX1;
// General interace :
sc_in_clk CLK;
sc_in<bool> RESET;
//data from input
sc_signal<sc_bv<64>> M[5];
//Res from stage 6
sc_signal<sc_bv<64>> product_s6[4];
//Res from stage 7
sc_signal<sc_bv<64>> product_s7[2];
//Res from stage 8
sc_signal<sc_bv<64>> product_s8[2];
// fifo x12x2
sc_signal<sc_bv<x12x2_size>> x12x2_din_sx1;
sc_signal<sc_bv<x12x2_size>> x12x2_dout_sx1;
sc_signal<bool> x12x2_full_sx1;
sc_signal<bool> x12x2_push_sx1;
fifo<x12x2_size> fifo_inst;
void parse_data();
//stage 6 (2 CSA)
void CSA1();
void CSA2();
//stage 7 (1 CSA remind product_s6 M3)
void CSA3();
//stage 8 (1 CSA)
void CSA4();
void manage_fifo();
void fifo_concat();
void fifo_unconcat();
void trace(sc_trace_file* tf);
SC_CTOR(x1_multiplier) :
fifo_inst("x12x2")
{
fifo_inst.DIN_S(x12x2_din_sx1);
fifo_inst.DOUT_R(x12x2_dout_sx1);
fifo_inst.EMPTY_S(X12X2_EMPTY_SX1);
fifo_inst.FULL_S(x12x2_full_sx1);
fifo_inst.PUSH_S(x12x2_push_sx1);
fifo_inst.POP_S(X12X2_POP_SX2);
fifo_inst.CLK(CLK);
fifo_inst.RESET_N(RESET);
SC_METHOD(parse_data);
sensitive << IN_RX0;
SC_METHOD(CSA1);
sensitive << M[0] << M[1] << M[2];
SC_METHOD(CSA3);
sensitive << product_s6[0] << product_s6[1] << M[3];
SC_METHOD(CSA4);
sensitive << product_s7[0] << product_s7[1] << M[4];
SC_METHOD(manage_fifo);
sensitive << x12x2_full_sx1 << X02X1_EMPTY_SX0;
SC_METHOD(fifo_concat);
sensitive << SELECT_HIGHER_BITS_RX0 << product_s8[0] << product_s8[1] << SIGNED_RES_RX0;
SC_METHOD(fifo_unconcat);
sensitive << x12x2_dout_sx1;
}
|
IP_RIVER |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<bool> ACK;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> GRANT;
sc_in<sc_uint<32>> ADR_I;
sc_out<sc_uint<32>> ADR;
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<2>> SEL;
sc_out<bool> STB;
sc_out<bool> WE;
sc_out<bool> CYC;
// DCache-Core
sc_signal<sc_uint<32>> DATA_ADR_SM;
sc_signal<sc_uint<32>> DATA_SM;
sc_signal<bool> VALID_ADR_SM;
sc_signal<bool> STORE_SM;
sc_signal<bool> LOAD_SM;
sc_signal<sc_uint<2>> MEM_SIZE_SM;
sc_signal<sc_uint<32>> DATA_SDC;
sc_signal<bool> STALL_SDC;
// ICache-Core
sc_signal<sc_uint<32>> ADR_SI;
sc_signal<bool> ADR_VALID_SI;
sc_signal<sc_bv<32>> INST_SIC;
sc_signal<bool> STALL_SIC;
//DCache-Wrapper
sc_signal<bool> READ_SDC;
sc_signal<bool> WRITE_SDC;
sc_signal<bool> DTA_VALID_SDC;
sc_signal<sc_uint<32>> DCACHE_DT;
sc_signal<sc_uint<32>> A_SDC;
sc_signal<sc_uint<2>> SIZE_SDC;
sc_signal<sc_uint<32>> WRAPPER_DT;
sc_signal<bool> DCACHE_ACK;
sc_signal<bool> STALL_SW;
//ICache-Wrapper
sc_signal<bool> ICACHE_ACK;
sc_signal<sc_uint<32>> ICACHE_DT;
sc_signal<sc_uint<32>> A_SIC;
sc_signal<bool> DTA_VALID_SIC;
//Debug CORE
sc_in<sc_uint<32>> PC_RESET;
sc_out<sc_uint<32>> PC_VALUE;
sc_in<sc_uint<32>> PROC_ID;
void trace(sc_trace_file*);
core core_inst;
icache icache_inst;
dcache dcache_inst;
wb_river_mc wrapper_inst;
SC_CTOR(IP_RIVER):
core_inst("core"),
icache_inst("icache"),
dcache_inst("dcache"),
wrapper_inst("wb_river_mc")
{
//CORE map
core_inst.CLK(CLK);
core_inst.RESET(RESET_N);
core_inst.DEBUG_PC_READ(PC_VALUE);
core_inst.PC_INIT(PC_RESET);
core_inst.PROC_ID(PROC_ID);
core_inst.MCACHE_ADR_SM(DATA_ADR_SM);
core_inst.MCACHE_DATA_SM(DATA_SM);
core_inst.MCACHE_ADR_VALID_SM(VALID_ADR_SM);
core_inst.MCACHE_STORE_SM(STORE_SM);
core_inst.MCACHE_LOAD_SM(LOAD_SM);
core_inst.MCACHE_RESULT_SM(DATA_SDC);
core_inst.MCACHE_STALL_SM(STALL_SDC);
core_inst.MEM_SIZE_SM(MEM_SIZE_SM);
core_inst.ADR_SI(ADR_SI);
core_inst.ADR_VALID_SI(ADR_VALID_SI);
core_inst.INST_SIC(INST_SIC);
core_inst.STALL_SIC(STALL_SIC);
//DCache map
dcache_inst.CLK(CLK);
dcache_inst.RESET_N(RESET_N);
dcache_inst.DATA_ADR_SM(DATA_ADR_SM);
dcache_inst.DATA_SM(DATA_SM);
dcache_inst.LOAD_SM(LOAD_SM);
dcache_inst.STORE_SM(STORE_SM);
dcache_inst.VALID_ADR_SM(VALID_ADR_SM);
dcache_inst.MEM_SIZE_SM(MEM_SIZE_SM);
dcache_inst.DATA_SDC(DATA_SDC);
dcache_inst.STALL_SDC(STALL_SDC);
dcache_inst.DTA_VALID_SDC(DTA_VALID_SDC);
dcache_inst.READ_SDC(READ_SDC);
dcache_inst.WRITE_SDC(WRITE_SDC);
dcache_inst.SIZE_SDC(SIZE_SDC);
dcache_inst.DT_SDC(DCACHE_DT);
dcache_inst.A_SDC(A_SDC);
dcache_inst.DT_SW(WRAPPER_DT);
dcache_inst.ACK_SW(DCACHE_ACK);
dcache_inst.ADR_SW(ADR_I);
dcache_inst.GRANT(GRANT); // signal for snoopy control
dcache_inst.STALL_SW(STALL_SW);
//ICache map
icache_inst.CLK(CLK);
icache_inst.RESET_N(RESET_N);
icache_inst.ADR_SI(ADR_SI);
icache_inst.ADR_VALID_SI(ADR_VALID_SI);
icache_inst.INST_SIC(INST_SIC);
icache_inst.STALL_SIC(STALL_SIC);
icache_inst.DT_SW(ICACHE_DT);
icache_inst.A_SIC(A_SIC);
icache_inst.DTA_VALID_SIC(DTA_VALID_SIC);
icache_inst.ACK_SW(ICACHE_ACK);
icache_inst.STALL_SW(STALL_SW);
//Wrapper map
wrapper_inst.CLK(CLK);
wrapper_inst.RESET_N(RESET_N);
wrapper_inst.DAT_I(DAT_I);
wrapper_inst.ACK_I(ACK);
wrapper_inst.DAT_O(DAT_O);
wrapper_inst.ADR_O(ADR);
wrapper_inst.SEL_O(SEL);
wrapper_inst.WE_O(WE);
wrapper_inst.STB_O(STB);
wrapper_inst.A_IC(A_SIC);
wrapper_inst.DTA_VALID_IC(DTA_VALID_SIC);
wrapper_inst.DT_IC(ICACHE_DT);
wrapper_inst.ACK_IC(ICACHE_ACK);
wrapper_inst.DTA_VALID_DC(DTA_VALID_SDC);
wrapper_inst.READ_DC(READ_SDC);
wrapper_inst.WRITE_DC(WRITE_SDC);
wrapper_inst.SIZE_SEL_DC(SIZE_SDC);
wrapper_inst.DT_DC(DCACHE_DT);
wrapper_inst.A_DC(A_SDC);
wrapper_inst.DT_RM(WRAPPER_DT);
wrapper_inst.ACK_DC(DCACHE_ACK);
wrapper_inst.GRANT_I(GRANT);
wrapper_inst.CYC_O(CYC);
wrapper_inst.STALL_SW(STALL_SW);
}
|
s8 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s8_box();
SC_CTOR(s8)
{
SC_METHOD(s8_box);
sensitive << stage1_input;
}
|
icache |
// interface global
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface RiVer
sc_in<sc_uint<32> > ADR_SI;
sc_in<bool> ADR_VALID_SI;
sc_out<sc_bv<32> > INST_SIC;
sc_out<bool> STALL_SIC;
//interface wrapper
sc_in<sc_uint<32>> DT_SW;
sc_out<sc_uint<32>> A_SIC;
sc_out<bool> DTA_VALID_SIC;
sc_in<bool> ACK_SW;
sc_in<bool> STALL_SW;
//signals
sc_signal<sc_bv<32>> data[256][4];
sc_signal<sc_uint<20>> tag[256];
sc_signal<bool> data_validate[256];
sc_signal<sc_uint<20>> address_tag;
sc_signal<sc_uint<8>> address_index;
sc_signal<sc_uint<4>> address_offset;
sc_signal<sc_uint<20>> current_address_tag;
sc_signal<sc_uint<8>> current_address_index;
sc_signal<bool> hit;
sc_signal<sc_uint<3>> fsm_state;
void trace(sc_trace_file*);
void parse_adr();
void miss_detection();
void transition();
SC_CTOR(icache)
{
SC_METHOD(parse_adr);
sensitive << ADR_SI;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< STALL_SIC;
for(int i=0; i < 256 ;i++){
sensitive << data[i][0]
<< data[i][1]
<< data[i][2]
<< data[i][3]
<< data_validate[i];
}
SC_THREAD(transition);
sensitive << CLK.neg();
reset_signal_is(RESET_N, false);
}
|
sc_dffrs_TB |
sc_clock clk;
sc_signal<bool> r, s, d, q;
Vdffrs* u_Vdffrs;
sc_trace_file* fp; // VCD file
SC_CTOR(sc_dffrs_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vdffrs = new Vdffrs("u_Vdffrs");
// Binding
u_Vdffrs->clk(clk);
u_Vdffrs->r(r);
u_Vdffrs->s(s);
u_Vdffrs->d(d);
u_Vdffrs->q(q);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_dffrs_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, r, "r");
sc_trace(fp, s, "s");
sc_trace(fp, d, "d");
sc_trace(fp, q, "q");
}
void test_generator()
{
int test_count =0;
r.write(1);
s.write(1);
d.write(0);
while(true)
{
wait(clk.posedge_event());
wait(clk.negedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.negedge_event());
r.write(0);
wait(clk.posedge_event());
r.write(1);
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
d = false;
wait(clk.negedge_event());
d = 1;
wait(clk.posedge_event());
d = 0;
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(1);
wait(clk.posedge_event());
r.write(0);
s.write(0);
//d.write(0);
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(0);
wait(clk.posedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.posedge_event());
// Ending stimulus
wait(clk.posedge_event());
wait(clk.posedge_event());
sc_close_vcd_trace_file(fp);
sc_stop();
}
}
|
scClk |
sc_out<bool> clk{"clk_o" |
sc_beh_shifter_TB |
sc_clock clk;
sc_signal<bool> rst;
sc_signal<uint32_t> din, qout;
Vbeh_shifter* u_Vbeh_shifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_beh_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vbeh_shifter = new Vbeh_shifter("u_Vbeh_shifter");
// Binding
u_Vbeh_shifter->clk(clk);
u_Vbeh_shifter->rst(rst);
u_Vbeh_shifter->din(din);
u_Vbeh_shifter->qout(qout);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_shifter_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, rst, "rst");
sc_trace(fp, din, "din");
sc_trace(fp, qout, "qout");
}
void test_generator()
{
int test_count =0;
din.write(0);
rst.write(0);
wait(clk.posedge_event());
wait(clk.posedge_event());
rst.write(1);
wait(clk.posedge_event());
while(true)
{
din.write(1);
wait(clk.posedge_event());
if (test_count>6)
{
sc_close_vcd_trace_file(fp);
sc_stop();
}
else
test_count++;
}
}
|
cnn |
// typedef
typedef hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n,
P_pool_size, P_PE_pipeline_II, P_pe_pre_fifo_deep>
top_cnn_t;
// interface
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(64)> ctrl_sink;
sc_fifo_out<hwcore::pipes::SC_DATA_T(P_output_width)> data_source;
#if __RTL_SIMULATION__
sc_status_module_create_interface_only(reg1);
ap_rtl::cnn rtl_wrapper_cnn;
SC_FIFO_IN_TRANS<P_input_width> data_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> data_buf_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> w_sink_trans;
SC_FIFO_IN_TRANS<64> ctrl_sink_trans;
SC_FIFO_OUT_TRANS<P_output_width> data_source_trans;
sc_signal<sc_logic> reset_s;
sc_signal<sc_lv<32> > status_add_s;
sc_signal<sc_lv<32> > status_val_s;
void signal_connection() {
sc_dt::sc_logic reset_tmp = (sc_dt::sc_logic)reset.read();
reset_s.write(reset_tmp);
status_add_s.write(status_add.read());
status_val.write(status_val_s.read().to_int());
}
SC_CTOR(cnn)
: rtl_wrapper_cnn("rtl_wrapper_cnn"), data_sink_trans("data_sink_trans"),
data_buf_sink_trans("data_buf_sink_trans"), data_source_trans("data_source_trans"),
w_sink_trans("w_sink_trans"), ctrl_sink_trans("ctrl_sink_trans") {
// SC_MODULE_LINK(rtl_wrapper_cnn);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_sink_trans, data_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_buf_sink_trans, data_buf_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, w_sink_trans, w_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, ctrl_sink_trans, ctrl_sink);
SC_FIFO_OUT_TRANS_CONNECT(rtl_wrapper_cnn, data_source_trans, data_source);
rtl_wrapper_cnn.clk(clk);
rtl_wrapper_cnn.reset(reset_s);
rtl_wrapper_cnn.status_add(status_add_s);
rtl_wrapper_cnn.status_val(status_val_s);
SC_METHOD(signal_connection);
sensitive << status_add << status_val_s << reset;
}
#else
sc_status_module_create(reg1);
sc_status_reg_create(r0_dma_ingress);
sc_status_reg_create(r1_dma_egress);
sc_status_reg_create(r2_data_W);
sc_status_reg_create(r3_data_P);
sc_status_reg_create(r4_input_BW_N);
sc_status_reg_create(r5_output_BW_N);
sc_status_reg_create(r6_pe_n);
sc_status_reg_create(r7_pe_bw_n);
sc_status_reg_create(r8_wbuf_size);
sc_status_reg_create(r9_data_buf_clb_size);
sc_status_reg_create(r10_data_buf_clb_n);
sc_status_reg_create(r11_data_buf_shift_size);
sc_status_reg_create(r12_data_out_n);
sc_status_end_create(regend);
void status_reg_param_link() {
r2_data_W_status.write(P_data_W);
r3_data_P_status.write(P_data_P);
r4_input_BW_N_status.write(P_input_BW_N);
r5_output_BW_N_status.write(P_pool_size);
r6_pe_n_status.write(P_pe_n);
r7_pe_bw_n_status.write(P_pe_bw_n);
r8_wbuf_size_status.write(P_wbuf_size);
r9_data_buf_clb_size_status.write(P_data_buf_clb_size);
r10_data_buf_clb_n_status.write(P_data_buf_clb_n);
r11_data_buf_shift_size_status.write(P_data_buf_shift_size);
r12_data_out_n_status.write(P_data_out_n);
}
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_output_width)> data_source_forward;
sc_fifo<sc_uint<31> > weight_ctrls_fifo;
sc_fifo<sc_uint<32> > ctrl_image_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_size_pkg_fifo;
sc_fifo<sc_uint<16> > ctrl_window_size_fifo;
sc_fifo<sc_uint<16> > ctrl_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stride_fifo;
sc_fifo<sc_uint<16> > ctrl_replay_fifo;
sc_fifo<sc_uint<16> > ctrl_zeropad_fifo;
sc_fifo<sc_uint<1> > ctrl_output_channel_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_buf_depth_fifo;
sc_fifo<sc_uint<1> > ctrl_db_output_fifo;
sc_fifo<sc_uint<1> > ctrl_image_data_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_type_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_N_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_N_fifo;
sc_fifo<sc_uint<16> > ctrl_acf_fifo;
// modules
hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n>
top_cnn;
sc_status_reg_create_dummy(top_cnn_reg);
SC_CTOR(cnn)
: data_sink_forward(P_X_fifo_deep), data_buf_sink_forward(P_BUF_fifo_deep), w_sink_forward(P_W_fifo_deep),
data_source_forward(P_Y_fifo_deep), weight_ctrls_fifo(16), ctrl_row_size_pkg_fifo(16),
ctrl_window_size_fifo(16), ctrl_depth_fifo(16), ctrl_stride_fifo(16), ctrl_replay_fifo(16),
ctrl_row_N_fifo(16), ctrl_acf_fifo(16), ctrl_zeropad_fifo(16), SC_INST(top_cnn), SC_INST(reg1),
SC_INST(regend), SC_INST(r0_dma_ingress), SC_INST(r1_dma_egress), SC_INST(r2_data_W), SC_INST(r3_data_P),
SC_INST(r4_input_BW_N), SC_INST(r5_output_BW_N), SC_INST(r6_pe_n), SC_INST(r7_pe_bw_n), SC_INST(r8_wbuf_size),
SC_INST(r9_data_buf_clb_size), SC_INST(r10_data_buf_clb_n), SC_INST(r11_data_buf_shift_size),
SC_INST(r12_data_out_n), ctrl_output_channel_fifo(16), ctrl_db_output_fifo(16), ctrl_pool_depth_fifo(16),
ctrl_pool_type_fifo(16), ctrl_pool_N_fifo(16), ctrl_pool_size_fifo(16), ctrl_stitch_depth_fifo(16),
ctrl_stitch_buf_depth_fifo(1), ctrl_image_data_fifo(16)
{
top_cnn.clk(clk);
top_cnn.reset(reset);
/*SC_METHOD(reset_logic);
sensitive << reset << iclear;
SC_CTHREAD(clear_reg, clk.pos());*/
top_cnn.data_sink(data_sink_forward);
top_cnn.data_buf_sink(data_buf_sink_forward);
top_cnn.w_sink(w_sink_forward);
top_cnn.data_source(data_source_forward);
top_cnn.weight_ctrls_in(weight_ctrls_fifo);
// top_cnn.data_ctrls_in(data_ctrls_fifo);
top_cnn.ctrl_row_N(ctrl_row_N_fifo);
top_cnn.ctrl_row_size_pkg(ctrl_row_size_pkg_fifo);
top_cnn.ctrl_window_size(ctrl_window_size_fifo);
top_cnn.ctrl_depth(ctrl_depth_fifo);
top_cnn.ctrl_stride(ctrl_stride_fifo);
top_cnn.ctrl_replay(ctrl_replay_fifo);
top_cnn.ctrl_image_size(ctrl_image_size_fifo);
top_cnn.ctrl_acf(ctrl_acf_fifo);
top_cnn.ctrl_zeropad(ctrl_zeropad_fifo);
top_cnn.ctrl_output_channel(ctrl_output_channel_fifo);
top_cnn.ctrl_stitch_depth(ctrl_stitch_depth_fifo);
top_cnn.ctrl_stitch_buf_depth(ctrl_stitch_buf_depth_fifo);
top_cnn.ctrl_db_output(ctrl_db_output_fifo);
top_cnn.ctrl_image_data(ctrl_image_data_fifo);
top_cnn.ctrl_pool_depth(ctrl_pool_depth_fifo);
top_cnn.ctrl_pool_type(ctrl_pool_type_fifo);
top_cnn.ctrl_pool_N(ctrl_pool_N_fifo);
top_cnn.ctrl_pool_size(ctrl_pool_size_fifo);
// status reg
sc_status_module_connect(reg1);
sc_status_reg_connect(r0_dma_ingress, reg1);
sc_status_reg_connect(r1_dma_egress, r0_dma_ingress);
sc_status_reg_connect(r2_data_W, r1_dma_egress);
sc_status_reg_connect(r3_data_P, r2_data_W);
sc_status_reg_connect(r4_input_BW_N, r3_data_P);
sc_status_reg_connect(r5_output_BW_N, r4_input_BW_N);
sc_status_reg_connect(r6_pe_n, r5_output_BW_N);
sc_status_reg_connect(r7_pe_bw_n, r6_pe_n);
sc_status_reg_connect(r8_wbuf_size, r7_pe_bw_n);
sc_status_reg_connect(r9_data_buf_clb_size, r8_wbuf_size);
sc_status_reg_connect(r10_data_buf_clb_n, r9_data_buf_clb_size);
sc_status_reg_connect(r11_data_buf_shift_size, r10_data_buf_clb_n);
sc_status_reg_connect(r12_data_out_n, r11_data_buf_shift_size);
sc_status_end_connect(regend, r12_data_out_n);
SC_CTHREAD(thread_cnn_stream_source, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_buf_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_w_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_ctrl, clk.pos());
reset_signal_is(reset, true);
}
void thread_cnn_stream_source() {
SC_STREAM_INTERFACE_CREATE_SOURCE(data_source, "-bus_bundle M_AXIS_Y")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_output_width) tmp_out = data_source_forward.read();
data_source.write(tmp_out);
count++;
r0_dma_ingress_status.write(count);
}
}
void thread_cnn_stream_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_sink, "-bus_bundle S_AXIS_X")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_sink.read();
data_sink_forward.write(tmp_in);
count++;
r1_dma_egress_status.write(count);
}
}
void thread_cnn_stream_buf_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_buf_sink, "-bus_bundle S_AXIS_BUF")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_buf_sink.read();
data_buf_sink_forward.write(tmp_in);
}
}
void thread_cnn_stream_w_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(w_sink, "-bus_bundle S_AXIS_W")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = w_sink.read();
w_sink_forward.write(tmp_in);
}
}
void thread_cnn_ctrl() {
SC_STREAM_INTERFACE_CREATE_SINK(ctrl_sink, "-bus_bundle S_AXIS_CTRL")
hwcore::pipes::SC_DATA_T(64) tmp_in;
status_reg_param_link();
while (true) {
do {
hls_pipeline(1);
tmp_in = ctrl_sink.read();
sc_uint<64> raw = tmp_in.data;
sc_uint<56> value = raw(56 - 1, 0);
sc_uint<8> address;
if (tmp_in.tkeep == 0) {
address = -1;
} else {
address = raw(64 - 1, 56);
}
#define add_new_reg_interface(name_, nr_) \
case nr_: \
name_##_fifo.write(value); \
break;
switch (address) {
add_new_reg_interface(weight_ctrls, 0);
add_new_reg_interface(ctrl_row_N, 1);
add_new_reg_interface(ctrl_row_size_pkg, 2);
add_new_reg_interface(ctrl_window_size, 3);
add_new_reg_interface(ctrl_depth, 4);
add_new_reg_interface(ctrl_stride, 5);
add_new_reg_interface(ctrl_replay, 6);
add_new_reg_interface(ctrl_image_size, 7);
add_new_reg_interface(ctrl_acf, 8);
add_new_reg_interface(ctrl_zeropad, 9);
add_new_reg_interface(ctrl_output_channel, 10);
add_new_reg_interface(ctrl_stitch_depth, 11);
add_new_reg_interface(ctrl_stitch_buf_depth, 12);
add_new_reg_interface(ctrl_db_output, 13);
add_new_reg_interface(ctrl_image_data, 14);
add_new_reg_interface(ctrl_pool_depth, 15);
add_new_reg_interface(ctrl_pool_type, 16);
add_new_reg_interface(ctrl_pool_N, 17);
add_new_reg_interface(ctrl_pool_size, 18);
default:
break;
|
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > E_Yout;
sc_signal<bool> E_Vld;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Vld("Vld"),
Rdy("Rdy"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
u_sc_fir8->Rdy(Rdy);
u_sc_fir8->Vld(Vld);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
u_sc_fir8->E_Vld(E_Vld);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
#endif
}
~sc_fir8_tb(void)
{
}
|
mux_pcnt |
sc_port<sc_signal_in_if<bool>,0> mout_i {"mout_i" |
E_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#define N_TX 4
#define N_RX 3
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket[N_RX];
while(true)
{
wait(clk.posedge_event());
txPacket[3] = (uint8_t)(Yin.read()); // LSB of Yin
txPacket[2] = (uint8_t)(Yin.read()>>8); // MSB of Yin
txPacket[1] = (uint8_t)Xin.read(); // Xin
txPacket[0] = (uint8_t)Cin.read(); // Cin
// Send to Emulator
for (int i=0; i<N_TX; i++)
{
x = txPacket[i];
while(write(fd, &x, 1)<=0) usleep(1);
}
// Receive from Emulator
for (int i=0; i<N_RX; i++)
{
while(read(fd, &y, 1)<=0) usleep(1);
rxPacket[i] = y;
}
Xout.write( (uint8_t)rxPacket[0]);
Yout.write((uint16_t)rxPacket[1]<<8 | (uint16_t)rxPacket[2]);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
SC_CTOR(E_fir_pe):
clk("clk"),
Cin("Cin"), Xin("Xin"), Xout("Xout"),
Yin("Yin"), Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
return;
}
// Set up serial port
options.c_cflag = B115200 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
}
~E_fir_pe(void)
{
}
|
<DIRNAME>test |
/* Signals */
sc_signal<bool> led {"led" |
full_adder |
public: sc_in<bool> a, b, cin;
public: sc_out<bool> sum, cout;
//---------------------------------------
public: SC_CTOR(full_adder)
{
SC_METHOD(process);
sensitive << a << b << cin;
}
//---------------------------------------
private: void process()
{
bool aANDb, aXORb, cinANDaXORb;
aANDb = a.read() & b.read();
aXORb = a.read() ^ b.read();
cinANDaXORb = cin.read() & aXORb;
//Calculate sum and carry out of the 1-BIT adder
sum = aXORb ^ cin.read();
cout = aANDb | cinANDaXORb;
//next_trigger(1, SC_NS);
}
//---------------------------------------
|
AXIS_ENGINE |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_out<DATA> din1;
bool send;
bool recv;
int id;
void DMA_MMS2() {
while (1) {
while (!send) wait();
for (int i = 0; i < input_len; i++) {
int d = DMA_input_buffer[i + input_offset];
din1.write({d, 1});
wait();
}
send = false;
wait();
sc_pause();
wait();
}
|
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
|
readMifaretest |
/* Signals */
gn_signal_mix i2c_sda {"i2c_sda" |
SerialToSerialBTtest |
/* Signals */
sc_signal<bool> led {"led" |
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
|
dcache |
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SDC;
sc_out<bool> STALL_SDC; // if stall donc miss else hit
// interface wrapper
sc_out<bool> DTA_VALID_SDC;
sc_out<bool> READ_SDC;
sc_out<bool> WRITE_SDC;
sc_out<sc_uint<2>> SIZE_SDC;
sc_out<sc_uint<32>> DT_SDC;
sc_out<sc_uint<32>> A_SDC;
sc_in<sc_uint<32>> DT_SW;
sc_in<bool> ACK_SW; // slave answer (slave dt valid)
sc_in<sc_uint<32>> ADR_SW;
sc_in<bool> GRANT;
sc_in<bool> STALL_SW;
//signals
//parse address from CPU
sc_signal<sc_uint<21>> address_tag;
sc_signal<sc_uint<7>> address_index;
sc_signal<sc_uint<4>> address_offset;
//parse address from MP
sc_signal<sc_uint<21>> mp_address_tag;
sc_signal<sc_uint<7>> mp_address_index;
sc_signal<sc_uint<4>> mp_address_offset;
//parse address from BUS
sc_signal<sc_uint<21>> bus_tag;
sc_signal<sc_uint<7>> bus_index;
sc_signal<sc_uint<4>> bus_offset;
sc_signal<sc_uint<4>> mp_last_addr_offset;
sc_signal<bool> way0_hit;
sc_signal<bool> way1_hit;
sc_signal<bool> miss;
sc_signal<sc_uint<32>> selected_data;
sc_signal<bool> current_LRU; // false: 0, true: 1
// WAYS 128 lines
sc_signal<bool> LRU_bit_check[128]; // bit to compare least recently used
// WAY 0
sc_signal<sc_uint<32>> w0_word[128][4];
sc_signal<sc_uint<21>> w0_TAG[128];
sc_signal<bool> w0_LINE_VALIDATE[128];
//WAY 1
sc_signal<sc_uint<32>> w1_word[128][4];
sc_signal<sc_uint<21>> w1_TAG[128];
sc_signal<bool> w1_LINE_VALIDATE[128];
//buffer
sc_signal<bool> write_buff;
sc_signal<bool> full, empty;
sc_signal<sc_uint<32>> adr_sc;
int burst_cpt;
sc_signal<sc_uint<32>> data_mask_sc;
//FMS signal debug
sc_signal<sc_uint<2>> current_state;
sc_signal<sc_uint<2>> future_state;
void adresse_parcer();
void miss_detection();
void new_state();
void state_transition();
void mae_output();
void buffer_manager();
void trace(sc_trace_file*);
buffercache buffcache_inst;
SC_CTOR(dcache) :
buffcache_inst("buffercache")
{
SC_METHOD(adresse_parcer);
sensitive << DATA_ADR_SM << ADR_SW;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< LOAD_SM
<< STORE_SM
<< way0_hit
<< way1_hit
<< CLK.neg();
SC_METHOD(new_state);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(mae_output);
sensitive << CLK.neg() << RESET_N;
reset_signal_is(RESET_N, false);
buffcache_inst.RESET_N(RESET_N);
buffcache_inst.CLK(CLK);
buffcache_inst.WRITE_OBUFF(write_buff);
buffcache_inst.ACK(ACK_SW);
buffcache_inst.DATA_C(DATA_SM);
buffcache_inst.ADR_C(DATA_ADR_SM);
buffcache_inst.STORE_C(STORE_SM);
buffcache_inst.LOAD_C(LOAD_SM);
buffcache_inst.SIZE_C(MEM_SIZE_SM);
buffcache_inst.ADR_I(ADR_SW);
buffcache_inst.FULL(full);
buffcache_inst.EMPTY(empty);
buffcache_inst.DATA_MP(DT_SDC);
buffcache_inst.ADR_MP(A_SDC);
buffcache_inst.STORE_MP(WRITE_SDC);
buffcache_inst.LOAD_MP(READ_SDC);
buffcache_inst.SIZE_MP(SIZE_SDC);
}
|
pcnttest |
/* Signals */
sc_signal<bool> led {"led" |
ACCNAME |
sc_uint<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
#else
sc_signal<bool> d_in1;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> write1;
sc_signal<bool> arrange1;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
sc_uint<32> g1 [256];
sc_uint<8> r1 [256];
//GEMM 1 Inputs
sc_uint<32> lhsdata1a[IN_BUF_LEN];
sc_uint<32> lhsdata2a[IN_BUF_LEN];
sc_uint<32> lhsdata3a[IN_BUF_LEN];
sc_uint<32> lhsdata4a[IN_BUF_LEN];
//Global Weights
sc_uint<32> rhsdata1[WE_BUF_LEN];
sc_uint<32> rhsdata2[WE_BUF_LEN];
sc_uint<32> rhsdata3[WE_BUF_LEN];
sc_uint<32> rhsdata4[WE_BUF_LEN];
//new sums bram
sc_int<32> lhs_sum1[SUMS_BUF_LEN];
sc_int<32> lhs_sum2[SUMS_BUF_LEN];
sc_int<32> lhs_sum3[SUMS_BUF_LEN];
sc_int<32> lhs_sum4[SUMS_BUF_LEN];
sc_int<32> rhs_sum1[SUMS_BUF_LEN];
sc_int<32> rhs_sum2[SUMS_BUF_LEN];
sc_int<32> rhs_sum3[SUMS_BUF_LEN];
sc_int<32> rhs_sum4[SUMS_BUF_LEN];
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<char> sIs1;
sc_fifo<char> sIs2;
sc_fifo<char> sIs3;
sc_fifo<char> sIs4;
sc_fifo<char> sIs5;
sc_fifo<char> sIs6;
sc_fifo<char> sIs7;
sc_fifo<char> sIs8;
sc_fifo<char> sIs9;
sc_fifo<char> sIs10;
sc_fifo<char> sIs11;
sc_fifo<char> sIs12;
sc_fifo<char> sIs13;
sc_fifo<char> sIs14;
sc_fifo<char> sIs15;
sc_fifo<char> sIs16;
sc_fifo<char> sWs1;
sc_fifo<char> sWs2;
sc_fifo<char> sWs3;
sc_fifo<char> sWs4;
sc_fifo<char> sWs5;
sc_fifo<char> sWs6;
sc_fifo<char> sWs7;
sc_fifo<char> sWs8;
sc_fifo<char> sWs9;
sc_fifo<char> sWs10;
sc_fifo<char> sWs11;
sc_fifo<char> sWs12;
sc_fifo<char> sWs13;
sc_fifo<char> sWs14;
sc_fifo<char> sWs15;
sc_fifo<char> sWs16;
sc_int<64> rf;
int ra=0;
sc_int<32> l_offset = 0;
int mask = 0;
int r = 0;
int sm = 0;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int g1_macs=0;
int g1_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_1;
sc_out<int> wstall_1;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Data_In();
void Tracker();
void Scheduler();
void Post1();
void schedule_gemm_unit(int, int, int, int, int,int,int);
int SHR(int,int);
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
sc_uint<32> mul_u8(sc_uint<8>,sc_uint<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512),sIs1(2048),sIs2(2048),sIs3(2048),sIs4(2048),sIs5(2048),sIs6(2048),sIs7(2048),sIs8(2048),
sIs9(2048),sIs10(2048),sIs11(2048),sIs12(2048),sIs13(2048),sIs14(2048),sIs15(2048),sIs16(2048),
WRQ2(512),sWs1(2048),sWs2(2048),sWs3(2048),sWs4(2048),sWs5(2048),sWs6(2048),sWs7(2048),sWs8(2048),
sWs9(2048),sWs10(2048),sWs11(2048),sWs12(2048),sWs13(2048),sWs14(2048),sWs15(2048),sWs16(2048){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS array_partition variable=g1 complete dim=0
#pragma HLS RESET variable=reset
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=inS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=rmax
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=lmax
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=outS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=schS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=inS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=p1S
}
|
HamReg |
HCGen *hgen; //this circuit generate a code word
SynGen *sgen; //this circuit calculate the syndrome
Corrector *corr; //this circuit correct and decode a word
//Ports
sc_in < bool > clk;
sc_in < sc_uint<15> > coded_din;
sc_out < sc_uint<15> > coded_dout;
sc_in < sc_uint<11> > din;
sc_out < sc_uint<11> > dout;
//signals to connect between the modules
sc_signal < sc_uint <4> > syndSig;
sc_signal< sc_uint <11> > din_sig;
sc_signal< sc_uint <15> > codeddout_sig;
// handshake signals
sc_in < bool > din_vld;
sc_out < bool > din_rdy;
sc_out < bool > codedout_vld;
sc_in < bool > codedout_rdy;
sc_in < bool > codedin_vld;
sc_out < bool > codedin_rdy;
sc_out < bool > dout_vld;
sc_in < bool > dout_rdy;
void ham_main_din(); //coding process
void ham_main_codedin(); //decoding process
SC_CTOR(HamReg){
hgen=new HCGen("hgen");
hgen->din( din );
hgen->dout( coded_dout );
hgen->clk(clk);
hgen->din_rdy(din_rdy);
hgen->din_vld(din_vld);
hgen->codedout_rdy(codedout_rdy);
hgen->codedout_vld(codedout_vld);
sgen=new SynGen("sgen");
sgen->din( coded_din );
sgen->dout( syndSig );
sgen->clk(clk);
corr=new Corrector("corr");
corr->datain( coded_din );
corr->syndin( syndSig );
corr->dout( dout );
corr->clk(clk);
corr->codedin_rdy(codedin_rdy);
corr->codedin_vld(codedin_vld);
corr->dout_rdy(dout_rdy);
corr->dout_vld(dout_vld);
SC_CTHREAD(ham_main_din,clk.pos());
SC_CTHREAD(ham_main_codedin,clk.pos());
sensitive << din;
sensitive << din_vld;
sensitive << clk.pos();
}
~HamReg(){
delete hgen;
delete sgen;
delete corr;
}
|
tb |
sc_in_clk clk;
sc_out< bool > rst;
cynw_p2p< input_data, ioConfig >::base_out out; /* from tb to dut. */
cynw_p2p< output_data, ioConfig >::base_in in; /* from dut to tb. */
stream_16X8::in <ioConfig> streamin;
stream_16X8::out <ioConfig> streamout;
FILE * ofile;
SC_CTOR( tb )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, out( "out" )
, streamin( "streamin" )
, streamout( "streamout" )
{
SC_CTHREAD( source, clk.pos() );
SC_CTHREAD( sink, clk.pos() );
streamout.clk_rst( clk, rst );
streamin.clk_rst( clk, rst );
/* Open a file to save DUT output. The environment variable
"BDW_SIM_CONFIG_DIR" is set by Stratus to a unique
directory for each simulation configuration. */
char filename[PATH_MAX];
char * dir = getenv( "BDW_SIM_CONFIG_DIR" );
if( !dir )
{
dir = ".";
}
sprintf( filename, "%s/response.dat", dir );
ofile = fopen( filename, "w" );
if( !ofile )
{
fprintf( stderr, "Could not open file '%s' for writing.\n", filename );
}
}
/* The module destructor closes the output file. */
~tb()
{
fclose( ofile );
}
sc_uint<8> x[8];
sc_uint<8> y[4];
sc_uint<8> data[16];
/* Declaration of source and sink thread functions. */
void source();
void sink();
/* Local data members of type sc_time, used to keep track of
simulation timings (e.g. latency of the DUT). */
sc_time start_time, end_time, clock_period;
|
sc_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<16> > mul;
sc_signal<sc_uint<16> > rYin;
void pe_thread(void)
{
while (true)
{
wait(clk.posedge_event());
Xout.write(Xin.read());
mul.write(Xin.read() * Cin.read()); // Multiplication
rYin.write(Yin.read()); // Delay 1-clock
Yout.write(rYin.read() + mul.read()); // Accumulation
}
}
SC_CTOR(sc_fir_pe):
clk("clk"),
Cin("Cin"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
}
~sc_fir_pe(void)
{
}
|
x0_multiplier |
// input :
sc_in<sc_uint<32>> OP1_SE, OP2_SE;
sc_in<sc_uint<2>> EXE_CMD_RD;
sc_in<bool> X02X1_POP_SX1;
sc_in<bool> DEC2X0_EMPTY_SD;
// output :
sc_out<sc_bv<320>> RES_RX0;
sc_out<bool> SELECT_HIGHER_BITS_RX0;
sc_out<bool> SIGNED_RES_RX0;
sc_out<bool> X02X1_EMPTY_SX0;
// General interace :
sc_in_clk CLK;
sc_in<bool> RESET;
sc_signal<sc_bv<64>> product[32];
sc_signal<sc_bv<64>> product_s1[20]; // product of stage 1
sc_signal<sc_bv<64>> product_s2[14]; // product of stage 2
sc_signal<sc_bv<64>> product_s3[10]; // product of stage 3
sc_signal<sc_bv<64>> product_s4[6]; // product of stage 4
sc_signal<sc_bv<64>> product_s5[4]; // product of stage 5
sc_signal<bool> signed_op;
sc_signal<bool> select_higher_bits_sx0;
sc_signal<bool> signed_res_sx0;
// fifo x02x1
sc_signal<sc_bv<x02x1_size>> x02x1_din_sx0;
sc_signal<sc_bv<x02x1_size>> x02x1_dout_sx0;
sc_signal<bool> x02x1_push_sx0, x02x1_full_sx0;
fifo<x02x1_size> fifo_inst;
void operation();
// stage 1 (11 CSA remind product 33)
void CSA_1();
void CSA_2();
void CSA_3();
void CSA_4();
void CSA_5();
void CSA_6();
void CSA_7();
void CSA_8();
void CSA_9();
void CSA_10();
void CSA_11();
// stage 2 (7 CSA remind product 33 and product_s1 21)
void CSA_12();
void CSA_13();
void CSA_14();
void CSA_15();
void CSA_16();
void CSA_17();
void CSA_18();
//stage 3 (5 CSA remind product 33)
void CSA_19();
void CSA_20();
void CSA_21();
void CSA_22();
void CSA_23();
//stage 4 (3 CSA remind product_s3 9 product 33)
void CSA_24();
void CSA_25();
void CSA_26();
//stage 5 (2 CSA remind product_s3 9)
void CSA_27();
void CSA_28();
//res => 320bits => 5x64 => M4 M3 M2 M1 M0
void manage_fifo();
void fifo_concat();
void fifo_unconcat();
void trace(sc_trace_file* tf);
SC_CTOR(x0_multiplier) :
fifo_inst("x02x1")
{
fifo_inst.DIN_S(x02x1_din_sx0);
fifo_inst.DOUT_R(x02x1_dout_sx0);
fifo_inst.EMPTY_S(X02X1_EMPTY_SX0);
fifo_inst.FULL_S(x02x1_full_sx0);
fifo_inst.PUSH_S(x02x1_push_sx0);
fifo_inst.POP_S(X02X1_POP_SX1);
fifo_inst.CLK(CLK);
fifo_inst.RESET_N(RESET);
SC_METHOD(operation);
sensitive << OP1_SE << OP2_SE << EXE_CMD_RD;
//stage 1
SC_METHOD(CSA_1);
sensitive << product[0] << product[1] << product[2];
SC_METHOD(CSA_2);
sensitive << product[3] << product[4] << product[5];
SC_METHOD(CSA_3);
sensitive << product[6] << product[7] << product[8];
SC_METHOD(CSA_4);
sensitive << product[9] << product[10] << product[11];
SC_METHOD(CSA_5);
sensitive << product[12] << product[13] << product[14];
SC_METHOD(CSA_6);
sensitive << product[15] << product[16] << product[17];
SC_METHOD(CSA_7);
sensitive << product[18] << product[19] << product[20];
SC_METHOD(CSA_8);
sensitive << product[21] << product[22] << product[23];
SC_METHOD(CSA_9);
sensitive << product[24] << product[25] << product[26];
SC_METHOD(CSA_10);
sensitive << product[27] << product[28] << product[29];
// stage 2
SC_METHOD(CSA_11);
sensitive << product_s1[0] << product_s1[1] << product_s1[2];
SC_METHOD(CSA_12);
sensitive << product_s1[3] << product_s1[4] << product_s1[5];
SC_METHOD(CSA_13);
sensitive << product_s1[6] << product_s1[7] << product_s1[8];
SC_METHOD(CSA_14);
sensitive << product_s1[9] << product_s1[10] << product_s1[11];
SC_METHOD(CSA_15);
sensitive << product_s1[12] << product_s1[13] << product_s1[14];
SC_METHOD(CSA_16);
sensitive << product_s1[15] << product_s1[16] << product_s1[17];
SC_METHOD(CSA_17);
sensitive << product_s1[18] << product_s1[19] << product[30];
// stage 3
SC_METHOD(CSA_18);
sensitive << product_s2[0] << product_s2[1] << product_s2[2];
SC_METHOD(CSA_19);
sensitive << product_s2[3] << product_s2[4] << product_s2[5];
SC_METHOD(CSA_20);
sensitive << product_s2[6] << product_s2[7] << product_s2[8];
SC_METHOD(CSA_21);
sensitive << product_s2[9] << product_s2[10] << product_s2[11];
SC_METHOD(CSA_22);
sensitive << product_s2[12] << product_s2[13] << product[31];
//stage 4
SC_METHOD(CSA_23);
sensitive << product_s3[0] << product_s3[1] << product_s3[2];
SC_METHOD(CSA_24);
sensitive << product_s3[3] << product_s3[4] << product_s3[5];
SC_METHOD(CSA_25);
sensitive << product_s3[6] << product_s3[7] << product_s3[8];
//stage 5
SC_METHOD(CSA_26);
sensitive << product_s4[0] << product_s4[1] << product_s4[2];
SC_METHOD(CSA_27);
sensitive << product_s4[3] << product_s4[4] << product_s4[5];
//fifo
SC_METHOD(fifo_concat);
sensitive << product_s5[0] << product_s5[1] << product_s5[2]
<< product_s5[3] << select_higher_bits_sx0 << signed_res_sx0;
SC_METHOD(fifo_unconcat);
sensitive << x02x1_dout_sx0;
SC_METHOD(manage_fifo);
sensitive << x02x1_full_sx0 << DEC2X0_EMPTY_SD;
}
|
s7 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s7_box();
SC_CTOR(s7)
{
SC_METHOD(s7_box);
sensitive << stage1_input;
}
|
buffercache |
sc_in<bool> RESET_N;
sc_in_clk CLK;
//INPUT from DCACHE
sc_in<bool> WRITE_OBUFF;
sc_in<bool> ACK;
sc_in<sc_uint<32>> DATA_C;
sc_in<sc_uint<32>> ADR_C;
sc_in<bool> STORE_C;
sc_in<bool> LOAD_C;
sc_in<sc_uint<2>> SIZE_C;
//Snoopy
sc_in<sc_uint<32>> ADR_I;
//OUTPUT
//TO DCACHE
sc_out<bool> FULL;
sc_out<bool> EMPTY;
//TO RAM
sc_out<sc_uint<32>> DATA_MP; // MP mem primaire
sc_out<sc_uint<32>> ADR_MP;
sc_out<bool> STORE_MP;
sc_out<bool> LOAD_MP;
sc_out<sc_uint<2>> SIZE_MP;
//signals
// buffers
sc_signal<bool> buffer_choice;
//buff0
sc_signal<sc_uint<32>> buff0_DATA;
sc_signal<sc_uint<32>> buff0_DATA_ADR;
sc_signal<bool> buff0_STORE;
sc_signal<bool> buff0_LOAD;
sc_signal<sc_uint<2>> buff0_SIZE;
sc_signal<bool> buff0_VALIDATE; // data valid on buffer
//buff1
sc_signal<sc_uint<32>> buff1_DATA;
sc_signal<sc_uint<32>> buff1_DATA_ADR;
sc_signal<bool> buff1_STORE;
sc_signal<bool> buff1_LOAD;
sc_signal<sc_uint<2>> buff1_SIZE;
sc_signal<bool> buff1_VALIDATE; // data valid on buffer
sc_signal<bool> busreq_we;
sc_signal<bool> wait_for_ack_falling_edge;
void fifo();
void write_output();
void bufferfull();
void read_buffer_choice();
void choice_buff();
void trace(sc_trace_file*);
SC_CTOR(buffercache)
{
SC_METHOD(fifo);
sensitive << CLK.neg() << ACK;
SC_METHOD(write_output);
sensitive << buffer_choice << buff0_VALIDATE << buff1_VALIDATE
<< buff0_LOAD << buff0_STORE << buff1_LOAD << buff1_STORE
<< ADR_I;
SC_METHOD(bufferfull);
sensitive << buff0_VALIDATE << buff1_VALIDATE;
SC_METHOD(choice_buff);
sensitive << RESET_N << ACK;
reset_signal_is(RESET_N, false);
}
|
desround |
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<sc_uint<4> > iteration_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<32> > R_i;
sc_in<sc_uint<32> > L_i;
sc_in<sc_uint<56> > Key_i;
sc_out<sc_uint<32> > R_o;
sc_out<sc_uint<32> > L_o;
sc_out<sc_uint<56> > Key_o;
sc_out<sc_uint<6> > s1_o, s2_o, s3_o, s4_o, s5_o, s6_o, s7_o, s8_o;
sc_in<sc_uint<4> > s1_i, s2_i, s3_i, s4_i, s5_i, s6_i, s7_i, s8_i;
void registers();
void round_proc();
sc_signal<sc_uint<56> > previous_key;
sc_signal<sc_uint<4> > iteration;
sc_signal<bool > decrypt; //When decrypting we rotate rigth instead of left
sc_signal<sc_uint<56> > non_perm_key;
sc_signal<sc_uint<48> > new_key;
sc_signal<sc_uint<32> > next_R;
///sc_signal<sc_uint<32> > expanRSig;
//Round key generator
key_gen *kg1;
SC_CTOR(desround)
{
kg1 = new key_gen("key_gen");
kg1->previous_key(previous_key);
kg1->iteration(iteration);
kg1->decrypt(decrypt);
kg1->new_key(new_key);
kg1->non_perm_key(non_perm_key);
SC_METHOD(registers);
sensitive << clk.pos();
sensitive << reset.neg();
SC_METHOD(round_proc);
sensitive << R_i << L_i << Key_i << iteration_i << decrypt_i;
sensitive << new_key << s1_i << s2_i << s3_i << s4_i << s5_i;
sensitive << s6_i << s7_i << s8_i;
}
|
cchan |
sc_in<unsigned int> rx;
sc_out<unsigned int> tx;
sc_fifo<unsigned char> from;
sc_fifo<unsigned char> to;
void intake();
void outtake();
sc_time baudperiod;
void set_baud(unsigned int baudrate);
cchan(sc_module_name name, int tx_buffer_size, int rx_buffer_size):
rx("rx"), tx("tx"),
from("fromfifo", rx_buffer_size), to("tofifo", tx_buffer_size) {
SC_THREAD(intake);
sensitive << rx;
SC_THREAD(outtake); /* Active when something is in the fifo. */
set_baud(2000000); /* The default is 2MHz. */
}
SC_HAS_PROCESS(cchan);
|
NoximNoC |
// I/O Ports
sc_in_clk clock; // The input clock for the NoC
sc_in<bool> reset; // The reset signal for the NoC
// Signals
sc_signal <bool> req_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <NoximFlit> flit_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <int> free_slots_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
// NoP
sc_signal <NoximNoP_data> NoP_data_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
// Matrix of tiles
NoximTile *t[MAX_STATIC_DIM][MAX_STATIC_DIM][MAX_STATIC_DIM];
// Global tables
NoximGlobalRoutingTable grtable;
NoximGlobalTrafficTable gttable;
void flitsMonitor()
{
if (!reset.read())
{
unsigned int count = 0;
for(int i=0; i<NoximGlobalParams::mesh_dim_x; i++)
for(int j=0; j<NoximGlobalParams::mesh_dim_y; j++)
for(int k=0; k<NoximGlobalParams::mesh_dim_z; k++)
count += t[i][j][k]->r->getFlitsCount();
cout << count << endl;
}
}
// Constructor
SC_CTOR(NoximNoC)
{
// Build the Mesh
buildMesh();
}
// Support methods
NoximTile* searchNode(const int id) const;
private:
void buildMesh();
|
counters |
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow2.write(false);
SC_METHOD(handleCount1);
sensitive<<clock.pos();
SC_METHOD(handleCount2);
sensitive<<clock.pos();
SC_METHOD(updateEnded);
sensitive<<clock.pos();
}
|
alu |
sc_in<sc_uint<32>> OP1_SE, OP2_SE;
sc_in<bool> CIN_SE;
sc_in<sc_uint<2>> CMD_SE;
sc_out<sc_uint<32>> RES_SE;
void operation();
void trace(sc_trace_file * tf);
SC_CTOR(alu) {
SC_METHOD(operation);
sensitive << OP1_SE << OP2_SE << CIN_SE << CMD_SE;
}
|
i2c_slave_controller |
sc_inout<sc_logic> sda;
sc_inout<sc_logic> scl;
enum states {READ_ADDR, SEND_ACK, READ_DATA, WRITE_DATA, SEND_ACK2 |
dual_memory | |
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#ifdef EMULATED
sc_out<sc_uint<8> > E_Xout;
sc_out<sc_uint<16> > E_Yout;
#endif
// void fir8_thread(void)
// {
// }
#ifdef VERILATED
V_fir_pe* u_fir_pe[N_PE_ARRAY];
#endif
#ifdef EMULATED
E_fir_pe* u_E_fir_pe;
// sc_signal<sc_uint<8> > E_Xout;
// sc_signal<sc_uint<16> > E_Yout;
#endif
#ifdef MTI_SIM
fir_pe* u_fir_pe[N_PE_ARRAY];
#endif
#if !defined(VERILATED) && !defined(MTI_SIM)
sc_fir_pe* u_fir_pe[N_PE_ARRAY];
#endif
sc_signal<sc_uint<8> > X[N_PE_ARRAY-1]; // X-input
sc_signal<sc_uint<16> > Y[N_PE_ARRAY-1]; // Accumulated
sc_signal<sc_uint<8> > C[N_PE_ARRAY]; // Filter-Tabs Coeff
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
// SC_THREAD(fir8_thread);
// sensitive << clk;
// Instaltiate PE array -----------------------------
char szPeName[16];
for (int i=0; i<N_PE_ARRAY; i++)
{
sprintf(szPeName, "u_PE_%d", i);
#ifdef VERILATED
u_fir_pe[i] = new V_fir_pe(szPeName);
#endif
#ifdef MTI_SIM
u_fir_pe[i] = new fir_pe(szPeName);
#endif
#if !defined(VERILATED) && !defined(MTI_SIM)
u_fir_pe[i] = new sc_fir_pe(szPeName);
#endif
C[i].write(sc_uint<8>(filter_taps[i]));
u_fir_pe[i]->Cin(C[i]);
u_fir_pe[i]->clk(clk);
}
#ifdef EMULATED
u_E_fir_pe = new E_fir_pe("u_PE_Emulated");
u_E_fir_pe->Cin(C[N_PE_ARRAY-1]);
u_E_fir_pe->clk(clk);
#endif
// Configure Array -----------------------------------
// 0-th PE
u_fir_pe[0]->Xin(Xin);
u_fir_pe[0]->Xout(X[0]);
u_fir_pe[0]->Yin(Yin);
u_fir_pe[0]->Yout(Y[0]);
// Systolic Array
for (int i=1; i<N_PE_ARRAY-1; i++)
{
u_fir_pe[i]->Xin(X[i-1]);
u_fir_pe[i]->Xout(X[i]);
u_fir_pe[i]->Yin(Y[i-1]);
u_fir_pe[i]->Yout(Y[i]);
}
// Last PE
#ifdef EMULATED
u_E_fir_pe->Xin(X[N_PE_ARRAY-2]);
u_E_fir_pe->Xout(E_Xout);
u_E_fir_pe->Yin(Y[N_PE_ARRAY-2]);
u_E_fir_pe->Yout(E_Yout);
#endif
u_fir_pe[N_PE_ARRAY-1]->Xin(X[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Xout(Xout);
u_fir_pe[N_PE_ARRAY-1]->Yin(Y[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Yout(Yout);
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
#ifdef EMULATED
sc_trace(fp, E_Xout, "E_Xout");
sc_trace(fp, E_Yout, "E_Yout");
#endif
char szTrace[8];
for (int i=0; i<N_PE_ARRAY-1; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
sprintf(szTrace, "Y_%d", i);
sc_trace(fp, Y[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
}
|
dut |
// Declare the clock and reset ports
sc_in< bool > clk;
sc_in< bool > rst;
// Declare the input port and the output port.
// The template specializations <DT_*> configure the
// modular interfaces to carry the desired datatypes.
// LAB EXERCISE: Add a second parameter to select TLM I/O
// OLD
cynw_p2p< input_t, CYN::TLM >::in din; // The input port
cynw_p2p< output_t, CYN::TLM >::out dout; // The output port
// NEW
//cynw_p2p< input_t, ioConfig >::in din; // The input port
//cynw_p2p< output_t, ioConfig >::out dout; // The output port
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, 0 );
// Connect the clk and rst signals to the modular interface ports
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1(); // the thread function
|
sc_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<16> > y;
void pe_thread(void)
{
//sc_uint<16> y=0; // Beware! Do NOT use variable for F/F model
while (true)
{
wait(clk.posedge_event());
Xout.write(Xin.read());
//y = Xin.read() * Cin.read() + Yin.read();
Yout.write(y);
y = Xin.read() * Cin.read() + Yin.read();
}
}
SC_CTOR(sc_fir_pe):
clk("clk"),
Cin("Cin"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
}
~sc_fir_pe(void)
{
}
|
s2 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s2_box();
SC_CTOR(s2)
{
SC_METHOD(s2_box);
sensitive << stage1_input;
}
|
s1 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s1_box();
SC_CTOR(s1)
{
SC_METHOD(s1_box);
sensitive << stage1_input;
}
|
System |
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > chan1;
cynw_p2p< output_t > chan2;
// Declare pointers for the testbench and dut modules
dut_wrapper *m_dut; // use the generated wrapper for all HLS modules
tb *m_tb;
// LAB EXERCISE: Declare a pointer for the memory
// NEW
RAM_64x8::wrapper<> *m_mem;
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, chan1( "chan1" )
, chan2( "chan2" )
{
// Connect the design module
m_dut = new dut_wrapper( "dut_wrapper" );
m_dut->clk( clk_sig );
m_dut->rst( rst_sig );
m_dut->din( chan1 );
m_dut->dout( chan2 );
// Connect the testbench
m_tb = new tb( "tb" );
m_tb->clk( clk_sig );
m_tb->rst( rst_sig );
m_tb->dout( chan1 );
m_tb->din( chan2 );
// LAB EXERCISE: Instantiate and connect the memory
// NEW
m_mem = new RAM_64x8::wrapper<>("mem");
m_dut->mem( *m_mem );
m_mem->clk_rst( clk_sig, rst_sig );
}
~System()
{
delete m_tb;
delete m_dut;
}
|
serial_tft |
sc_in<gn_mixed> sck {"sck" |
clkgen |
sc_out<bool> apb_clk {"apb_clk" |
Diviseur |
// input :
sc_in<sc_uint<32>> OP1_SE;
sc_in<sc_uint<32>> OP2_SE;
sc_in<sc_uint<2>> CMD_RD;
sc_in<bool> START_SE;
// output :
sc_out<sc_uint<32>> DIVIDER_RES_OUTPUT;
sc_out<bool> BUSY_SE;
sc_out<bool> DONE_SE;
// General interface:
sc_in_clk CLK;
// signals :
sc_signal<sc_biguint<64>> divisor_re;
sc_signal<sc_uint<32>> quotient_re;
sc_signal<sc_biguint<64>> reminder_re;
sc_signal<sc_biguint<64>> divisor_se;
sc_signal<sc_uint<32>> quotient_se;
sc_signal<sc_biguint<64>> reminder_se;
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> next_state;
sc_signal<sc_uint<6>> shift_cpt_se;
sc_signal<sc_uint<6>> shift_cpt_re;
sc_signal<bool> quotient_sign_se;
sc_signal<bool> reminder_sign_se;
//mae
void new_state();
void state_transition();
void mae_output();
void RET();
void trace(sc_trace_file * tf);
SC_CTOR(Diviseur)
{
SC_METHOD(new_state);
sensitive << CLK.pos();
SC_METHOD(state_transition);
sensitive << current_state << START_SE << shift_cpt_re << OP2_SE;
SC_METHOD(mae_output);
sensitive << current_state << START_SE << divisor_re
<< quotient_re << reminder_re
<< OP1_SE << OP2_SE << shift_cpt_re;
SC_METHOD(RET);
sensitive << reminder_re << quotient_re << CMD_RD;
}
|
display |
sc_port < sc_csp_channel_in_if < system_display_payload > > system_display_port_in;
SC_CTOR(display)
{
SC_THREAD(main);
}
void main();
|
CounterTestbench |
// Inputs
sc_in<bool> clk;
sc_in<sc_uint<N> > count_out;
sc_in<bool> overflow_intr;
sc_in<bool> underflow_intr;
//Outputs
sc_out<bool> reset;
sc_out<bool> up_down_ctrl;
sc_out<bool> count_enable;
// Main function of the module
void do_testbench();
SC_CTOR(CounterTestbench){
SC_THREAD(do_testbench);
sensitive << clk.pos();
}
|
wb_ram_sc |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<sc_uint<32>> ADR_I;
sc_in<bool> CYC_I; // when asserted indicates that a valid bus cycle in progress
sc_in<sc_uint<2>> SEL_I; // select which words on DAT_O are valid
sc_in<bool> STB_I;
sc_in<bool> WE_I;
sc_out<sc_uint<32>> DAT_O;
sc_out<bool> ACK_O; // when asserted indicates the termination of a bus cycle
//interface with module
sc_in<sc_uint<32>> RAM_DT_I;
sc_out<sc_uint<32>> RAM_DT_O;
sc_out<sc_uint<32>> RAM_ADR_O;
sc_out<bool> RAM_WE_O;
sc_out<sc_uint<2>> RAM_SEL_O;
sc_out<bool> RAM_DTA_RDY_O;
//interface with BCU
sc_in<bool> ARBITER_SEL_I;
//signals
sc_signal<sc_uint<4>> current_state;
sc_signal<sc_uint<4>> future_state;
sc_signal<sc_uint<32>> ADR_REG;
sc_signal<bool> strobe;
void strobe_signal();
void new_state();
void state_transition();
void mae_output();
void trace(sc_trace_file*);
SC_CTOR(wb_ram_sc)
{
SC_METHOD(new_state);
sensitive << CLK.pos() << RESET_N;
SC_METHOD(state_transition);
sensitive << current_state << STB_I << CYC_I << ARBITER_SEL_I << WE_I;
SC_METHOD(mae_output);
sensitive << current_state << WE_I;
}
|
e4067test |
/* Signals */
sc_signal<bool> led {"led" |
receiver)
//class receiver : public sc_module
{
/// Input port for datac from the transmitter
sc_in<Packet> datac;
/// Input port for the strobe from the transmitter
sc_in<sc_bit> strobe;
/// reset port
sc_in<bool> rst_n;
/// clock port
sc_in<bool> clk;
/// output port for the data to the receiver switch
sc_out<Packet> dataout;
/// analysis of the strobe and decision if to sample or not the next PC
void strobe_analysis();
/// manage the output, deciding from which FF to take the results (pos edge triggered, neg edge triggered, or synch reg)
void receiver_register();
/// evaluate when the strobe has changed the last time
void time_strobe();
/// manage the positive edge sensitive input FF
void update_P();
/// manage the negative edge sensitive input FF
void update_N();
/// manage the synchronisation register
void synch_reg_module();
/// matrix of 2 lines. In the first line i put the samples sampled on clkR edge, on the second one the ones from clkR2
bool** sample_container;
/// used to manage the output
Packet datac_container[2];
/// counter to decide which column of sample_container i'm analyzing
int actual_sample;
/// general counter
int i; //general counter
/// vector used to decide when to sample on clkR1 edge
bool* must_i_sample;
/// when strobe has changed the last time
sc_time strobelastchange;
/// manage particular case in which strobe and clkR change simultaneously
sc_time synchro_delta_cycle; //in case strobe and clkR change simultaneously, strobechange is evaluated BEFORE strobeget function
/// manage kernel
sc_event update_event_P;
/// manage kernel
sc_event update_event_N;
/// manage kernel
sc_event output_update;
/// info in reg_N
Packet save_register_N;
/// info in reg_P
Packet save_register_P;
/// info to output
Packet saved_packet;
/// info from synchreg
Packet synch_reg_out;
/// vs flag
bool vs_flag;
/// flag set in case of error
bool error_flag;
//SC_CTOR(receiver)
SC_HAS_PROCESS(receiver);
/// constructor of the transmitter
receiver(sc_module_name name_ , int N_R , int N_T, int Tsw, int Tsu) : sc_module(name_), m_N_R(N_R), m_N_T(N_T),m_Tsw(Tsw),m_Tsu(Tsu |
sample_container = new bool*[2];
sample_container[0] = new bool[(m_N_T*2)+1];
sample_container[1] = new bool[(m_N_T*2)+1];
must_i_sample = new bool[(m_N_T*2)+1];
SC_METHOD(receiver_register);
//sensitive<<clk.pos()<<rst_n.neg();
sensitive<<output_update<<rst_n.neg();
SC_THREAD(strobe_analysis);
sensitive<<clk<<rst_n.neg();
SC_METHOD(update_P);
sensitive<<update_event_P<<rst_n.neg(); //sensitive on clkr1
SC_METHOD(update_N);
sensitive<<update_event_N<<rst_n.neg();
SC_METHOD(synch_reg_module);
//sensitive<<clk.pos()<<rst_n.neg();
sensitive<<update_event_P<<rst_n.neg(); //sensitive on clkr1
SC_METHOD(time_strobe);
sensitive<<strobe;
dont_initialize();
}
private:
int m_N_R,m_N_T,m_Tsw,m_Tsu;
|
fir |
sc_in<bool> clk;
sc_in<bool> rst;
sc_in< sc_int<16> > inp;
sc_out< sc_int<16> > outp;
sc_in<bool> inp_sig_vld;
sc_in<bool> outp_sig_rdy;
sc_out<bool> inp_sig_rdy;
sc_out<bool> outp_sig_vld;
//Just prototype this here as you have a lot to type and we don't want to
//inline the whole behavioral in this file
//this should just be ports, threads, and constructors
void fir_main(void);
SC_CTOR( fir )
{
//Takes 2 arguments
//name of the clock thread function
//edge of the clock the thread is sensitive to
SC_CTHREAD( fir_main, clk.pos() );
//Takes 2 arguments
//name of the reset input port
//polarity of the reset (true = reset is asserted high, false = reset is asserted low)
reset_signal_is( rst, true );
}
|
System |
// testbench and DUT modules
dut_wrapper *m_dut; // use the generated wrapper for all hls_modules
tb *m_tb;
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > in_chan1; // For data going into the design
cynw_p2p< input_t > in_chan2; // For data going into the design
cynw_p2p< output_t > out_chan; // For data coming out of the design
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, in_chan1( "in_chan1" )
, in_chan2( "in_chan2" )
, out_chan( "out_chan" )
{
// Connect the design module
m_dut = new dut_wrapper( "dut_wrapper" );
m_dut->clk( clk_sig );
m_dut->rst( rst_sig );
m_dut->din_1( in_chan1 );
m_dut->din_2( in_chan2 );
m_dut->dout( out_chan );
// Connect the testbench
m_tb = new tb( "tb" );
m_tb->clk( clk_sig );
m_tb->rst( rst_sig );
m_tb->dout_1( in_chan1 );
m_tb->dout_2( in_chan2 );
m_tb->din( out_chan );
}
~System()
{
delete m_tb;
delete m_dut;
}
|
stim_gen |
sc_port < sc_csp_channel_out_if < stimulus_system_payload > > stimulus_system_port_out;
SC_CTOR(stim_gen)
{
SC_THREAD(main);
}
void main();
|
ledctest |
/* Signals */
sc_signal<bool> led {"led" |
System |
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > in_chan_1; // For data going into the design
cynw_p2p< input_t > in_chan_2; // For data going into the design
cynw_p2p< output_t > out_chan; // For data coming out of the design
// The testbench and DUT modules.
dut_wrapper *m_dut; // use the generated wrapper for the DUT hls module
tb *m_tb;
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, in_chan_1( "in_chan_1" )
, in_chan_2( "in_chan_2" )
, out_chan( "out_chan" )
{
// Connect the design module
m_dut = new dut_wrapper( "dut_wrapper" );
m_dut->clk( clk_sig );
m_dut->rst( rst_sig );
m_dut->din_1( in_chan_1 );
m_dut->din_2( in_chan_2 );
m_dut->dout( out_chan );
// Connect the testbench
m_tb = new tb( "tb" );
m_tb->clk( clk_sig );
m_tb->rst( rst_sig );
m_tb->dout_1( in_chan_1 );
m_tb->dout_2( in_chan_2 );
m_tb->din( out_chan );
}
~System()
{
delete m_tb;
delete m_dut;
}
|
sc_fir8 |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
V_fir_pe* u_fir_pe[N_PE_ARRAY];
sc_signal<sc_uint<4> > X[N_PE_ARRAY-1]; // X-input
sc_signal<sc_uint<4> > Y[N_PE_ARRAY-1]; // Accumulated
sc_signal<sc_uint<6> > C[N_PE_ARRAY]; // Filter-Tabs Coeff
sc_signal<bool> Valid[N_PE_ARRAY];
sc_trace_file* fp; // VCD file
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
// Instaltiate PE array
char szPeName[16];
for (int i=0; i<N_PE_ARRAY; i++)
{
sprintf(szPeName, "u_PE_%d", i);
u_fir_pe[i] = new V_fir_pe(szPeName);
C[i].write(sc_uint<8>(filter_taps[i])); // Filter Coeff.
u_fir_pe[i]->Cin(C[i]);
u_fir_pe[i]->clk(clk);
}
// 0-th PE
u_fir_pe[0]->Xin(Xin);
u_fir_pe[0]->Xout(X[0]);
u_fir_pe[0]->Yin(Yin);
u_fir_pe[0]->Yout(Y[0]);
u_fir_pe[0]->Rdy(Rdy);
u_fir_pe[0]->Vld(Valid[0]);
// Systolic Array
for (int i=1; i<N_PE_ARRAY-1; i++)
{
u_fir_pe[i]->Xin(X[i-1]);
u_fir_pe[i]->Xout(X[i]);
u_fir_pe[i]->Yin(Y[i-1]);
u_fir_pe[i]->Yout(Y[i]);
u_fir_pe[i]->Rdy(Valid[i-1]);
u_fir_pe[i]->Vld(Valid[i]);
}
// Last PE
u_fir_pe[N_PE_ARRAY-1]->Xin(X[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Xout(Xout);
u_fir_pe[N_PE_ARRAY-1]->Yin(Y[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Yout(Yout);
u_fir_pe[N_PE_ARRAY-1]->Rdy(Valid[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Vld(Vld);
// VCD Trace
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
char szTrace[16];
for (int i=0; i<N_PE_ARRAY-1; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
sprintf(szTrace, "Y_%d", i);
sc_trace(fp, Y[i], szTrace);
sprintf(szTrace, "Valid_%d", i);
sc_trace(fp, Valid[i], szTrace);
}
}
~sc_fir8(void)
{
}
|
fifo)
//class fifo : public sc_module
{
/// It is used to get input values from a file which represents the resource.
sc_in<Packet> FIFO_in;
/// reset signal
sc_in<sc_bit> rst_n;
/// Input of the resource ready signal. If the resource is ready (true) i can output values from the fifo every clock period.
sc_in<sc_bit> Resource_ready;
/// It gives packets to the switch only when the switch is ready to take a new packet (see resourceready signal).
sc_out<Packet> FIFO_out;
/// Row and column of the switch in the Network.
public:
/// Row of the switch in the Network.
int row_fifo;
/// Col of the switch in the Network.
int col_fifo;
/*! Main clocked process of the fifo module.
*/
void prc_fifo();
/// Useful to see how many elements are memorized in the fifo.
int FIFO_LastPosition;
/// Useful to see how many elements are memorized in the fifo.
struct Packet FIFO_vector[10];
/// Variable used to memorize the next output value of the fifo.
struct Packet FIFO_reg;
/// Counter for loops.
int i;
/// Clock of the fifo
sc_clock clkfifo;
/// Open a file in order to write on it.
ofstream fifofile;
/// Signal which samples the input.
struct Packet FIFO_in_s,FIFO_reg_appoggio;
/// Constructor: Initializes the fifo (all zeros) and open the fifofile to write on it.
SC_CTOR(fifo):clkfifo("clkfifo",1,SC_NS |
SC_METHOD(prc_fifo);
sensitive<<rst_n<<clkfifo; //is the same of having sensitive<<d<<empty
//dont_initialize();
FIFO_LastPosition=0;
for (i=0;i<10;i++)
FIFO_vector[i]=empty_NL_PDU;
FIFO_reg=empty_NL_PDU;
fifofile.open ("fifo.txt",ios::trunc);
fifofile << "SIMULATION STARTS NOW: "<<endl<<endl;
fifofile.close();
}
|
s5 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s5_box();
SC_CTOR(s5)
{
SC_METHOD(s5_box);
sensitive << stage1_input;
}
|
DFTModule |
sc_in_clk clock;
sc_in<bool> f_Enable;
sc_in<bool> f_RxSamples;
sc_in<bool> f_Calculate;
sc_in<bool> Reset;
sc_in<int> N;
sc_in<double> Sample;
sc_out<double> OutReal;
sc_out<double> OutImg;
double* _Samples;
int _N;
int _Counter;
void DFT(void);
SC_CTOR(DFTModule)
{
SC_METHOD(DFT);
sensitive << clock.pos();
sensitive << Reset;
}
~DFTModule()
{
if(_Samples)
delete[] _Samples;
}
|
fpu_monitor |
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> mult_en; // Signals that a multiply computation step should be performed
sc_in<sc_logic> add_en; // Signals that an add computation step should be performed
sc_in<sc_lv<16> > srf_in; // Scalar operand from SRF
sc_in<sc_lv<16> > grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_in<sc_lv<16> > grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_in<sc_lv<16> > grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_in<sc_lv<16> > grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_in<sc_lv<16> > even_in[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_in<sc_lv<16> > odd_in[SIMD_WIDTH]; // Input from ODD_BANK
sc_in<sc_lv<8> > mult_in1_sel; // Selects input 1 for addition
sc_in<sc_lv<8> > mult_in2_sel; // Selects input 2 for multiplication
sc_in<sc_lv<8> > add_in1_sel; // Selects input 1 for addition
sc_in<sc_lv<8> > add_in2_sel; // Selects input 2 for multiplication
sc_in<sc_logic> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
sc_in<sc_lv<16> > output[SIMD_WIDTH]; // Output of the Floating Point Unit
#else
sc_in_clk clk;
sc_in<bool> rst;
sc_in<bool> mult_en; // Signals that a multiply computation step should be performed
sc_in<bool> add_en; // Signals that an add computation step should be performed
sc_in<half> srf_in; // Scalar operand from SRF
sc_in<half> grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_in<half> grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_in<half> grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_in<half> grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_in<half> even_in[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_in<half> odd_in[SIMD_WIDTH]; // Input from ODD_BANK
sc_in<uint8_t> mult_in1_sel; // Selects input 1 for addition
sc_in<uint8_t> mult_in2_sel; // Selects input 2 for multiplication
sc_in<uint8_t> add_in1_sel; // Selects input 1 for addition
sc_in<uint8_t> add_in2_sel; // Selects input 2 for multiplication
sc_in<bool> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
sc_in<half> output[SIMD_WIDTH]; // Output of the Floating Point Unit
#endif
// Internal events
sc_event_or_list output_change_evnt; // Event signaling that any of the outputs has changed
// Internal variables and signals for checking
half **mpipe;
half **apipe;
half *m1_in;
half *m2_in;
half *a1_in;
half *a2_in;
half *pred_out;
bool error;
SC_CTOR(fpu_monitor) {
SC_THREAD(monitor_thread);
sensitive << clk.pos();
SC_THREAD(mirror_thread);
sensitive << rst.neg() << clk.pos();
SC_METHOD(out_mirror_thread);
int i, j;
mpipe = new half*[MULT_STAGES];
for (i = 0; i < MULT_STAGES; i++) {
mpipe[i] = new half[SIMD_WIDTH];
for (j = 0; j < SIMD_WIDTH; j++)
mpipe[i][j] = half_float::half_cast<half>(0.0);
}
apipe = new half*[ADD_STAGES];
for (i = 0; i < ADD_STAGES; i++) {
apipe[i] = new half[SIMD_WIDTH];
for (j = 0; j < SIMD_WIDTH; j++)
apipe[i][j] = half_float::half_cast<half>(0.0);
}
m1_in = new half[SIMD_WIDTH];
m2_in = new half[SIMD_WIDTH];
a1_in = new half[SIMD_WIDTH];
a2_in = new half[SIMD_WIDTH];
pred_out = new half[SIMD_WIDTH];
for (i = 0; i < SIMD_WIDTH; i++) {
m1_in[i] = half_float::half_cast<half>(0.0);
m2_in[i] = half_float::half_cast<half>(0.0);
a1_in[i] = half_float::half_cast<half>(0.0);
a2_in[i] = half_float::half_cast<half>(0.0);
pred_out[i] = half_float::half_cast<half>(0.0);
}
error = false;
}
void end_of_elaboration() {
// creates output_change_evnt once all ports are bounded
for (int i = 0; i < SIMD_WIDTH; i++) {
output_change_evnt |= output[i]->value_changed_event();
}
}
void monitor_thread(); // Outputs the behavior for the first SIMD rail, and automatically checks the functionality
void mirror_thread(); // Mirror FPU behavior for checking its functionality
void out_mirror_thread(); // Mirror FPU output for checking functionality
|
Producer |
sc_out<int> data;
int generatedNumber;
int i;
SC_CTOR(Producer){
data.initialize(42); //initialisiert den Ausgangsport mit dem angegebenen Wert (ansonsten 0)
SC_THREAD(produce);
}
void produce()
{
i = 0;
while(i < 10) {
generatedNumber = rand();
cout << "[" << sc_time_stamp() << "](" << name() << "): generated " << generatedNumber << endl;
data.write(generatedNumber);
//data = generatedNumber; //geht bei SC_SIGNAL auch
wait(SC_ZERO_TIME); //sonst kommt der Consumer nie dran
i++;
}
}
|
cpu |
sc_in<bool> clk;
sc_in<bool> reset;
axi_tc_in s_ctl;
axi_tc_out m_ctl;
int exitval;
void th_main()
{
if (reset.read() == RLEVEL) for (int i = 0; i < 2; i++) wait();
#if 0
printf("&s_ctl: %p\n", &s_ctl);
printf("s_gctl: %p\n", s_gctl);
// printf("sbrk(0): %p\n", sbrk(0));
{int var; printf("var: %p\n", &var);}
{void *heap = memalign(64,1024); printf("aheap: %p\n", heap);}
{void *heap = malloc(1UL<<30); printf("heap: %p\n", heap); if (heap!=NULL) free(heap);}
#endif
// &s_ctl: 0x7ffc632447e0
// s_gctl: 0x8da410
// sbrk(0): 0xb58000
// var: 0x7f5c66946d6c
// aheap: 0x7fe0dc0008c0
// heap: 0x7f5c1ffff010
int _sub_main(int argc, char *argv[]);
exitval = _sub_main(sc_argc(), (char**)sc_argv());
// cout << "Info: Application exit value: " << exitval << endl;
sc_stop();
}
SC_CTOR(cpu) :
exitval(-1)
{
// initialize global references to ports
s_gctl[0] = &s_ctl;
m_gctl[0] = &m_ctl;
#if 0
printf("&s_ctl: %p\n", &s_ctl);
printf("s_gctl: %p\n", s_gctl);
// printf("sbrk(0): %p\n", sbrk(0));
{int var; printf("var: %p\n", &var);}
{void *heap = memalign(64,1024); printf("aheap: %p\n", heap);}
{void *heap = malloc(1UL<<30); printf("heap: %p\n", heap); /*if (heap!=NULL) free(heap);*/}
#endif
// &s_ctl: 0x7ffc632447e0
// s_gctl: 0x8da410
// sbrk(0): 0xaf5000
// var: 0x7ffc63242790
// aheap: 0x10e9180
// heap: 0x7f5c672ee010
SC_THREAD(th_main);
sensitive << clk.pos();
// sensitive << s_ctl.data_chg() << s_ctl.valid_chg() << m_ctl.ready_chg();
reset_signal_is(reset, RLEVEL);
}
|
dcache |
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SC;
sc_out<bool> STALL_SC; // if stall donc miss else hit
// interface MP
sc_out<bool> DTA_VALID_SC;
sc_out<bool> READ_SC, WRITE_SC;
sc_out<sc_uint<2>> SIZE_SC;
sc_out<sc_uint<32>> DT_SC;
sc_out<sc_uint<32>> A_SC;
sc_in<sc_uint<32>> DT_SP;
sc_in<sc_uint<32>> A_SP;
sc_in<bool> SLAVE_ACK_SP; // slave answer (slave dt valid)
//signals
//parse address from CPU
sc_signal<sc_uint<21>> address_tag;
sc_signal<sc_uint<7>> address_index;
sc_signal<sc_uint<4>> address_offset;
//parse address from MP
sc_signal<sc_uint<21>> mp_address_tag;
sc_signal<sc_uint<7>> mp_address_index;
sc_signal<sc_uint<4>> mp_address_offset;
sc_signal<sc_uint<4>> mp_last_addr_offset;
sc_signal<bool> way0_hit;
sc_signal<bool> way1_hit;
sc_signal<bool> miss;
sc_signal<sc_uint<32>> selected_data;
sc_signal<bool> current_LRU; // false: 0, true: 1
// WAYS 128 lines
sc_signal<bool> LRU_bit_check[128]; // bit to compare least recently used
// WAY 0
sc_signal<sc_uint<32>> w0_word[128][4];
sc_signal<sc_uint<21>> w0_TAG[128];
sc_signal<bool> w0_LINE_VALIDATE[128];
//WAY 1
sc_signal<sc_uint<32>> w1_word[128][4];
sc_signal<sc_uint<21>> w1_TAG[128];
sc_signal<bool> w1_LINE_VALIDATE[128];
//buffer
sc_signal<bool> write_buff, read_buff;
sc_signal<bool> full, empty;
sc_signal<sc_uint<32>> adr_sc;
sc_signal<sc_uint<32>> dt_sc;
int burst_cpt;
sc_signal<sc_uint<32>> data_mask_sc;
//FMS signal debug
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> future_state;
void adresse_parcer();
void miss_detection();
void new_state();
void state_transition();
void mae_output();
void buffer_manager();
void trace(sc_trace_file*);
buffercache buffcache_inst;
SC_CTOR(dcache) :
buffcache_inst("buffercache")
{
SC_METHOD(adresse_parcer);
sensitive << DATA_ADR_SM << A_SP;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< LOAD_SM
<< STORE_SM
<< way0_hit
<< way1_hit
<< CLK.neg();
SC_METHOD(new_state);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(mae_output);
sensitive << CLK.neg() << RESET_N << mp_address_tag
<< mp_address_index << mp_address_offset;
reset_signal_is(RESET_N, false);
buffcache_inst.RESET_N(RESET_N);
buffcache_inst.CLK(CLK);
buffcache_inst.WRITE_OBUFF(write_buff);
buffcache_inst.READ_OBUFF(read_buff);
buffcache_inst.DATA_C(DATA_SM);
buffcache_inst.ADR_C(DATA_ADR_SM);
buffcache_inst.STORE_C(STORE_SM);
buffcache_inst.LOAD_C(LOAD_SM);
buffcache_inst.SIZE_C(MEM_SIZE_SM);
buffcache_inst.FULL(full);
buffcache_inst.EMPTY(empty);
buffcache_inst.DATA_MP(DT_SC);
buffcache_inst.ADR_MP(A_SC);
buffcache_inst.STORE_MP(WRITE_SC);
buffcache_inst.LOAD_MP(READ_SC);
buffcache_inst.SIZE_MP(SIZE_SC);
}
|
des |
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<bool > load_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<64> > data_i;
sc_in<sc_uint<64> > key_i;
sc_out<sc_uint<64> > data_o;
sc_out<bool > ready_o;
//Registers for iteration counters
sc_signal<sc_uint<4> > stage1_iter, next_stage1_iter;
sc_signal<bool > next_ready_o;
sc_signal<sc_uint<64> > next_data_o;
sc_signal<bool > data_ready, next_data_ready;
//Conections to desround stage1
sc_signal<sc_uint<32> > stage1_L_i;
sc_signal<sc_uint<32> > stage1_R_i;
sc_signal<sc_uint<56> > stage1_round_key_i;
sc_signal<sc_uint<4> > stage1_iteration_i;
sc_signal<sc_uint<32> > stage1_R_o;
sc_signal<sc_uint<32> > stage1_L_o;
sc_signal<sc_uint<56> > stage1_round_key_o;
sc_signal<sc_uint<6> > s1_stag1_i, s2_stag1_i, s3_stag1_i, s4_stag1_i, s5_stag1_i, s6_stag1_i, s7_stag1_i, s8_stag1_i;
sc_signal<sc_uint<4> > s1_stag1_o, s2_stag1_o, s3_stag1_o, s4_stag1_o, s5_stag1_o, s6_stag1_o, s7_stag1_o, s8_stag1_o;
void des_proc();
void reg_signal();
desround *rd1;
s1 *sbox1;
s2 *sbox2;
s3 *sbox3;
s4 *sbox4;
s5 *sbox5;
s6 *sbox6;
s7 *sbox7;
s8 *sbox8;
SC_CTOR(des)
{
SC_METHOD(reg_signal);
sensitive << clk.pos();
sensitive << reset.neg();
SC_METHOD(des_proc);
sensitive << data_i << key_i << load_i << stage1_iter << data_ready;
sensitive << stage1_L_o << stage1_R_o << stage1_round_key_o;
rd1 = new desround("round1");
sbox1 = new s1("s1");
sbox2 = new s2("s2");
sbox3 = new s3("s3");
sbox4 = new s4("s4");
sbox5 = new s5("s5");
sbox6 = new s6("s6");
sbox7 = new s7("s7");
sbox8 = new s8("s8");
//For each stage in the pipe one instance
//First stage always present
rd1->clk(clk);
rd1->reset(reset);
rd1->iteration_i(stage1_iteration_i);
rd1->decrypt_i(decrypt_i);
rd1->R_i(stage1_R_i);
rd1->L_i(stage1_L_i);
rd1->Key_i(stage1_round_key_i);
rd1->R_o(stage1_R_o);
rd1->L_o(stage1_L_o);
rd1->Key_o(stage1_round_key_o);
rd1->s1_o(s1_stag1_i);
rd1->s2_o(s2_stag1_i);
rd1->s3_o(s3_stag1_i);
rd1->s4_o(s4_stag1_i);
rd1->s5_o(s5_stag1_i);
rd1->s6_o(s6_stag1_i);
rd1->s7_o(s7_stag1_i);
rd1->s8_o(s8_stag1_i);
rd1->s1_i(s1_stag1_o);
rd1->s2_i(s2_stag1_o);
rd1->s3_i(s3_stag1_o);
rd1->s4_i(s4_stag1_o);
rd1->s5_i(s5_stag1_o);
rd1->s6_i(s6_stag1_o);
rd1->s7_i(s7_stag1_o);
rd1->s8_i(s8_stag1_o);
sbox1->stage1_input(s1_stag1_i);
sbox1->stage1_output(s1_stag1_o);
sbox2->stage1_input(s2_stag1_i);
sbox2->stage1_output(s2_stag1_o);
sbox3->stage1_input(s3_stag1_i);
sbox3->stage1_output(s3_stag1_o);
sbox4->stage1_input(s4_stag1_i);
sbox4->stage1_output(s4_stag1_o);
sbox5->stage1_input(s5_stag1_i);
sbox5->stage1_output(s5_stag1_o);
sbox6->stage1_input(s6_stag1_i);
sbox6->stage1_output(s6_stag1_o);
sbox7->stage1_input(s7_stag1_i);
sbox7->stage1_output(s7_stag1_o);
sbox8->stage1_input(s8_stag1_i);
sbox8->stage1_output(s8_stag1_o);
}
|
wrapper_mod)
//class wrapper_mod : public sc_module
{
private:
int m_N_left,m_N_right;
public:
///data input port of the left side of the wrapper
sc_in<Packet> L_datain;
///data output port of the left side of the wrapper
sc_out<Packet> L_dataout;
///data input port of the right side of the wrapper
sc_in<Packet> R_datain;
///data output port of the right side of the wrapper
sc_out<Packet> R_dataout;
///clock input form the switch on the left side of the wrapper
sc_in<bool> clkL;
///clock input form the switch on the right side of the wrapper
sc_in<bool> clkR;
///reset input
sc_in<bool> rst_n;
///instantiation of the transmitters sub-blocks
transmitter tx_LtoR;
///instantiation of the transmitters sub-blocks
transmitter tx_RtoL;
///instantiation of the receivers sub-blocks
receiver rx_LtoR;
///instantiation of the receivers sub-blocks
receiver rx_RtoL;
///stobe signal for the left to right couple of tx and rx
sc_signal<sc_bit> L_strobe_s;
///full signal for the left to right couple of tx and rx
sc_signal<sc_bit> L_full_s;
///stobe signal for the right to left couple of tx and rx
sc_signal<sc_bit> R_strobe_s;
///full signal for the right to left couple of tx and rx
sc_signal<sc_bit> R_full_s;
///data signal for the left to right couple of tx and rx
sc_signal<Packet> L_datac_s;
///data signal for the right to left couple of tx and rx
sc_signal<Packet> R_datac_s;
//SC_CTOR(wrapper_mod):tx_LtoR("tx_LtoR",5,3,7),tx_RtoL("tx_RtoL",3,5,7),rx_LtoR("rx_LtoR",5,3,100,25),rx_RtoL("rx_RtoL",3,5,100,25)
/// indication that we want to explicit the constructor
SC_HAS_PROCESS(wrapper_mod);
/// constructor of the wrapper
wrapper_mod(sc_module_name name_ , int N_left , int N_right) : sc_module(name_), m_N_left(N_left), m_N_right(N_right) ,tx_LtoR("tx_LtoR",m_N_left,m_N_right,7),tx_RtoL("tx_RtoL",m_N_right,m_N_left,7),rx_LtoR("rx_LtoR",m_N_left,m_N_right,100,25),rx_RtoL("rx_RtoL",m_N_right,m_N_left,100,25 |
tx_LtoR.datain(L_datain);
tx_LtoR.rst_n(rst_n);
tx_LtoR.clk(clkL);
tx_LtoR.full(L_full_s);
tx_LtoR.datac(L_datac_s);
tx_LtoR.strobe(L_strobe_s);
rx_LtoR.datac(L_datac_s);
rx_LtoR.strobe(L_strobe_s);
rx_LtoR.clk(clkR);
rx_LtoR.rst_n(rst_n);
rx_LtoR.dataout(R_dataout);
tx_RtoL.datain(R_datain);
tx_RtoL.rst_n(rst_n);
tx_RtoL.clk(clkR);
tx_RtoL.full(R_full_s);
tx_RtoL.datac(R_datac_s);
tx_RtoL.strobe(R_strobe_s);
rx_RtoL.datac(R_datac_s);
rx_RtoL.strobe(R_strobe_s);
rx_RtoL.clk(clkL);
rx_RtoL.rst_n(rst_n);
rx_RtoL.dataout(L_dataout);
}
|
Blinktest |
/* Signals */
sc_signal<bool> led {"led" |
__TBUF_ |
sc_in< sc_logic> A;
sc_in< sc_logic> E;
sc_out< sc_logic> Y;
SC_CTOR(__TBUF_){
SC_METHOD(eval);
sensitive << A << E;
}
void eval(void){
if (E->read() == SC_LOGIC_1){
Y->write(A->read());
} else {
Y->write(SC_LOGIC_Z);
}
|
wb_river_mc |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> ACK_I; // when asserted indicates the normal termination of a bus cycle
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<32>> ADR_O;
sc_out<sc_uint<2>> SEL_O; // select which words on DAT_O are valid
sc_out<bool> WE_O;
sc_out<bool> STB_O; // Master is talking on the bus
//interface with ICACHE
sc_in<sc_uint<32>> A_IC;
sc_in<bool> DTA_VALID_IC;
sc_out<sc_uint<32>> DT_IC;
sc_out<bool> ACK_IC;
//interface with DCACHE
sc_in<bool> DTA_VALID_DC;
sc_in<bool> READ_DC;
sc_in<bool> WRITE_DC;
sc_in<sc_uint<2>> SIZE_SEL_DC;
sc_in<sc_uint<32>> DT_DC;
sc_in<sc_uint<32>> A_DC;
sc_out<sc_uint<32>> DT_RM;
sc_out<bool> ACK_DC;
sc_out<bool> STALL_SW;
//interface with BCU
sc_in<bool> GRANT_I;
sc_out<bool> CYC_O;
//signals
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> future_state;
void new_state();
void state_transition();
void mae_output();
void trace(sc_trace_file*);
SC_CTOR(wb_river_mc)
{
SC_METHOD(new_state);
sensitive << CLK.pos() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.pos() << DTA_VALID_DC << DTA_VALID_IC
<< GRANT_I << WRITE_DC << READ_DC << ACK_I;
SC_METHOD(mae_output);
sensitive << current_state << DAT_I << ACK_I;
}
|
id_driver |
sc_out<bool> rst;
sc_out<bool> rf_access; // Enables rd/wr to the RFs while not in PIM mode
// sc_out<bool> rf_wr_nrd; // Signals if reading (low) or writing (high)
sc_out<bool> decode_en; // Enables decoding of the next CRF instruction
sc_out<uint8_t> pc_in; // Program Counter
sc_out<uint32_t> instr; // Instruction input from CRF
sc_out<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_uint<COL_BITS> > col_addr; // Address of the bank column
SC_CTOR(id_driver) {
SC_THREAD(driver_thread);
}
void driver_thread();
|